1374595 九、發明說明： f發明所屬之技術領域】 庙田本發⑽與靜電放電輯（ESDpiOteetiGn)有Μ，尤指-種 ^ESD Γ用絲^ A件之靜f放電賴？路之靜電放電偵測 (ESDdetechon)電路及其相關方法。 【先前技術】 隨著科技進步，積體電路穿 積體電路㈣麵知，各種術镇之顿魏。如熟悉 上，而為了要使晶片能接收電路可集積/成形於晶片 源），並能與外界其他電路/晶片^電壓源（例如偏壓電 導電的接墊(pad)。譬如說，交換貝料，晶片上會設有 設有電源接塾(powerpad)。除^專輪偏麗電壓’晶片上可 號接墊（signal pad)，亦即輪入/輪之外，在晶片上也設有訊 收輸入訊號及/或發出輸出tfLfJ出塾（I/〇pad)，用以接 這些導電的接㈣使日日日片得 連接。然而，當晶片在封梦、、 外界其他電路/晶片 、 須J試、運私 , 中，這些接墊也报容易因為連輸、加工、等過程 靜電的不當電力傳導至曰^ ^ ,的靜電電源接觸，而將 日日乃内部，祐、# 路的損毀，這種現象即為 亚進而導致晶片内部電 吓5月的靜電放電（咖， 7 1374595 meetiO_Statie Discharge)。因此，用來保護積體電路免受靜電 放電袖害之靜電放電保護電路(ESD pr〇tecti〇n drcuit)，也因此隨著 積體電路製程之進步而變得更加重要。 % • 通常在晶片的各接墊之間會設置有靜電放電防護電 路。此靜電放電防護電路的基本功能是，當晶片的兩接墊 間誤觸靜電電源時，靜電放電防護電路可在兩接墊間導通 鲁一個低阻抗的電流路徑，使靜電電源放電的電流能優先從 此一電流路杻流過而不會流人至晶片的其他内部電路；這 樣一來，就能保護晶片中的其他内部電路不受靜電放電影 響或由於大里的靜電放電電流（Esd current)而導致損壞。 一般而言，一靜電放電防護電路係由一靜電放電（暫態） 偵測電路（ESD transition detection circuit)以及一電源籍 制（power clamp)電路所構成。請參閱第i圖，第i圖所 示為習知靜電放電防濩電路的方塊示意圖。如第1圖所 • 示，靜電放電防護電路1〇〇包含有一靜電放電偵測電路110 以及-電源箝制電路120。如此之外，此靜電放電電路刚 係耦接於兩電源接墊（P〇werpad) vDD (電壓供應端）與 V s s (接地端）4間。 一 ， ㈣，隨料導體製㈣演進，使崎小尺相電晶體元# 來降低成本已成為各種電路設計技術中的基本需求。隨 製程由點一八製程、點一二製程一路演進至山+太 體 ’、丁不米，或所謂 8 1374595 的奈米先進製程(nano scale process);半導體元件的閘極氧化層 (gate oxuJe)厚度也隨之日益趨薄。除此之外，基於降低整體電路面 積及成本的考量：一般靜電放電防護電路中的靜電放電偵測電路 所具有之電容元件普遍採用金屬氧化層電容(M〇s capadt〇r，亦稱 之為金氧半導體電晶體電容)來加以實現，而非使用一般傳統的電 容元件。 明參閱第2圖，第2圖所示為另一習知靜電放電偵測電路2〇〇 的電路架構示意圖。如第2圖所示’靜電放賴測電路勘包含 有-容阻電路21〇卩及-反相電路22〇,用以產生一靜電放電觸 發訊號Itrigger，其中當靜電放電偵測電路2〇〇偵測到靜電放電事件 (ESD event)時，靜電放電觸發訊號丨吨㈣會由低邏輯準位轉換 至高邏輯準位以啟動後續的靜電放電防護元件（例如電源符制電 路）。靜電放電偵測電路200係連接於一第一電源接墊（亦即VDD 端）以及一第二電源接墊（亦即vss端）之間。在第2圖中，容 阻電路210包含有一阻抗元件211以及一金氧半導體電晶體電 谷（MOS capacitance)212，而反相電路22〇係由一 N型金氧 半導體電晶體222以及一 p型金氧半導體電晶體221所構 成。 然而’在利用由先進製程（nan〇scalepr〇cess)所形成之金屬 氧化層電容時’其閘極氧化層所具有之較薄厚度往往會使靜電偵 測電路產生嚴㈣漏電流’麵f流可驗得靜f放電防護電路 1374595 產生誤動作（malfiinction) ’使其在正常工 常邏輯，進而產生更嚴重的漏電流。作况下無法達到其正 而靜電防護電路之漏電流的現象係肇因 之容阻電路（請參閱第2圖）中的金氧半，.、静電放電偵測電路 採用了先進製程的薄氧化層元件，此電晶*電容212 體電谷212的閘極端往往會出現大量办、*氧半導體電晶 current)而導致晶片於正常 遂電流（tunneling -間之-連接端（其输於P^r;rt2r；r電路 控制端與N型金氧半導體電晶體22 日日體221之一 對於P型金氧半導體電晶體22丨之—第：制山端）的電壓相 於第-電源接墊）的電壓值 力而（其耦接 L, _ ^ , 口句個相對低的電壓，因 金氧二導體電晶體即導通而造成靜電放電觸發訊 位轉換至高邏輯準位，因此便錯誤地啟動 後續的靜電放電防護祕（例如電賴制電路）。換句料， 當靜電放電事件縣發生時，由於錢半導 212的穿遂電流將拉低連接端顺其連結容阻電路210以 及反相電路220)的電壓值，因而導致反相電路22〇於晶 片正常操作下無法有效地_，進而導致在兩電源接塾 (VDD端與:VSS端之間）有大量的漏電流產生。因此本發 月係提供新穎的靜電放電偵測電路，由於利用新的電路架 構，即使在採用先進製程之薄氧化層元件的狀況下，仍能 改善靜電放電防護電路於正常操作時的漏電流現象。 1374595 【發明内容】 因此本發_目的之-係提供具有柯魏結構之靜電放電 侧電路及相關技術，以克服習知技術中由於靜電放電防護電路 點&冑偵測電路於先進製程之下會產生大量漏電流現象的缺 發明之靜電放電偵測電路，其容阻電路並未直接接 地* ’而辟·山 9田使用偏壓電路，便可減少容阻電路之金氧半導 ^雷曰吁 電容兩端的壓差’從而改善先進製程中靜電放電 偵測電路的漏電流現象。 發明之一實施例，其係揭露一種靜電放電偵測 電 〇 +女 一 電放電偵測電路包含有：一第一電源接墊、一 第電源镇塾、包含有一阻抗元件以及一電容元件之一容 阻電路、〜 碉毛電路、—偏壓電路、一第一連接端與一第 '—連接端0 _>·方贷雨 邊弟一電源接墊係用以接收一第一供應電壓； '原接墊係用以接收不同於該第一供應電壓之一第 一供應電麼.j^· a ^ + ，忒谷阻電路之阻抗元件，其耦接於該第一電 '、〃、噙第一連接端之間；該電容元件，其柄接於該第 一端點與兮楚_ — ^ ^弟一^點之間；該觸發電路，耦接於該第一電 源接墊、診 ^ 一俨f盥/ 冤源接墊以及該容阻電路，用來依據該第 „, . ^第一端點之電壓準位來產生一靜電放電觸發訊 ； '居偏壓電路’耦接於該第一電源接墊以及該第二 11 電源接墊之間，用以提供一偏壓電壓予該第二端點。 …根據本發明之另一實施例，其係揭露一種應用於靜電放 電偵測之方法，該方法包含有：提供—容阻電路，其巾該容阻電 5包含有-阻抗雜以及-電容祕，該電容元件，係輕接於 -第-供應與-第-端點之間，而該電容元件，雜於該第 -端點與—第二端點之間，其中該第二端點未直接連接於不同於 該第一供應電壓之一第二供應電壓； 依據該第-與該第二端點之㈣準位來產生—靜電放電觸發 訊號；以及提供一偏壓電壓至該第二端點。 藉由上述之電路設計與相關方法，可解決先進製程下之靜電放 電谓測電路由於採用薄氧化層金氧半導體電晶體元件而導致 正常操作下的漏電流問題。 【實施方式】 …在說明書及後續的巾請專利範圍當中使用了某些詞彙來指稱 特疋的7L件。所屬領域中具有通常知識者應可理解，製造商可能 會用不同的糊來稱呼同—個元件。本說明書及後續的中請專利 犯圍並不以名制差異來作為區分元件的对，而是以树在功 能上駐異來作為區分醉則。在通篇制書及_的請求項當 中所提及的「包含」係為—開放式的用語，故應解釋成「包含但 j374595 不限定於」。以外，「耦接」一詞在此係包含任何直接及間接的電 氣連接手段。因此，若文中描述一第一裝置耦接於一第二裝置， 則代表該第一裝置可直接電氣連接於該第二裝置，或透過其他裝 ' 置或連接手段間接地電氣連接至該第二裝置。 請參閱第3圖，第3圖所示為本發明靜電放電偵測電路之一 第一實施例的電路架構示意圖。如第3圖所示，靜電放電偵測電 φ 路300係耦接於一第一電源接墊301與一第二電源接墊302之間， 在本實施例中，第一電源接墊301為一 Vdd接墊（用以提供第一 供應電壓vDD)’而該第二電源接墊302為一 Vss接墊（用以提供 第二供應電壓Vss，例如接地電壓;)。靜電偵測電路3⑻包含有一 偏壓電路（biascircuit) 310、一容阻電路(RCcircuit)32〇以及一觸 發電路330。在本說明書後續的說明之中，靜電放電偵測電路之容 阻電路中的電容元件皆以金氧半導體電晶體電容來加以實 &，以及容阻電路中的阻抗元件係以—電阻元件來加 •以實施。 除此之外，靜電放電偵測電路之觸發電路中係包含有不同導 電型之金氧轉體電晶體元件，也就是說，觸發電路巾同時採用 了 N型以及P型之錢半導體電晶體元件4者，本發明之電路 架構以及相瞧術係翻制先進餘她pm·)之元件 來加以實施。請注意，上述僅作域例說明之用，並不為本發明 的限制條件之一。 13 1374595 請參閱第3圖，在本實施例中，容阻電路32〇包含有一阻抗 兀件321以及一電容元件322 ’而阻抗元件321為一電阻電容元 件322係以採用先進製程(nan〇 scak)之金氧半導體電晶體電容 (MOS capacitor)來加以實施。觸發電路33〇包含有一第—金氧 半導體電晶體331以及-第二金氧半導體電晶體332,對第一金氧 半導體電晶體331而言，其一控制端（閘極）墟於一第一端點 ^ ’其—第一連接端（源極）雛於第一電源接墊30卜以及其 了第二連接端（汲極）用以輸出靜電放電觸發訊號W給後續的 靜電放電防遵7〇件（例如電源箝制電路）以於靜電放電事件發生 時旁通靜電放電電流，如圖所示，靜電放電觸發訊號^係_ 輸出。此外，對於觸發電路之第二金氧半導體電晶體 々而。’其-控制端（亦即間極）輕接於一第二端點灿，其一 第連接知（及極）轉接於第一金氧半導體電晶體別之第二連 f:以及其—第二連接端（源極）_於第二電源接塾302。在 貫知例中，第一金氧半導 體電晶體來實作而第331係以一p型之金氧半導 氧半導體電晶體來實作，㈣兩今晶體332則是以—N型之金 不同導電型之金氧半導體=金__體331、332係為 圖所，她於^°靜較電侧祕（如第2 於本實施例中，偏電偵測1路_另包含有偏壓電路310， 1 路 310 係為一分壓電路（voltagedivider)， 1374595 用以根據第一電源端301與第二電源端302之供應電壓（例如v〇d 以及vss)提供容阻電路320之電容元件322下端（亦即第二端點 Nb) -個高於第二魏接塾302之供應電壓（例如Vss)的偏麼 * 電壓’也就是說，電容元件似兩端間的跨壓分別為第一端點他 ..以及第二端點Nb之間的電壓差，此電壓差會小於第—電源接墊 301的供應電壓（例如Vdd)以及第二鶴接# 3〇2的供應電壓（例 如vss)間的電壓差。在本實施例中，偏壓電路31〇係以五個具有 • 二極體接法形式（diode-c_ected )的電晶體元件311來加以實施， ，得第二端點Nb的電壓值為Vdd和〜之間的一個分壓（^ 不過分壓電路的架構與採用之元件並不為本發明的限 制條件之一，任何其他可產生分麗之電路架構皆屬於本發明的設 計變化之-；而分壓元件的數目亦不為本發明的限制條件之一。 靜電放電制電路於正常操作下的電路雜以及靜電放 # t事件發生時的電路狀態將於後續之揭露中詳細說明。 當一靜電放電事件發生時，第—電源接塾則與第二 =二02Γ的跨壓急遽升高，對於第-金氧半導體電 = 容阻㈣320之電容元件322⑽半導 接:;= 速反應’以致於第-金氧半導體電晶體 -連㈣紐將高於第 一嫩電觸㈣w(㈣輪崎職峡會由低^ 15 1374595 輯準位轉換至高邏輯準位）。對於第一端點Na來說，由於電 容元件322來不及對電壓急升進行相對應的反應，使得第 一端點Na的電壓會暫時維持於第一電源接墊301原本之電 壓值（亦即趨近VDD)。由於第一金氧半導體電晶體331因為 其控制端與第一連接端的兩端電壓差而導通，使端點Nc的電壓 隨之升高進而觸發靜電放電防護電路之電源箝制電路（未 顯示於圖中），使得電源箝制電路導通一低阻抗電流路徑以 疏導靜電放電電流來達成靜電防護的目的。 靜電放電偵測電路300在正常運作時，偏壓電路310 提供分壓電壓予第二端點Nb(亦即電容元件322之一端）， 使得第二端點Nb偏壓於一個大於第二電源接墊302之電壓 (亦即VSS)的較高電壓位準。如第3圖所示，於正常操 作之下，由於偏壓電路310所提供的偏壓電壓，使得第二 端點Nb之電壓可導通第二金氧半導體電晶體332 (第二金 氧半導體電晶體332係一 N型金氧半導體電晶體332元 件），此時因為第二端點Nb之電壓為一較高位準（相較於 第二電源接墊302之電壓準位），經由適當的分壓設計，第 一端點Na與第二端點Nb間的跨壓於正常模式之下不大， 因此先進製程之金氧半導體電晶體電容（亦即電容元件 322)的閘極漏電流現象也隨之改善，並使得第一端點Na 之電壓得以維持在一個近似於第一電源接墊301之供應電 壓（VDD)的狀態，由於第一金氧半導體電晶體331係為 16 1374595 一 P型金氧半導體電晶體，故此一接近於VDD之電壓將會 關閉第一金氡半導體電晶體331。換句話說，由於先進製 程之金氧半導體電晶體電容（亦即電容元件322)兩端（第 . 一端點Na與第二端點Nb)之跨壓減少，進而可有效地關 _ 閉正常操作狀態下的第一金氧半導體電晶體331，避免因 為漏電流而不當產生靜電放電觸發訊號而觸發電源箝制電 路，因此，可防止靜電放電防護電路產生誤動作，避免處 在不正常邏輯狀態。 請同時參閱第4圖與第3圖，第4圖為本發明第一實 施例之靜電放電偵測電路模擬靜電放電事件發生時觸發電 流的示意圖。如第4圖所示，此模擬係固定靜電放電彳貞測 電路300之容阻電路320的RC時間常數（RC constant) 為50ns以及固定第一金氧半導體電晶體331之通道長度(L) 為0.12um，而調變第一金氧半導體電晶體331之通道寬度 • (W)而產生的數據(請參考曲線1〜曲線7)。請參閱第5圖與 第3圖，第5圖為本發明第一實施例之靜電放電偵測電路 模擬正常操作狀態（normal operation )下漏電流狀態的示 意圖。如第5圖所示，此模擬係當第一電源端301之第一 - 供應電壓（亦即VDD)固定為1伏特時，靜電放電偵測電 . 路300中漏電情形的數據（請參考曲線1〜曲線2)。 由前述之揭露可清楚得知，當積體電路設計中需要採用先進 17 1374595 製程之薄閘極氡化層元件時，採用第3圖所示之電路架構可在兼 顧電路面積的同時實現靜電放電的防護功能，且在晶片正常 操作時可以使習知技術由於採用先進製程之薄閘極氧化層元 件（尤其是金氧半導體電晶體電容）所產生的漏電流有效地減少， 進而改善了靜電放電防護電路的整體性能。 請參閱第6圖，第6圖所示為本發明靜電放電偵測電路之一 第一貫^例的電路架構示意圖。如第6圖所示，靜電放電偵測電 路600係耦接於一第一電源接墊6〇1與一第二電源接墊之間， 在本實施例中，第一電源接墊601為一 YDD接墊（用以提供第一 供應電壓vDD)’而第二電源接墊602為一 vss接墊（用以提供第 二供應電壓Vss，例如接地電壓）。靜電偵測電路6〇〇包含有一偏 壓電路610、一容阻電路620以及一觸發電路63〇。在本實施例中， 各阻電路620係耦接於第一電源接墊6〇1以及一連接端灿之間， 在容阻電路620内包含有一阻抗元件621以及一電容元件622。此 外，觸發電路630耦接於第一電源接墊6(U、第二電源接墊邠二、 容阻電路620以及偏壓電路61〇。 在此一實施例中，觸發電路63〇採用兩個p型之金氧半導體 電晶體（第-金氧半導體電晶體如以及第二金氧半導體電晶體 632)叠接，以及另使用-N型之今氧半導體電晶體（亦即第三金 氧半導體電晶體633)以構成—個具有雙重關之觸發反相器 (triggerhwerter)。如帛6圖所示，觸發電路㈣之輕接關係如口下所 18 1374595 ，：第一金氧半導體電晶體631之一控制端（閉極）雛於第一 々 产、而/、第一連接端（源極）耦接於第一電源接墊601 ; 第一金^半導體電晶體632之一控制端（閉極）搞接於第二端點 第連接^ (源極）〶接於第—金氧半導體電晶體⑶之 ^ 一第二連接端（汲極），而其一第二連接端（沒極）係用以在靜電 放電事件產生時觸發靜電放電觸發訊號W以導通後續的靜電放 電防護兀件（例如電源箝制電路），如圖所示，觸發靜電放電觸發 • 赠丄啊係由端點⑹所輸出；第三金氧半導體電晶體633，其 -控制端（閘極）叙接於第二端點灿，一第一連接端（沒極）搞 接於第二金氧铸體電晶體632之第二連接端，而其一第二連接 端（源極）則耦接於第二電源接墊602。 請繼續參閲第6圖，偏壓電路⑽包含有一反相器615以及 -阻抗兀件611。然而請注意到，在本實施例中採用阻抗元件6ιι 僅作為關說明之用’在其他實施例中，亦可依據設計需求而省 鲁略阻抗元件611的使用，此一設計變化亦屬於本發明的設計範缚。 在偏壓電路610中，反相器615包含有一 p型金氧半導體電晶體 612以及一N型金氧半導體電晶體613。反相器615耦接於第二端 點Nb與觸發電路630之第二金氧半導體電晶體632的第二連接端 •(亦即端點Nc)之間。在本實施例中，觸發電路63〇所構成之觸 發反相器(triggerinverter)與偏壓電路610中的反相器（偏壓反相 器）615形成了 一迴授控制機制(feedback control scheme)，使得反 相器615會依據靜電放電觸發訊號所提供的回授電壓準位來 19 康生-偏壓电整至第二端點灿，以減少電容元件622的兩端壓降 (亦即第-、第二端點Na與Nb之間的電壓差）。 然而’在本發明的其他實施例中，靜電放電細電路600亦 <採用々壓电路來作為偏㈣路，舉例來說，可採用第—實施例 中之偏壓電路310來取代第二實施例之偏壓電路61()，也就是說， 在不違反本發明之精神的情況之τ，可爾設計需求的不同而採 用其他偏壓電路的電路組態在靜電放電情測電路_之中，而這 些設計變化亦屬於本發明的範嘴。 靜電放電細彳電路_於正常操作下的電路狀態以及靜電放 電事件發生日㈣電路狀態將於後續之揭露巾詳細說明。 請參閱第6圖’當一靜電放電事件發生時，第一電源 接墊接墊601與第二電源接墊接墊6〇2之間的跨壓急遽升 高，由於容阻電路62〇所造成的RC：延遲（RCdeIay)，使 得第-金氧半導體電晶體631由於其第—連接端（祕）與第一 端點Na之間的壓差而導通，而第一金氧半導體電晶體⑶的導通 會進-步地拉高第二金氧半導體電晶體632之第一連接端（沒極） 的電壓準位’故第二金氧半導體電晶體纪2接著便會導通。隨著 苐-、第-金氧半導體電晶體63卜632的導通將提升端點Nc.(亦 P第-金氧半導體電晶體632之第二連接端）#電壓而提供靜電 敌電觸發訊號ItriggCT (由低賴準㈣換至高邏輯雜）至電源籍 1374595 制電路（未顯示於圖中）以排除靜電放電電流。當端，點Nc的電塵 提升時’此電壓亦回授至麵電路61〇之反相器仍㈣通_ 金氧半_電晶體613，隨著N型金氧半導體電晶體613的導通， 第二端點Nb的碰會降低至—雜低之電鮮位（例如接近％ 電座的電齡位），*先進縣之薄祕氧化層元件之本身特性， 由於電容元件622的兩端屬差增加，故電容元件必將產生大量 的閘極漏電流，從而進一步地拉低第一端點Na的電鮮位，因此 在靜電放電事件發生時，第一端點Na與第二端點灿的較低電愿 準位將使得觸發電路63G之第—金氧半導體電晶體631與第二金 氧。半導體電晶體6M皆維持導通的狀態而繼續提供靜電放電觸發 訊號W至後續的靜電放電防護元件（例如電源箝制電路） 以旁通靜電放電電流來達成靜電防護的目的。 睛繼續參閱第6圖，當靜電放電偵測電路_在正常 運作時，觸發電路630中的第三金氧半導體電晶體633會導通 而使端點Nc趨近於第：電源接塾6〇2所提供的電壓（Μ，如此 —來’藉由回授機制’端點Nc的低電壓會導通偏壓電路61〇之反 相盗615中的P型金氧半導體電晶體612，此時，由於p型金氧半 導體電晶體犯的導通’第二端點m㈣壓會被拉升至一個接近 第—供應電壓（VDD)的電壓準位，由於在正常操作時，第-端點 Na亦處於-個近似於第一供應電壓(v的電壓準位，相較於習知 技術，這兩個端點Na與N b之間的跨壓便可減少（既然端點 ^與灿間的電壓皆近似於VDD )，-方面可降低了容阻電 21 1374595 路62〇之電容元件32〇(由於在本發明皆假設採用先進製程之薄閘 極金屬氧化層電容來實施)的閘極漏電流，另—方面更可有效地關 閉觸發電路630之第一金氧半導體電晶體631與第二金氧半導體 電晶體632。也就是說，在本實施例中，於正常操作之下， 因為先進製程之金氧半導體電晶體電容（亦即電容元件 622 )兩端之跨壓減少，從而避免因為漏電流而不當地產生 靜電放電觸發訊號來觸發電源箝制電路，因此，可防止靜 電放電防護電路產生誤動作’避免處在不正常邏輯狀態。 請同時參閱第7圖與第6圖，第7圖為本發明第二實 施例之靜電放電偵測電路模擬靜電放電事件發生時觸發電 流的示意圖。如第7圖所示，此模擬係固定靜電放電债測 電路600之容阻電路620的RC時問當叙炎， 亏間㊉数為25ns以及固定 第-金氧半導體電晶體之通道長度⑸為〇伽，而調 變第:金氧料體電晶體631與第二金氧半導體電晶體㈣之通 道寬度（W)而產生的數據(請參考曲皤 姑。、 曲線1〜曲線5)。請參閱 弟8圖與苐6圖，第8圖為本發明窜一凉 币一列之靜電放電 偵測電路模擬正常操作狀態下漏電湳 _ 电仙·狀態的示意圖。如第 8圖所不，此模擬係當第一電源端6 &第一供廣電壓 (VDD)固定為i伏特時’靜電放電_電路^之 形的數據(請參考曲線1〜曲線2卜 卜 由前迷之減可清楚得知，.當積體魏設計巾㉞採用先進 22 1374595 製私之薄閘極氧化層元件時，第6圖所示之電路架構利用閂鎖 (latch)結構（由觸發電路63〇與偏壓電路61〇中的反相器結構 所形成）與偏壓電路6i 〇不僅於正常操#時降低了靜電放電侧 電路600㈣電济L ’亦可於靜電放電事件發生時加速導通電源箝 制電路以猶靜電放電電流。在本實補巾，當靜電放電事件產 生恰，靜電放電偵測電路600產生大量的閘極漏電流，並將電容 元件622之閘極漏電流變成可持續疏導靜電放電電流的一個抱紐 (藉由讓第-金氧半導體電晶體631以及第二金氧半導體電晶體 632持續導通）’換言之，第6圖所示之電路架構利用先進製程之 金氧半導體電晶體電容本身的漏電流來使得觸發電路能持 續產生靜f放電觸發喊來啟動後續的靜電放電防護元件（例如 例如電源箝制電路而這樣的機制，更可在適當的狀況下，將容 阻電路620之R C日销f數的數值純姆而娜持靜電放電防 護的功效；在這些情況中靜電放電防護電路的電路面積可因而縮 減並降低成本。 請注意，在林背本㈣之精神之下，其他的設計變化亦 是可行的’舉例來說’在本發明之其他實施例中，靜電放電偵測 電路300之偏壓電路310亦可用第6圖所示之偏壓電路⑽來加 以取代，此外’偏壓電路61〇之阻抗元件611為一選擇性使用 (optional)之7L件。這些相關的設計變化皆屬於本發明的範鳴。 總而言之，相較於習知靜電放電偵測電路，本發明所 23 提供之靜電放電防護技術可藉由避免讓容阻電路直接接地 ssh)而免除讓其内之電容元件由於大量的跨麼而造成 ‘=面的影響，亦可在靜電放電事件發生時提升疏導靜電滅 電電流之能力並同時兼顧電路面積以及成本的考量。如前 逑之各個實施例所示，本發明靜電放電偵測電路中的备裀 電路，構皆可採用各種其他等效電路來實現。舉例來説， 第-實施例之分壓電路亦可採用電阻元件來作為分壓元件 _ 而達到提供電容元件一個相異於Vss電麗之電壓準位。摻 δ之，任何採用前面敘述過之技術來降低容阻電路兩端跨廖以 改善靜電放電制電路於正常操作時肇因於閘極漏電流而導致之 問題的電路架構’皆符合本發明之精神並落於本發明的範鳴之中。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 園所做之均等變化與修姊，皆應屬本發明之涵蓋範圍。 _ 【圖式簡單說明】 第1圖為習知靜電放電防護電路的方塊示意圖。 第2圖為另-習知靜電放電價測電路的電路架構示意圖。 第3圖為本發明靜電放電細電路之_第—實施例的電路架麟系 意圖。 〃 第4圖為本發明第-實施例之靜電放電細電路模擬靜電 事件發生時觸發電流的示意圖。 24 1374595 第5圖為本發明第—實施例之靜電放電_電賴擬正常操作狀 態下漏電流狀態的示意圖。 第6圖為本發明靜電放電偵測電路之—第二實施綱電路架構示 意圖。 第7圖為本發明第二貫施例之靜電放電伽彳電路模擬靜電放電事 件發生時觸發電流的示意圖。 第8圖為本發明第二實關之靜電放制測電賴擬正錄作狀 態下漏電流狀態的示意圖。 【主要元件符號說明】 100 靜電放電防護電路 110、200、300 、600靜電放電偵測電路 120 電源箝制電路 210、320、620 容阻電路 220、330、630 觸發電路 230 連接端 301 、 601 第一電源接墊 302 、 602 第二電源接墊 311 電晶體元件 32卜 611、621 阻抗元件 322 ' 622 電容元件 33 卜 631 第一金氧半導體電晶體 25 1374595 332 ' 632 第二金氧半導體電晶體 612 P型金氧半導體電晶體 613 N型金氧半導體電晶體 615 反相器 633 第三金氧半導體電晶體 261374595 IX. Description of the invention: The technical field to which f invention belongs] Miao Tian Benfa (10) and ESD (ESD) have a flaw, especially the kind of ^ESD Γ ^ ^ ^ ^ ^ ^ ^ ^ ^ Electrostatic discharge detection (ESDdetechon) circuit and related methods. [Prior Art] With the advancement of science and technology, the integrated circuit is embedded in the body circuit (4). As is familiar, in order to enable the chip receiving circuit to be accumulated/formed to the wafer source), and to other external circuits/chips (such as biased electrically conductive pads), for example, swapping bays The material is provided with a power pad on the wafer. In addition to the special wheel of the special voltage, the signal pad, that is, the wheel/wheel, is also provided on the wafer. The input signal and/or the output tfLfJ output (I/〇pad) are used to connect these conductive connections (4) to connect the day and day. However, when the chip is in the dream, other circuits/wafers, It is necessary to test, transport, and privately. These pads are also easy to report because of the improper transmission of static electricity from the process of transmission, processing, etc. to the electrostatic power supply of the 曰^^, and the day is the internal, the road of the Damage, this phenomenon is the electrostatic discharge that causes the internal internal shock of the wafer to scare May. (Cal, 7 1374595 meetiO_Statie Discharge). Therefore, the electrostatic discharge protection circuit (ESD pr) used to protect the integrated circuit from electrostatic discharge sleeves 〇tecti〇n drcuit), so with the integrated electricity The progress of the process has become more important. % • An ESD protection circuit is usually placed between the pads of the wafer. The basic function of the ESD protection circuit is when the two pads of the chip accidentally touch the electrostatic power supply. The ESD protection circuit can conduct a low-impedance current path between the two pads, so that the current discharged by the electrostatic power source can preferentially flow from the current path without flowing to other internal circuits of the chip; It can protect other internal circuits in the chip from electrostatic discharge or damage due to large electrostatic discharge current (Esd current). Generally, an ESD protection circuit is detected by an electrostatic discharge (transient) The circuit (ESD transition detection circuit) and a power clamp circuit are formed. Please refer to the i-th diagram, which is a block diagram of a conventional electrostatic discharge anti-smash circuit. The ESD protection circuit 1A includes an ESD detection circuit 110 and a power supply clamping circuit 120. In addition, the ESD circuit It is coupled between two power pads (P〇werpad) vDD (voltage supply terminal) and V ss (ground terminal) 4. First, (four), with the conductor system (four) evolution, so that the small size phase transistor yuan # come Reducing the cost has become a basic requirement in various circuit design techniques. With the process of the process from point to eight processes, point one or two processes all the way to the mountain + Tai body', Ding Bumi, or the so-called 8 1374595 nano-advanced process (nano scale) The thickness of the gate oxide layer (gate oxuJe) of the semiconductor device is also becoming thinner. In addition, based on the consideration of reducing the overall circuit area and cost: the electrostatic discharge detection circuit in the general electrostatic discharge protection circuit has a metal oxide layer capacitor (M〇s capadt〇r, also known as Instead of using conventional conventional capacitive elements, MOS transistors are used. Referring to FIG. 2, FIG. 2 is a schematic diagram showing the circuit structure of another conventional electrostatic discharge detecting circuit 2〇〇. As shown in FIG. 2, the 'electrostatic discharge measuring circuit includes a capacitance circuit 21〇卩 and an inverter circuit 22〇 for generating an electrostatic discharge trigger signal Itrigger, wherein the electrostatic discharge detecting circuit 2〇〇 When an ESD event is detected, the ESD trigger signal (4) will be switched from a low logic level to a high logic level to activate a subsequent ESD protection component (such as a power supply circuit). The ESD detecting circuit 200 is connected between a first power pad (ie, VDD end) and a second power pad (ie, a vss end). In FIG. 2, the resistance circuit 210 includes an impedance element 211 and a MOS capacitance 212, and the inverter circuit 22 is composed of an N-type MOS transistor 222 and a p. The MOS transistor 221 is formed. However, 'when using the metal oxide layer capacitor formed by the advanced process, the thin thickness of the gate oxide layer tends to cause the electrostatic detection circuit to generate a strict (four) leakage current 'surface f flow. It can be verified that the static f discharge protection circuit 1374595 generates a malfunction (malfiinction) 'making it in normal working logic, which in turn produces more serious leakage current. Under the condition that the leakage current of the positive and static protection circuit cannot be reached, the golden oxide half of the resistance circuit (see Figure 2) is used. The electrostatic discharge detection circuit adopts the advanced process thin. Oxide layer component, the gate terminal of the electro-crystal*capacitor 212 body-electric valley 212 tends to have a large amount of current, *oxygen semiconductor current crystal), resulting in the wafer in normal 遂 current (tunneling - the connection end (which is lost to P) ^r; rt2r; r circuit control terminal and N-type MOS transistor 22 one of the solar body 221 for the P-type MOS transistor 22 第 - the: mountain end) voltage phase of the first - power pad The voltage value of the voltage (which is coupled to L, _ ^, a relatively low voltage of the mouthpiece, because the gold-oxygen two-conductor transistor is turned on, causing the electrostatic discharge trigger signal to switch to a high logic level, thus erroneously starting Subsequent electrostatic discharge protection (such as electric circuit). When the electrostatic discharge event occurs, the current of the carbon semiconductor 212 will pull down the connection and connect the resistance circuit 210 and reverse the phase. The voltage value of circuit 220), thus causing the inverse _ 22〇 circuit can not be effectively under normal operation the wafer, leading to the two power connection Sook (VDD terminal and: between VSS terminal) of a large leakage current. Therefore, this month provides a novel electrostatic discharge detection circuit. Due to the new circuit architecture, the leakage current of the ESD protection circuit during normal operation can be improved even under the condition of using thin oxide elements of advanced processes. . 1374595 SUMMARY OF THE INVENTION Therefore, the present invention provides an electrostatic discharge side circuit having a Kewei structure and related technologies to overcome the prior art process of electrostatic discharge protection circuit point & detection circuit under advanced process. Insufficient electrostatic discharge detection circuit that generates a large amount of leakage current, its resistance circuit is not directly grounded* 'But the mountain 9 field uses a bias circuit to reduce the gold-oxide semi-conductance of the resistance circuit ^ Thunder calls the pressure difference across the capacitor' to improve the leakage current of the ESD detection circuit in advanced processes. An embodiment of the invention discloses an electrostatic discharge detecting device + a female electric discharge detecting circuit comprising: a first power pad, a first power supply, one impedance element and one capacitor element a resistor circuit, a bristles circuit, a bias circuit, a first connection end and a first 'connection terminal 0 _> a square power supply is used to receive a first supply voltage; The original pad is configured to receive a first supply voltage different from the first supply voltage. The impedance element of the valley resistance circuit is coupled to the first power ', 〃, Between the first connection end; the capacitive element, the handle is connected between the first end point and the _ ^ _ ^ ^ ^ ^ ^ point; the trigger circuit is coupled to the first power pad, diagnosis ^ 俨 盥 盥 冤 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 容 容 容 容 容 容 容 容 容 容 容 容 容 容 容 容 容 容 容 容 容 容 容 容 容 容Between the first power pad and the second 11 power pad, for providing a bias voltage to the second end point. Another embodiment of the present invention discloses a method for applying electrostatic discharge detection, the method comprising: providing a capacitance-resisting circuit, wherein the capacitive resistance 5 includes a -impedance impurity and a capacitance secret, The capacitive element is lightly connected between the -th supply and the -end terminal, and the capacitive element is interposed between the first end point and the second end point, wherein the second end point is not directly connected And a second supply voltage different from the first supply voltage; generating an electrostatic discharge trigger signal according to the (four) level of the first and the second end point; and providing a bias voltage to the second end point. Through the above circuit design and related methods, the problem of leakage current under normal operation due to the use of a thin oxide MOS transistor component can be solved by the electrostatic discharge measurement circuit under the advanced process. [Embodiment] ... Subsequent to the scope of the patent, some terms are used to refer to the characteristic 7L parts. Those of ordinary skill in the art should understand that the manufacturer may use different pastes to refer to the same component. In the continuation of the patent, the patent is not based on the difference of the name system as the pair of distinguishing elements, but the tree is functionally different as the difference between the drunk. In the whole book and the request of _ "Include" is an open-ended term, so it should be interpreted as "including but j374595 is not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device, or electrically connected to the second device indirectly through other devices or connecting means. Device. Please refer to FIG. 3. FIG. 3 is a schematic diagram showing the circuit structure of the first embodiment of the electrostatic discharge detecting circuit of the present invention. As shown in FIG. 3, the ESD detecting circuit 300 is coupled between a first power pad 301 and a second power pad 302. In this embodiment, the first power pad 301 is A Vdd pad (to provide a first supply voltage vDD)' and the second power pad 302 is a Vss pad (to provide a second supply voltage Vss, such as a ground voltage;). The static electricity detecting circuit 3 (8) includes a bias circuit 310, a RC circuit 32A, and a trigger circuit 330. In the subsequent description of the present specification, the capacitive elements in the capacitance-resistance circuit of the electrostatic discharge detecting circuit are implemented by a MOS transistor, and the impedance element in the resistance circuit is a resistive element. Plus to implement. In addition, the trigger circuit of the ESD detection circuit includes different oxygen-conducting transistor elements of different conductivity types, that is, the trigger circuit towel uses both N-type and P-type semiconductor transistor elements. 4, the circuit architecture of the present invention and the components of the 瞧 瞧 先进 先进 她 她 她 她 她 她 。 。 pm pm pm pm pm pm pm pm It should be noted that the above description is only for the purpose of description of the domain, and is not one of the limitations of the present invention. 13 1374595 Referring to FIG. 3, in the embodiment, the capacitive resistor circuit 32 includes an impedance element 321 and a capacitive element 322', and the impedance element 321 is a resistive capacitive element 322 for adopting an advanced process (nan〇scak). The MOS transistor is implemented. The trigger circuit 33A includes a first oxynitride transistor 331 and a second MOS transistor 332. For the first MOS transistor 331, a control terminal (gate) is first. End point ^ 'the first connection end (source) is entangled in the first power supply pad 30 and its second connection end (drain) for outputting the electrostatic discharge trigger signal W for subsequent electrostatic discharge prevention 7 A device (such as a power clamp circuit) bypasses the electrostatic discharge current when an electrostatic discharge event occurs, as shown in the figure, the electrostatic discharge trigger signal is output. In addition, the second MOS transistor for the trigger circuit is degraded. 'The control terminal (ie, the interpole) is lightly connected to a second terminal, and the first connection is connected to the second connection of the first MOS transistor: and The second connection end (source) is connected to the second power connection 302. In the conventional example, the first MOS transistor is implemented and the 331th is implemented as a p-type MOS semiconductor transistor. (4) The two crystals 332 are made of -N type gold. The different conductivity type of MOS semiconductor = gold __ body 331, 332 is the map, she is static on the side of the static side (as in the second embodiment, the polarization detection 1 way _ another contains bias The voltage circuit 310, the one channel 310 is a voltage divider, and the 1374595 is used to provide the resistance circuit 320 according to the supply voltages (eg, v〇d and vss) of the first power terminal 301 and the second power terminal 302. The lower end of the capacitive element 322 (ie, the second end point Nb) - a bias voltage higher than the supply voltage (eg, Vss) of the second interface 302 (that is, the capacitive element is like the voltage across the ends) The voltage difference between the first end point and the second end point Nb, respectively, which is smaller than the supply voltage of the first power pad 301 (for example, Vdd) and the supply of the second crane #3〇2 The voltage difference between voltages (e.g., vss). In the present embodiment, the bias circuit 31 is in the form of two diodes (diode-c_ected). The transistor element 311 is implemented to obtain a voltage value between the second terminal Nb and a voltage division between Vdd and ~ (but the structure of the voltage dividing circuit and the components used are not limited by the present invention) One of the conditions, any other circuit structure that can produce a beautiful one is a design change of the present invention; and the number of voltage dividing elements is not one of the limitations of the present invention. The circuit of the electrostatic discharge circuit under normal operation The circuit state at the time of the occurrence of the miscellaneous and electrostatic discharge # t event will be described in detail in the subsequent disclosure. When an electrostatic discharge event occurs, the first power supply junction is increased with the second = 02 Γ cross-pressure, for the first - MOS Semiconductor = Capacitance (4) 320 Capacitor Element 322 (10) Semi-conducting: ; = Fast response 'so that the MOS transistor - even (four) New will be higher than the first tender electric contact (four) w ((4) Rokaya Gorge It will be converted from a low level of 15 1374595 to a high logic level. For the first terminal Na, since the capacitive element 322 does not respond to the voltage surge, the voltage of the first terminal Na will temporarily Maintained on the first power pad The original voltage value of 301 (that is, approaches VDD). Since the first MOS transistor 331 is turned on because of the voltage difference between the control terminal and the first terminal, the voltage of the terminal Nc rises and triggers. The power clamp circuit of the ESD protection circuit (not shown) allows the power clamp circuit to conduct a low impedance current path to divert the electrostatic discharge current for electrostatic protection. The ESD detection circuit 300 is in normal operation. The voltage circuit 310 provides a divided voltage to the second terminal Nb (ie, one end of the capacitive element 322) such that the second terminal Nb is biased to a voltage greater than the voltage of the second power pad 302 (ie, VSS). High voltage level. As shown in FIG. 3, under normal operation, the voltage of the second terminal Nb can turn on the second MOS transistor 332 (the second MOS semiconductor) due to the bias voltage provided by the bias circuit 310. The transistor 332 is an N-type MOS transistor 332 device. At this time, because the voltage of the second terminal Nb is at a higher level (compared to the voltage level of the second power pad 302), In the voltage division design, the voltage across the first terminal Na and the second terminal Nb is not large under the normal mode, so the gate leakage current of the MOS transistor (ie, the capacitor element 322) of the advanced process is high. The improvement is also made, and the voltage of the first terminal Na is maintained at a state similar to the supply voltage (VDD) of the first power pad 301, since the first MOS transistor 331 is 16 1374595-P. A MOS transistor, such that a voltage close to VDD will turn off the first MOSFET semiconductor 331. In other words, since the voltage across the MOS transistor capacitor (ie, the capacitor element 322) of the advanced process is reduced (the first terminal Na and the second terminal Nb), the normal operation can be effectively turned off. The first MOS transistor 331 in the state avoids triggering the power supply clamping circuit due to the leakage current and the electrostatic discharge triggering signal, thereby preventing the electrostatic discharge protection circuit from malfunctioning and avoiding an abnormal logic state. Please refer to FIG. 4 and FIG. 3 at the same time. FIG. 4 is a schematic diagram of the trigger current when the electrostatic discharge detecting circuit of the first embodiment of the present invention simulates an electrostatic discharge event. As shown in FIG. 4, the RC time constant (RC constant) of the resistive circuit 320 of the analog fixed electrostatic discharge detecting circuit 300 is 50 ns and the channel length (L) of the fixed first oxynitride transistor 331 is 0.12um, and the data generated by the channel width of the first MOS transistor 331 • (W) (refer to curve 1 to curve 7). Referring to Fig. 5 and Fig. 3, Fig. 5 is a view showing the state of leakage current in the normal operation of the electrostatic discharge detecting circuit of the first embodiment of the present invention. As shown in FIG. 5, the simulation is when the first-supply voltage (ie, VDD) of the first power terminal 301 is fixed at 1 volt, and the electrostatic discharge detection data of the leakage current in the road 300 (please refer to the curve). 1 to curve 2). It can be clearly seen from the foregoing disclosure that when a thin gate electrode layer component of the advanced 17 1374595 process is required in the integrated circuit design, the circuit structure shown in FIG. 3 can realize electrostatic discharge while taking into consideration the circuit area. The protective function, and the normal operation of the wafer can effectively reduce the leakage current generated by the conventional technology of the thin gate oxide layer component (especially the MOS transistor), thereby improving the electrostatic discharge. The overall performance of the protection circuit. Please refer to FIG. 6. FIG. 6 is a schematic diagram showing the circuit structure of the first embodiment of the electrostatic discharge detecting circuit of the present invention. As shown in FIG. 6, the ESD detecting circuit 600 is coupled between a first power pad 6〇1 and a second power pad. In this embodiment, the first power pad 601 is a The YDD pad (to provide the first supply voltage vDD)' and the second power pad 602 is a vs. pad (to provide a second supply voltage Vss, such as a ground voltage). The static electricity detecting circuit 6A includes a bias circuit 610, a capacitance circuit 620, and a trigger circuit 63A. In the present embodiment, each of the resistor circuits 620 is coupled between the first power supply pad 6〇1 and a connection terminal 620. The resistance circuit 620 includes an impedance element 621 and a capacitor element 622. In addition, the trigger circuit 630 is coupled to the first power pad 6 (U, the second power pad 2, the resistance circuit 620, and the bias circuit 61 〇. In this embodiment, the trigger circuit 63 〇 uses two A p-type MOS transistor (a MOS transistor such as a second MOS transistor 632) is stacked, and an -N type oxy-oxide transistor (ie, a third gold oxide) is additionally used. The semiconductor transistor 633) is configured to form a trigger inverter with double-off. As shown in FIG. 6, the light-contact relationship of the trigger circuit (4) is as follows: 18 1374595: First MOS transistor One of the control terminals (closed) is in the first pass, and the first connection end (source) is coupled to the first power pad 601; one of the first metal semiconductor 632 controls ( Closedly connected to the second terminal, the connection (source) is connected to the second terminal (drain) of the first oxynitride transistor (3), and the second terminal (the terminal) ) is used to trigger an electrostatic discharge trigger signal W when an electrostatic discharge event occurs to turn on subsequent static electricity Electrical protection components (such as power clamp circuit), as shown in the figure, trigger the electrostatic discharge trigger • The gift is output by the end point (6); the third metal oxide semiconductor transistor 633, its control terminal (gate) Connected to the second end of the second end, a first connection end (no pole) is connected to the second connection end of the second gold-oxygen cast crystal 632, and a second connection end (source) is coupled to The second power pad 602. Please continue to refer to Fig. 6, the bias circuit (10) includes an inverter 615 and an impedance element 611. However, it should be noted that in the present embodiment, the impedance element 6 is used only as a For purposes of illustration, in other embodiments, the use of the impedance element 611 may also be omitted depending on design requirements. This design variation also falls within the design constraints of the present invention. In the bias circuit 610, the inverter 615 A p-type MOS transistor 612 and an N-type MOS transistor 613 are included. The inverter 615 is coupled to the second connection of the second terminal Nb and the second MOS transistor 632 of the flip-flop circuit 630. Between the ends (ie, the endpoint Nc). In this embodiment, the trigger is A trigger inverter composed of 63 与 and an inverter (bias inverter) 615 in the bias circuit 610 form a feedback control scheme, so that the inverter 615 will According to the feedback voltage level provided by the electrostatic discharge trigger signal, 19 Kangsheng-bias is electrically connected to the second end point to reduce the voltage drop across the capacitive element 622 (ie, the first and second terminals Na and The voltage difference between Nbs.) However, in other embodiments of the present invention, the electrostatic discharge fine circuit 600 also uses a squeezing circuit as the bias (four) way. For example, the bias in the first embodiment may be employed. The voltage circuit 310 is used in place of the bias circuit 61() of the second embodiment, that is, a circuit using other bias circuits different in design requirements without violating the spirit of the present invention. The configuration is in the electrostatic discharge circuit _, and these design changes are also the scope of the present invention. Electrostatic discharge fine circuit _ _ the state of the circuit under normal operation and the day of the electrostatic discharge event (4) circuit state will be detailed in the following disclosure. Please refer to FIG. 6 'When an electrostatic discharge event occurs, the voltage across the first power pad pad 601 and the second power pad pad 6 〇 2 is increased sharply due to the resistance circuit 62 RC: retardation (RCdeIay), such that the first oxynitride transistor 631 is turned on due to a voltage difference between the first terminal and the first terminal Na, and the first MOS transistor (3) The conduction further increases the voltage level of the first connection terminal (no pole) of the second MOS transistor 632, so that the second MOS transistor 2 is then turned on. As the conduction of the 苐-, MOS-electrode transistor 63 632 will raise the terminal Nc. (also the second terminal of the P-MOS transistor 632) # voltage to provide an electrostatic enemy trigger signal ItrigCT (Change from low (four) to high logic) to the power supply 1374595 circuit (not shown) to eliminate the electrostatic discharge current. At the end, when the electric dust of the point Nc is raised, the voltage is also fed back to the inverter of the surface circuit 61. (4) the pass_gold oxide half_electrode 613, with the conduction of the N-type MOS transistor 613, The contact of the second end point Nb is reduced to the low electric potential (for example, the electric age position close to the % electric seat), the characteristic of the thin oxide layer element of the advanced county, due to the two ends of the capacitive element 622 The difference increases, so the capacitive component must generate a large amount of gate leakage current, thereby further lowering the electric potential of the first terminal Na, so that when the electrostatic discharge event occurs, the first end point Na and the second end point can The lower electrical level will cause the first oxynitride transistor 631 of the flip-flop circuit 63G and the second gold oxide. The semiconductor transistor 6M is maintained in an on state and continues to provide an electrostatic discharge trigger signal W to a subsequent electrostatic discharge protection component (eg, a power supply clamp circuit) to bypass the electrostatic discharge current for electrostatic protection. Continuing to refer to FIG. 6, when the ESD detecting circuit _ is in normal operation, the third MOS transistor 633 in the flip-flop circuit 630 is turned on to bring the terminal Nc closer to the first: the power supply port 6〇2 The voltage supplied (Μ, so - to 'by the feedback mechanism' the low voltage of the terminal Nc turns on the P-type MOS transistor 612 in the reverse polarity 615 of the bias circuit 61, at this time, Since the p-type MOS transistor turns on the second terminal m (four) voltage will be pulled up to a voltage level close to the first supply voltage (VDD), since the first terminal Na is also in normal operation. - a voltage level close to the first supply voltage (v, compared to the prior art, the crossover between the two endpoints Na and N b can be reduced (since the voltage between the endpoint ^ and the can Approx. VDD ), in terms of the gate leakage current of the capacitor element 32 〇 (which is assumed to be implemented by the thin gate metal oxide capacitor of the advanced process in the present invention) In another aspect, the first MOS transistor 631 and the first circuit of the trigger circuit 630 are more effectively turned off. The MOS transistor 632. That is, in the present embodiment, under normal operation, since the voltage across the MOS transistor (i.e., the capacitor 622) of the advanced process is reduced, thereby avoiding The leakage current improperly generates an electrostatic discharge trigger signal to trigger the power clamp circuit, thus preventing the ESD protection circuit from malfunctioning to avoid being in an abnormal logic state. Please also refer to Figure 7 and Figure 6, Figure 7 is The electrostatic discharge detecting circuit of the second embodiment of the present invention simulates a trigger current when an electrostatic discharge event occurs. As shown in FIG. 7, the analog time is the RC time of the capacitive resistor circuit 620 of the fixed electrostatic discharge debt measuring circuit 600. Xu Yan, the deficit is 25 ns and the channel length (5) of the fixed MOS transistor is gamma, and the modulation is: the channel width of the oxy-oxide transistor 631 and the second MOS transistor (4) (W) The data generated (please refer to Qu Yugu., Curve 1~Curve 5). Please refer to the 8th and 6th diagrams of the brothers. The 8th figure shows the electrostatic discharge detection of the first and second columns of the invention. The circuit simulates the leakage current 正常_ 电仙·state diagram under normal operating conditions. As shown in Figure 8, this simulation is when the first power supply terminal 6 & first supply voltage (VDD) is fixed at i volts 'electrostatic discharge _Circuit ^ shape data (please refer to curve 1 ~ curve 2 Bu Bu can be clearly seen from the previous fans, when the integrated Wei design towel 34 uses the advanced 22 1374595 private thin gate oxide layer components, The circuit architecture shown in Fig. 6 utilizes a latch structure (formed by the inverter circuit 63A and the inverter structure in the bias circuit 61A) and the bias circuit 6i 〇 not only during normal operation # Reducing the electrostatic discharge side circuit 600 (4), the electric power L' can also accelerate the conduction of the power supply clamp circuit to an electrostatic discharge current when an electrostatic discharge event occurs. In the actual wiper, when an electrostatic discharge event occurs, the electrostatic discharge detecting circuit 600 generates a large amount of gate leakage current, and turns the gate leakage current of the capacitive element 622 into a holding point for continuously draining the electrostatic discharge current. The lead-metal oxy-oxide transistor 631 and the second MOS transistor 632 are continuously turned on. In other words, the circuit structure shown in FIG. 6 utilizes the leakage current of the MOS transistor capacitor of the advanced process to cause the trigger. The circuit can continuously generate a static f discharge trigger to initiate a subsequent electrostatic discharge protection component (for example, a power clamping circuit), and the value of the RC daily pin f of the tolerance circuit 620 can be purely under appropriate conditions. Mdina has the effect of electrostatic discharge protection; in these cases, the circuit area of the ESD protection circuit can be reduced and the cost can be reduced. Please note that under the spirit of Lin Biao Ben (4), other design changes are also feasible' For example, in other embodiments of the present invention, the bias circuit 310 of the electrostatic discharge detecting circuit 300 can also use the bias circuit shown in FIG. (10) is replaced by, in addition, the 'biasing circuit 61' of the impedance element 611 is an optional 7L piece. These related design changes belong to the fan of the invention. In summary, compared to the conventional static electricity The discharge detecting circuit, the electrostatic discharge protection technology provided by the invention 23 can avoid the influence of the '= plane caused by the large number of spans of the capacitive component in the capacitor circuit by avoiding the direct connection of the capacitive resistance circuit to the ssh). The ability to improve the static-discharge current during the occurrence of an electrostatic discharge event, taking into account both circuit area and cost considerations. As shown in the various embodiments of the foregoing, the preparation circuit of the electrostatic discharge detecting circuit of the present invention can be realized by various other equivalent circuits. For example, the voltage dividing circuit of the first embodiment can also use a resistive element as the voltage dividing element _ to achieve a voltage level different from the Vss voltage of the capacitor element. In addition to δ, any circuit architecture that uses the techniques described above to reduce the cross-over of the capacitive circuit to improve the leakage current of the ESD circuit during normal operation is in accordance with the present invention. The spirit falls within the fan of the present invention. The above is only the preferred embodiment of the present invention, and all changes and modifications made by the patent application scope of the present invention are within the scope of the present invention. _ [Simple description of the drawing] Fig. 1 is a block diagram of a conventional electrostatic discharge protection circuit. Figure 2 is a schematic diagram of the circuit architecture of another conventional electrostatic discharge price measurement circuit. Fig. 3 is a view showing the circuit arrangement of the first embodiment of the electrostatic discharge fine circuit of the present invention. Fig. 4 is a schematic view showing the trigger current when the electrostatic discharge fine circuit of the first embodiment of the present invention simulates an electrostatic event. 24 1374595 Fig. 5 is a schematic view showing the state of leakage current in the normal operation state of the electrostatic discharge_electrode according to the first embodiment of the present invention. Figure 6 is a schematic diagram showing the circuit architecture of the second embodiment of the electrostatic discharge detecting circuit of the present invention. Fig. 7 is a schematic view showing the trigger current when the electrostatic discharge gamma circuit of the second embodiment of the present invention simulates an electrostatic discharge event. Fig. 8 is a schematic view showing the state of leakage current in the state of the second embodiment of the electrostatic discharge test. [Main component symbol description] 100 Electrostatic discharge protection circuit 110, 200, 300, 600 Electrostatic discharge detection circuit 120 Power clamp circuit 210, 320, 620 Capacitance circuit 220, 330, 630 Trigger circuit 230 Connection terminals 301, 601 First Power pad 302, 602 second power pad 311 transistor element 32 611, 621 impedance element 322 ' 622 capacitor element 33 631 first MOS transistor 25 1374595 332 ' 632 second MOS transistor 612 P-type MOS transistor 613 N-type MOS transistor 615 Inverter 633 Third MOS transistor 26