CN108461475B - 三维半导体装置 - Google Patents

三维半导体装置 Download PDF

Info

Publication number
CN108461475B
CN108461475B CN201810270157.4A CN201810270157A CN108461475B CN 108461475 B CN108461475 B CN 108461475B CN 201810270157 A CN201810270157 A CN 201810270157A CN 108461475 B CN108461475 B CN 108461475B
Authority
CN
China
Prior art keywords
region
electrode
semiconductor device
sidewall
dummy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810270157.4A
Other languages
English (en)
Chinese (zh)
Other versions
CN108461475A (zh
Inventor
殷东锡
李宁浩
李俊熙
李锡元
申有哲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN108461475A publication Critical patent/CN108461475A/zh
Application granted granted Critical
Publication of CN108461475B publication Critical patent/CN108461475B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/083—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being via holes penetrating underlying conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/658—Shapes or dispositions of interconnections for devices provided for in groups H10D8/00 - H10D48/00

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
CN201810270157.4A 2012-08-22 2013-08-22 三维半导体装置 Active CN108461475B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR10-2012-0091920 2012-08-22
KR1020120091920A KR102003529B1 (ko) 2012-08-22 2012-08-22 적층된 전극들을 형성하는 방법 및 이를 이용하여 제조되는 3차원 반도체 장치
CN201310370209.2A CN103633043B (zh) 2012-08-22 2013-08-22 三维半导体装置

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN201310370209.2A Division CN103633043B (zh) 2012-08-22 2013-08-22 三维半导体装置

Publications (2)

Publication Number Publication Date
CN108461475A CN108461475A (zh) 2018-08-28
CN108461475B true CN108461475B (zh) 2021-09-24

Family

ID=50069720

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201810270157.4A Active CN108461475B (zh) 2012-08-22 2013-08-22 三维半导体装置
CN201310370209.2A Active CN103633043B (zh) 2012-08-22 2013-08-22 三维半导体装置

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201310370209.2A Active CN103633043B (zh) 2012-08-22 2013-08-22 三维半导体装置

Country Status (5)

Country Link
US (2) US9230904B2 (https=)
JP (1) JP6203573B2 (https=)
KR (1) KR102003529B1 (https=)
CN (2) CN108461475B (https=)
DE (1) DE102013109011B4 (https=)

Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8609536B1 (en) * 2012-07-06 2013-12-17 Micron Technology, Inc. Stair step formation using at least two masks
KR101974352B1 (ko) * 2012-12-07 2019-05-02 삼성전자주식회사 수직 셀을 갖는 반도체 소자의 제조 방법 및 그에 의해 제조된 반도체 소자
KR20150057147A (ko) * 2013-11-18 2015-05-28 삼성전자주식회사 메모리 장치
KR102183713B1 (ko) 2014-02-13 2020-11-26 삼성전자주식회사 3차원 반도체 장치의 계단형 연결 구조 및 이를 형성하는 방법
KR102154093B1 (ko) * 2014-02-14 2020-09-10 삼성전자주식회사 3차원 반도체 소자
CN104392962B (zh) 2014-04-28 2017-06-13 中国科学院微电子研究所 三维半导体器件制造方法
CN105514018B (zh) * 2014-09-26 2019-02-26 中芯国际集成电路制造(北京)有限公司 制造半导体装置的方法
US9337040B1 (en) * 2014-12-05 2016-05-10 Varian Semiconductor Equipment Associates, Inc. Angled ion beam processing of heterogeneous structure
KR20160071947A (ko) * 2014-12-12 2016-06-22 에스케이하이닉스 주식회사 반도체 장치 및 그 제조방법
CN105810640A (zh) * 2014-12-31 2016-07-27 上海格易电子有限公司 一种3d nand源极选择管及其制作方法
KR20160094785A (ko) * 2015-02-02 2016-08-10 에스케이하이닉스 주식회사 반도체 장치 및 그 제조 방법
US9356034B1 (en) * 2015-02-05 2016-05-31 Sandisk Technologies Inc. Multilevel interconnect structure and methods of manufacturing the same
KR102270101B1 (ko) * 2015-02-10 2021-06-29 삼성전자주식회사 반도체 소자 및 그 제조 방법
US9620519B2 (en) 2015-03-04 2017-04-11 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device having word line hookup region with dummy word lines
US20160268269A1 (en) * 2015-03-12 2016-09-15 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and method of manufacturing the same
KR102333478B1 (ko) * 2015-03-31 2021-12-03 삼성전자주식회사 3차원 반도체 장치
US10199386B2 (en) * 2015-07-23 2019-02-05 Toshiba Memory Corporation Semiconductor memory device and method for manufacturing same
US10186520B2 (en) 2015-09-11 2019-01-22 Toshiba Memory Corporation Semiconductor memory devices including a memory cell array and stepped wiring portions, and manufacturing methods thereof
US9704878B2 (en) 2015-10-08 2017-07-11 Samsung Electronics Co., Ltd. Nonvolatile memory devices and methods of forming same
US20170147730A1 (en) * 2015-11-23 2017-05-25 Apple Inc. Binary patterning for three-dimensional memory formation
KR102536261B1 (ko) * 2015-12-18 2023-05-25 삼성전자주식회사 3차원 반도체 장치
KR102649372B1 (ko) * 2016-01-08 2024-03-21 삼성전자주식회사 3차원 반도체 메모리 장치
KR102664184B1 (ko) * 2016-01-15 2024-05-16 삼성전자주식회사 3차원 반도체 메모리 장치
US9911753B2 (en) 2016-01-15 2018-03-06 Toshiba Memory Corporation Semiconductor device and method for manufacturing semiconductor device
KR102512322B1 (ko) * 2016-01-19 2023-03-22 에스케이하이닉스 주식회사 반도체 장치의 제조 방법
KR102550571B1 (ko) * 2016-05-02 2023-07-04 에스케이하이닉스 주식회사 반도체 장치 및 그 제조 방법
KR102415206B1 (ko) * 2016-06-27 2022-07-01 에스케이하이닉스 주식회사 반도체 장치
US10504838B2 (en) 2016-09-21 2019-12-10 Micron Technology, Inc. Methods of forming a semiconductor device structure including a stair step structure
US10192877B2 (en) * 2017-03-07 2019-01-29 Sandisk Technologies Llc Three-dimensional memory device with level-shifted staircase structures and method of making thereof
JP2018170447A (ja) * 2017-03-30 2018-11-01 東芝メモリ株式会社 半導体装置及びその製造方法
KR102421766B1 (ko) 2017-07-07 2022-07-18 삼성전자주식회사 3차원 반도체 장치 및 그 제조 방법
US11004726B2 (en) * 2017-10-30 2021-05-11 Macronix International Co., Ltd. Stairstep structures in multilevel circuitry, and method for forming the same
US10546870B2 (en) 2018-01-18 2020-01-28 Sandisk Technologies Llc Three-dimensional memory device containing offset column stairs and method of making the same
JP2019169489A (ja) 2018-03-21 2019-10-03 東芝メモリ株式会社 記憶装置及びその製造方法
US10804284B2 (en) 2018-04-11 2020-10-13 Sandisk Technologies Llc Three-dimensional memory device containing bidirectional taper staircases and methods of making the same
JP2019201028A (ja) 2018-05-14 2019-11-21 東芝メモリ株式会社 半導体装置
WO2020000306A1 (en) * 2018-06-28 2020-01-02 Yangtze Memory Technologies Co., Ltd. Staircase structures for three-dimensional memory device double-sided routing
KR102612408B1 (ko) 2018-11-02 2023-12-13 삼성전자주식회사 3차원 반도체 메모리 장치 및 그 제조 방법
KR102699605B1 (ko) * 2018-11-12 2024-08-29 삼성전자주식회사 3차원 반도체 메모리 장치 및 그 제조 방법
CN109962161A (zh) * 2018-12-03 2019-07-02 复旦大学 基于内置非线性rram的3d垂直交叉阵列及其制备方法
KR102736178B1 (ko) * 2019-01-15 2024-12-02 삼성전자주식회사 3차원 반도체 메모리 장치 및 그 제조 방법
JP7134901B2 (ja) * 2019-03-04 2022-09-12 キオクシア株式会社 半導体記憶装置の製造方法
US20220149073A1 (en) * 2019-04-04 2022-05-12 Samsung Electronics Co., Ltd. Three-dimensional flash memory and method for manufacturing same
KR102207214B1 (ko) * 2019-05-17 2021-01-25 삼성전자주식회사 집적화를 도모하는 3차원 플래시 메모리 및 그 제조 방법
KR102161740B1 (ko) * 2019-04-04 2020-10-05 삼성전자주식회사 효율적으로 워드라인을 형성하는 3차원 플래시 메모리 제조 방법
KR102721962B1 (ko) 2019-04-26 2024-10-28 삼성전자주식회사 가변 저항 층을 갖는 반도체 메모리 소자
KR102304931B1 (ko) * 2019-09-04 2021-09-24 삼성전자주식회사 워드라인 영역의 면적을 감소시키는 3차원 플래시 메모리
US11901287B2 (en) 2021-09-02 2024-02-13 Micron Technology, Inc. Microelectronic devices with multiple step contacts extending to stepped tiers, and related systems and methods
CN114256246A (zh) * 2022-01-14 2022-03-29 福建省晋华集成电路有限公司 三维存储器件及其制作方法
CN116867262A (zh) 2022-03-23 2023-10-10 长鑫存储技术有限公司 半导体结构及其制作方法、存储器
KR20240030031A (ko) 2022-08-29 2024-03-07 삼성전자주식회사 반도체 장치 및 데이터 저장 시스템

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101740579A (zh) * 2008-11-11 2010-06-16 三星电子株式会社 垂直型半导体器件
CN101794789A (zh) * 2009-02-02 2010-08-04 三星电子株式会社 三维存储器器件
CN102637629A (zh) * 2011-02-14 2012-08-15 旺宏电子股份有限公司 用于具叠层接触层的ic装置的减少数量的掩模组合及方法

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4768557B2 (ja) 2006-09-15 2011-09-07 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
JP4445514B2 (ja) 2007-04-11 2010-04-07 株式会社東芝 半導体記憶装置
JP4468433B2 (ja) 2007-11-30 2010-05-26 株式会社東芝 不揮発性半導体記憶装置
JP2009135328A (ja) 2007-11-30 2009-06-18 Toshiba Corp 不揮発性半導体記憶装置
JP2009200443A (ja) 2008-02-25 2009-09-03 Toshiba Corp 不揮発性半導体記憶装置、及びその製造方法
US7910973B2 (en) 2008-03-17 2011-03-22 Kabushiki Kaisha Toshiba Semiconductor storage device
JP2009224612A (ja) 2008-03-17 2009-10-01 Toshiba Corp 不揮発性半導体記憶装置、及びその製造方法
JP4635069B2 (ja) 2008-03-26 2011-02-16 株式会社東芝 不揮発性半導体記憶装置
JP5253875B2 (ja) 2008-04-28 2013-07-31 株式会社東芝 不揮発性半導体記憶装置、及びその製造方法
JP5086959B2 (ja) 2008-09-26 2012-11-28 株式会社東芝 不揮発性半導体記憶装置
JP5330017B2 (ja) 2009-02-17 2013-10-30 株式会社東芝 不揮発性半導体記憶装置、及びその製造方法
JP5305980B2 (ja) 2009-02-25 2013-10-02 株式会社東芝 不揮発性半導体記憶装置、及びその製造方法
JP2011003833A (ja) 2009-06-22 2011-01-06 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法
KR20110001527A (ko) * 2009-06-30 2011-01-06 주식회사 하이닉스반도체 수직채널형 비휘발성 메모리 소자의 제조 방법
KR101027349B1 (ko) 2009-08-03 2011-04-11 주식회사 하이닉스반도체 수직채널형 비휘발성 메모리 소자 및 그 제조 방법
KR20110015338A (ko) * 2009-08-07 2011-02-15 주식회사 하이닉스반도체 수직채널형 비휘발성 메모리 소자 제조 방법
KR101055587B1 (ko) 2010-06-09 2011-08-08 한양대학교 산학협력단 3차원 구조를 가지는 메모리의 제조방법
WO2011081438A2 (ko) 2009-12-31 2011-07-07 한양대학교 산학협력단 3차원 구조를 가지는 메모리 및 이의 제조방법
JP2011142276A (ja) 2010-01-08 2011-07-21 Toshiba Corp 不揮発性半導体記憶装置、及びその製造方法
KR101702060B1 (ko) 2010-02-19 2017-02-02 삼성전자주식회사 3차원 반도체 장치의 배선 구조체
JP2011204829A (ja) * 2010-03-25 2011-10-13 Toshiba Corp 半導体記憶装置
KR20110111809A (ko) 2010-04-05 2011-10-12 삼성전자주식회사 계단형 구조를 구현할 수 있는 패터닝 방법 및 이를 이용한 불휘발성 메모리 소자의 제조 방법
KR101738533B1 (ko) * 2010-05-24 2017-05-23 삼성전자 주식회사 적층 메모리 장치 및 그 제조 방법
KR20120030815A (ko) * 2010-09-20 2012-03-29 삼성전자주식회사 3차원 반도체 장치 및 그 제조 방법
KR101787041B1 (ko) * 2010-11-17 2017-10-18 삼성전자주식회사 식각방지막이 구비된 반도체 소자 및 그 제조방법
KR101778286B1 (ko) * 2011-01-03 2017-09-13 삼성전자주식회사 3차원 반도체 장치의 제조 방법
KR101265547B1 (ko) 2011-02-10 2013-05-20 농업회사법인 청양송이 주식회사 아미노산 함량이 높은 양송이버섯 재배용 배지 조성물 및 그 제조방법과 이를 이용한 양송이버섯 재배방법
KR101808822B1 (ko) 2011-08-04 2017-12-14 삼성전자주식회사 반도체 소자 및 그 제조방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101740579A (zh) * 2008-11-11 2010-06-16 三星电子株式会社 垂直型半导体器件
CN101794789A (zh) * 2009-02-02 2010-08-04 三星电子株式会社 三维存储器器件
CN102637629A (zh) * 2011-02-14 2012-08-15 旺宏电子股份有限公司 用于具叠层接触层的ic装置的减少数量的掩模组合及方法

Also Published As

Publication number Publication date
JP2014042029A (ja) 2014-03-06
US20160099170A1 (en) 2016-04-07
JP6203573B2 (ja) 2017-09-27
DE102013109011B4 (de) 2022-12-15
CN103633043B (zh) 2018-04-27
CN103633043A (zh) 2014-03-12
CN108461475A (zh) 2018-08-28
US9449870B2 (en) 2016-09-20
KR102003529B1 (ko) 2019-07-25
DE102013109011A1 (de) 2014-02-27
US20140054787A1 (en) 2014-02-27
KR20140025798A (ko) 2014-03-05
US9230904B2 (en) 2016-01-05

Similar Documents

Publication Publication Date Title
CN108461475B (zh) 三维半导体装置
US12389601B2 (en) Three dimensional semiconductor memory device and method for fabricating the same
US9224429B2 (en) Three-dimensional semiconductor devices and methods of fabricating the same
US8654584B2 (en) Three-dimensional non-volatile memory devices having highly integrated string selection and sense amplifier circuits therein
KR101965602B1 (ko) 3차원 반도체 장치의 제조 방법 및 이에 따라 제조된 3차원 반도체 장치
US8426272B2 (en) Non-volatile memory devices including shared bit lines and methods of fabricating the same
KR20090128779A (ko) 반도체 장치 및 그 제조 방법
KR20200057936A (ko) 반도체 메모리 장치 및 그 형성방법
US9947684B2 (en) Three-dimensional semiconductor device
US20140151627A1 (en) Semiconductor device and method of manufacturing the same
US20080096377A1 (en) Semiconductor device and method for forming the same
KR20120042420A (ko) 3차원 반도체 기억 소자
KR101616091B1 (ko) 모놀리식 3차원 nand 스트링

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant