CN105990499A - 发光二极管封装结构及其制作方法 - Google Patents

发光二极管封装结构及其制作方法 Download PDF

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Publication number
CN105990499A
CN105990499A CN201610157175.2A CN201610157175A CN105990499A CN 105990499 A CN105990499 A CN 105990499A CN 201610157175 A CN201610157175 A CN 201610157175A CN 105990499 A CN105990499 A CN 105990499A
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Prior art keywords
electrode
connection pad
emitting diode
light emitting
protection element
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CN201610157175.2A
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Inventor
洪钦华
林育锋
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Genesis Photonics Inc
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Genesis Photonics Inc
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Application filed by Genesis Photonics Inc filed Critical Genesis Photonics Inc
Publication of CN105990499A publication Critical patent/CN105990499A/zh
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Abstract

本发明为一种发光二极管封装结构及其制作方法。发光二极管封装结构包括承载基座、静电保护元件及发光二极管。承载基座具有第一导接垫及第二导接垫。静电保护元件是设置在承载基座上，具有第一电极及第二电极，且第一、第二电极分别电性连接在第一、第二导接垫。发光二极管设置在静电保护元件上方，具有第三电极及第四电极，第三、第四电极分别电性连接于第一、第二导接垫。该发光二极管封装结构可避免发光二极管受到异常电压或静电放电的破坏。

Description

发光二极管封装结构及其制作方法
技术领域
本发明是关于一种发光二极管封装结构及其制作方法，特别是一种具有静电保护元件的发光二极管封装结构及其制作方法。
背景技术
发光二极管具有诸如寿命长、体积小、高抗震性、低热产生及低功率消耗等优点，因此随着科技的发展，发光二极管已被广泛应用于家用及各种设备中的指示器或光源。虽然发光二极管具有上述众多优点，但却常因异常电压或静电放电(electrostatic discharge，ESD)而损坏。
在先前技术中，为了避免发光二极管因异常电压或静电放电而损坏，而将发光二极管与静电防护元件，例如是齐纳二极管(Zener diode)同时设置在同一承载基座上，且发光二极管与齐纳二极管是透过电极反向相连接，来避免发光二极管受到异常电压或静电放电的破坏。然而，由于发光二极管与静电防护元件设置在同一承载基座的相同平面上，静电防护元件会阻挡及吸收发光二极管所发出的光，会导致整体发光二极管的发光效率降低并造成封装结构面积过大，在应用上就受到许多限制。
因此，有必要发明一种发光二极管封装结构及其制作方法，以解决先前技术的缺失。
发明内容
本发明实施例在提供一种发光二极管封装结构及其制作方法，以改善上述现有问题。
本发明一实施例有关于一种发光二极管封装结构。发光二极管封装结构包括承载基座、静电保护元件及发光二极管。承载基座具有第一导接垫及第二导接垫。静电保护元件是设置在承载基座上，具有第一电极及第二电极，且第一、第二电极分别电性连接于第一、第二导接垫。发光二极管设置在静电保护元件上方，具有第三电极及第四电极，第三、第四电极分别电性连接于第一、第二导接垫。
本发明另一实施例有关于一种发光二极管封装结构的制作方法。制作方法包括以下步骤：提供承载基座，其中承载基座具有第一导接垫及第二导接垫；设置静电保护元件在承载基座上，其中静电保护元件具有第一电极及第二电极；使第一电极及第二电极分别电性连接于第一导接垫及第二导接垫；设置发光二极管在静电保护元件的上方，其中发光二极管具有第三电极及第四电极；以及使第三电极及第四电极分别电性连接于第一导接垫及第二导接垫。
附图说明
图1A是本发明一实施例的发光二极管封装结构的俯视图；
图1B是图1A的发光二极管封装结构沿方向1B-1B’的剖视图；
图2为本发明另一实施例的发光二极管封装结构的剖视图；
图3为本发明另一实施例的发光二极管封装结构的剖视图；
图4为本发明另一实施例的发光二极管封装结构的剖视图；
图5为本发明另一实施例的发光二极管封装结构的剖视图；
图6A至6F为图1B的发光二极管封装结构及图3的发光二极管封装结构的制造过程图；
图7A至7C为图1B、图2、图3及图4的承载基座的另一种制造过程图；
图8A至8F为图5的发光二极管封装结构的制造过程图。
附图标记说明：
10a、10a’、10b、10c、10d：发光二极管封装结构；
20、20’：承载基座；
20a、20a’：第一导接垫；
20b、20b’：第二导接垫；
20c’：第三导接垫；
20d’：第四导接垫；
20a1：第一上表面；
20e：下表面；
20b1：第二上表面；
20u：上表面；
21：凹槽；
21w：内侧壁；
211：第一子凹槽；
212：第二子凹槽；
22a：第一导通孔；
22b：第二导通孔；
24：陶瓷片；
24a：开孔；
30：静电保护元件；
30a：第一反射层；
31：第一电极；
32：第二电极；
40、40’：发光二极管；
40s：侧面；
41：第三电极；
42：第四电极；
43：基板；
44：第一型半导体层；
45：第二型半导体层；
46：发光层；
47：第二反射层；
48：第三反射层；
49：绝缘层；
50：高反射胶体；
55、55’：焊线；
60：绝缘体；
61：间隔部；
62：边缘部；
H1：第一厚度；
H2：第二厚度；
H3：深度；
P1：间隔；
W1：第一宽度；
W2：第二宽度。
具体实施方式
请参考图1A及图1B。图1A是本发明一实施例的发光二极管封装结构10a的俯视图，而图1B是图1A的发光二极管封装结构10a沿方向1B-1B’的剖视图。
发光二极管封装结构10a包括承载基座20、静电保护元件30及发光二极管40。
承载基座20用以承载静电保护元件30及发光二极管40。承载基座20包括第一导接垫20a、第二导接垫20b及绝缘体60。第一导接垫20a与第二导接垫20b透过绝缘体60电性隔离。举例来说，第一导接垫20a与第二导接垫20b之间具有一间隔P1。绝缘体60包括间隔部61及边缘部62，其中间隔部61填入间隔P1的至少一部分，以隔离第一导接垫20a与第二导接垫20b。此外，边缘部62包覆第一导接垫20a的侧面及第二导接垫20b的侧面，可防止第一导接垫20a的侧面及第二导接垫20b的侧面露出，进而避免第一导接垫20a与第二导接垫20b透过侧面电性短路。
在一实施例中，第一导接垫20a及第二导接垫20b的材料可以是金属，如铜、铝或其合金，但本发明实施例并不限于此。在一实施例中，绝缘体60的材料可以为硅氧树脂(Silicone)、环氧树脂(Epoxy)或聚邻苯二甲酰胺树脂(PPA)等，但本发明实施例并不限于此。
静电保护元件30设置在承载基座20上，静电保护元件30可为一种用以防止异常电压或静电放电的电子元件，例如齐纳二极管，但本发明实施例并不限于此。静电保护元件30具有第一电极31及第二电极32，第一电极31电性连接至第一导接垫20a，而第二电极32电性连接至第二导接垫20b。虽然图未示出，然第一电极31与第一导接垫20a之间可包含有焊锡，而第二电极32与第二导接垫20b之间可包含有焊锡，焊锡可焊合电极与导接垫。
承载基座20具有凹槽21，凹槽21从第一导接垫20a的第一上表面20a1及第二导接垫20b的第二上表面20b1往下延伸，但不贯穿第一导接垫20a及第二导接垫20b。凹槽21可采用例如是半蚀刻技术或机械加工技术形成，但本发明实施例并不限于此方式。
静电保护元件30是设置在凹槽21内，因此不会干涉到上方的发光二极管40，且也可充分利用承载基座20沿厚度方向的空间。
静电保护元件30的至少一电极可位于发光二极管40的第三电极41与第四电极42之间。例如，如图1B所示，本实施例的静电保护元件30的第一电极31及第二电极32位于第三电极41与第四电极42之间。
此外，承载基座20具有一侧壁，静电保护元件30可位于侧壁内。例如，如第1A图所示，静电保护元件30受到凹槽21的内侧壁21w围绕。如图1B所示，凹槽21具有相对之内侧壁21w1与21w2，静电保护元件30位于相对二内侧壁21w1与21w2内或之间。
发光二极管40可发出一光线。发光二极管40配置在承载基座20上。举例来说，发光二极管40具有第三电极41及第四电极42，第三电极41电性连接至第一导接垫20a，而第四电极42电性连接至第二导接垫20b。如此一来，静电保护元件30的第一电极31与发光二极管40的第三电极41共接点，而静电保护元件30的第二电极32与发光二极管40的第四电极42共接点，因此静电保护元件30与发光二极管40并联；如此一来，静电保护元件30可避免发光二极管40受到异常电压或静电放电的破坏。
此外，发光二极管40与承载基座20采用共晶接合方式等方式进行接合，但本发明实施例不限于此。虽然图未示出，然第三电极41与第一导接垫20a之间可包含有焊锡，而第四电极42与第二导接垫20b之间可包含有焊锡，焊锡可焊合电极与导接垫。
如图1B所示，发光二极管40可直接设置在静电保护元件30的正上方。通过发光二极管40与静电保护元件30沿垂直方位配置，可避免静电保护元件30占用承载基座20的水平面积，进而使发光二极管封装结构10a的表面积缩小。
发光二极管40的表面积是大于凹槽21的表面积。举例来说，如图1B所示，发光二极管40的体积大于凹槽21的容积，因此发光二极管40的表面积大于凹槽21的表面积。
如图1B所示，发光二极管40具有第一宽度W1，而静电保护元件30具有第二宽度W2，其中第一宽度W1大于第二宽度W2，使发光二极管40可覆盖整个静电保护元件30。在一实施例中，第一宽度W1可以是第二宽度W2的三倍，然也可为三倍以下或以上。此外，承载基座20具有第一厚度H1，静电保护元件30具有第二厚度H2，而凹槽21具有深度H3。在一实施例中，第一厚度H1例如是介于0.38毫米与0.5毫米之间，第二厚度度H2例如是0.1毫米，而深度H3可满足下式(1)及(2)，其中式(2)中的A例如是介于0.05毫米与0.1毫米之间的数值。
由于第一厚度H1、第二厚度H2及深度H3的设计，使当发光二极管40设置在该静电保护元件30上方时，从发光二极管封装结构10a的外观几乎看不到静电保护元件30，且/或凹槽21的深度也不会影响到承载基座20原来的作用。
如图1B所示，发光二极管40例如是覆晶式(Flip-Chip)发光二极管，但本发明实施例不限于此。发光二极管40还包括基板43、第一型半导体层44、第二型半导体层45、发光层46及第二反射层47。第一型半导体层44形成于基板43上，发光层46例如是多层量子井结构(Multiple Quantum Well，MQW)，其形成于第一型半导体层44与第二型半导体层45之间。第一型半导体层44例如是P型与N型半导体之一者，而第二型半导体层45例如是P型与N型半导体之另一者。
在本实施例中，第二反射层47形成布拉格反射层DBR(Distributed Braggreflector)结构。第二反射层47可形成于发光二极管40的底层，例如是形成于第二型半导体层45的下方。如此，可将射向第二反射层47的光线反射至从基板43出光，也可避免光线往承载基座20的方向漏光。
如图1B所示，静电保护元件30的顶部也可以形成具有第一反射层30a，以提高光反射效果。此外，第二反射层47及/或第一反射层30a可采用蒸镀方式形成。在一实施例中，第二反射层47及/或第一反射层30a的材料例如是金属。在另一实施例中，发光二极管40可省略第二反射层47与第一反射层30a的至少一者。
如图1B所示，第二反射层47具有二开孔(未标示)，其分别露出第一型半导体层44与第二型半导体层45。第三电极41及第四电极42可透过二开孔分别电性连接于第一型半导体层44与第二型半导体层45。
如图1B所示，凹槽21内可不包含任何胶体；或者，凹槽21内除了静电保护元件30外，可不包含任何实体元件，然本发明实施例不以此为限。
图2为本发明另一实施例的发光二极管封装结构10a’的剖视图。发光二极管封装结构10a’包括承载基座20、静电保护元件30、发光二极管40及高反射胶体50。与前述发光二极管封装结构10a不同的是，本实施例的发光二极管封装结构10a’还包括高反射胶体50。
高反射胶体50可填入凹槽21的至少一部分，以固定静电保护元件30与承载基座20的相对位置。高反射胶体50的材质可为环氧树脂或硅树脂，其反射率可超过90％，但本发明实施例并不限于此。如图2所示，高反射胶体50可包覆静电保护元件30的整个顶面及整个侧面，然在另一实施例中，高反射胶体50可包覆静电保护元件30的顶面的一部分及/或侧面的一部分。在本实施例中，高反射胶体50不接触发光二极管40的底面，然在另一实施例中，高反射胶体50可接触发光二极管40的底部，如接触电极及/或第二反射层47。
如图2所示，由于高反射胶体50的设计，静电保护元件30可省略第一反射层30a，然也可包含有第一反射层30a。
图3为本发明另一实施例的发光二极管封装结构10b的剖视图。发光二极管封装结构10b包括承载基座20、静电保护元件30、发光二极管40及高反射胶体50。
与上述发光二极管封装结构10a’不同的是，本实施例的发光二极管封装结构10b的高反射胶体50更包覆发光二极管40的四周，如侧面40s；如此一来，当发光二极管40的侧面40s发出的光线到达高反射胶体50时，可被反射至从发光二极管40的上表面出光，借此，可使发光二极管40的发光更集中，而不会往四周散射出去。
图4为本发明另一实施例的发光二极管封装结构10c的剖视图。发光二极管封装结构10c包括承载基座20、静电保护元件30、发光二极管40’、高反射胶体50及数条焊线55及55’。
与上述发光二极管40不同的是，本实施例的发光二极管40’的结构例如是横向芯片(Lateral Chip)结构发光二极管。
举例来说，发光二极管40’包括基板43、第一型半导体层44、第二型半导体层45、发光层46、第二反射层47、第三反射层48及绝缘层49。第一型半导体层44形成在基板43上，发光层46形成在第一型半导体层44与第二型半导体层45之间。第二反射层47可形成在发光层46下方，以将到达第二反射层47的光线反射至从发光二极管40’上表面出光，也可避免光线往承载基座20的方向漏光。绝缘层49形成在第三反射层48上，例如是形成在第三反射层48的下方，以隔离第三反射层48与承载基座20，避免第三反射层48与承载基座20电性短路。
此外，第二反射层47及/或第三反射层48可采用蒸镀方式形成。在一实施例中，第三反射层48及/或第二反射层47的材料例如是金属。在另一实施例中，发光二极管40’可省略第二反射层47与第三反射层48的至少一者。
第二反射层47及第三反射层48可形成全方向反射层ODR结构(Omni-Directional reflector)结构。在另一实施例中，若省略第三反射层48，则第二反射层47可形成DBR(Distributed Bragg reflector)结构。
如图4所示，一焊线55可连接第一导接垫20a与第二型半导体层45，而另一焊线55’可连接第二导接垫20b与第一型半导体层44，使承载基座20与发光二极管40’透过焊线55及55’电性连接。
在另一实施例中，图4的发光二极管封装结构10c的高反射胶体50可更包覆焊线55及55’及发光二极管40’的侧面40s，但可不包覆发光二极管40’的出光上表面。在其它实施例中，发光二极管封装结构10c可省略高反射胶体50。
图5为本发明另一实施例的发光二极管封装结构10d的剖视图。发光二极管封装结构10d包括承载基座20’、静电保护元件30、发光二极管40及高反射胶体50。
与前述实施例不同的是，本发明实施例的承载基座20’为陶瓷基板。承载基座20’包括堆叠的数片陶瓷片24、第一导接垫20a’、第二导接垫20b’、第一导通孔22a、第二导通孔22b、第三导接垫20c’及第四导接垫20d’及凹槽21。
凹槽21从承载基座20’的上表面20u(如最上层的陶瓷片24的顶面)往承载基座20’的下表面20e的方向延伸，但不贯穿堆叠的数片陶瓷片24的厚度。第一导接垫20a’及第二导接垫20b’从上表面20u延伸至凹槽21内，第一导接垫20a’与第二导接垫20b’彼此隔离。第三导接垫20c’及第四导接垫20d’形成在承载基座20’的下表面20e，第三导接垫20c’与第四导接垫20d’彼此隔离。第一导通孔22a及第二导通孔22b贯穿堆叠的陶瓷片24，其中第一导通孔22a连接第一导接垫20a’与第三导接垫20c’，而第二导通孔22b连接第二导接垫20b’与第四导接垫20d’。
静电保护元件30设在凹槽21内。静电保护元件30包括第一电极31及第二电极32，其中第一电极31电性连接第一导接垫20a’，而第二电极32连接第二导接垫20b’。虽然图未示出，然第一电极31与第一导接垫20a’之间可包含有焊锡，而第二电极32与第二导接垫20b’之间可包含有焊锡，焊锡可焊合电极与导接垫。
发光二极管40可设置在承载基座20’的上表面20u上。发光二极管40的第三电极41电性连接于第一导接垫20a’，而第四电极42电性连接于第二导接垫20b’。虽然图未示出，然第三电极41与第一导接垫20a’之间包含有焊锡，而第四电极42与第二导接垫20b’之间包含有焊锡，焊锡可焊合电极与导接垫。
由于静电保护元件30的第一电极31与发光二极管40的第三电极41共接点，而静电保护元件30的第二电极32与发光二极管40的第四电极42共接点，因此静电保护元件30与发光二极管40并联；如此一来，静电保护元件30可避免发光二极管40受到异常电压或静电放电的破坏。
在一实施例中，第一导接垫20a’、第二导接垫20b’、第三导接垫20c’与第四导接垫20d’中至少一者可采用例如是电镀方式在同一制程中形成，然本发明实施例不限于此。在一实施例中，第一导通孔22a及第二导通孔22b可采用例如是钻孔及电镀方式形成。以材料而言，第一导接垫20a’、第二导接垫20b’、第三导接垫20c’及第四导接垫20d’可以是银或其合金，而第一导通孔22a及第二导通孔22b可以是铜或其合金。
在另一实施例中，发光二极管封装结构10d可省略高反射胶体50；或者，发光二极管封装结构10d的高反射胶体50可仅包覆静电保护元件30的至少一部分，但不包覆发光二极管40。
图6A至6F为图1B的发光二极管封装结构10a及图3的发光二极管封装结构10b的制造过程图。
首先，提供一承载基座20。以下说明承载基座20的制作方法。
如图6A所示，提供第一导接垫20a及第二导接垫20b。第一导接垫20a与第二导接垫20b相距一间隔P1，使第一导接垫20a与第二导接垫20b透过间隔P1彼此电性隔离。第一导接垫20a具有第一子凹槽211，而第二导接垫20b具有第二子凹槽212，第一子凹槽211与第二子凹槽212形成凹槽21。第一子凹槽211、第二子凹槽212与间隔P1可在同一制程中形成，然也可在不同制程中分别形成。此外，第一子凹槽211、第二子凹槽212及/或间隔P1可采用例如是半蚀刻技术或机械加工技术形成。
如图6B所示，可采用例如是封装技术或点胶技术，形成绝缘体60，以形成承载基座20，其中绝缘体60可填入间隔P1的至少一部分，且包覆第一导接垫20a的侧面及第二导接垫20b的侧面。
如图6C所示，可采用例如是表面接合技术(SMT)或是共晶接合技术，设置静电保护元件30在凹槽21内。静电保护元件30包括第一电极31及第二电极32，其分别电性连接于第一导接垫20a及第二导接垫20b。
如图6D所示，提供发光二极管40。发光二极管40至少包括第三电极41及第四电极42。
如图6E所示，可采用例如是表面接合技术或是共晶接合技术，设置发光二极管40在承载基座20上，以形成图1B所示的发光二极管封装结构10a，其中发光二极管40的第三电极41及第四电极42分别电性连接于第一导接垫20a及第二导接垫20b。
如图6E所示，静电保护元件30的第一电极31与发光二极管40的第三电极41共接点，而静电保护元件30的第二电极32与发光二极管40的第四电极42共接点，因此静电保护元件30与发光二极管40并联；如此一来，静电保护元件30可避免发光二极管40受到异常电压或静电放电的破坏。
如图6F所示，可采用例如是封装技术或点胶技术，形成高反射胶体50，以形成图3所示的发光二极管封装结构10b，其中高反射胶体50填满凹槽21且覆盖发光二极管40的侧面40s。
在另一实施例中，图6F的高反射胶体50可仅覆盖静电保护元件30的至少一部分，但不覆盖发光二极管40的侧面40s，如此可形成例如是图2所示的发光二极管封装结构10a’。
图4的发光二极管封装结构10c的制造过程类似发光二极管封装结构10a，差异在于发光二极管封装结构10c的制造过程增加一焊线55的打线步骤。
图7A至7C为图1B、图2、图3及图4的承载基座20的另一种制造过程图。
如图7A所示，提供第一导接垫20a及第二导接垫20b，其中第一导接垫20a与第二导接垫20b之间相距一间隔P1，使第一导接垫20a与第二导接垫20b透过间隔P1彼此电性隔离。相较于图6A的导接垫，本步骤所提供的第一导接垫20a尚未形成第一子凹槽211且第二导接垫20b尚未形成第二子凹槽212。
如图7B所示，可采用例如是封装技术或点胶技术，形成绝缘体60，其中绝缘体60可填入间隔P1的至少一部分，且包覆第一导接垫20a的侧面及第二导接垫20b的侧面。
如图7C所示，可采用例如是半蚀刻技术或机械加工技术，移除图7B的第一导接垫20a、第二导接垫20b及绝缘体60的一部分，以形成凹槽21，进而。形成承载基座20。
图8A至8F为图5的发光二极管封装结构10d的制造过程图。
如图8A所示，堆叠数片陶瓷片24形成一堆叠陶瓷基板。数片陶瓷片24形成凹槽21，凹槽21从堆叠陶瓷基板的上表面20u往下表面20e方向延伸，但不贯穿堆叠陶瓷基板。例如，数片陶瓷片24的一些陶瓷片24’各具有开孔24a，此些陶瓷片24’堆叠后形成凹槽21。
如图8B所示，可采用例如是钻孔技术，形成第一导通孔22a及第二导通孔22b贯穿堆叠陶瓷基板。
如图8C所示，可采用例如是电镀技术或微影蚀刻，形成第一导接垫20a’、第二导接垫20b’、第三导接垫20c’及第四导接垫20d’，以形成承载基座20’，其中第一导接垫20a’及第二导接垫20b’从堆叠陶瓷基板的上表面20u延伸至凹槽21内，而第三导接垫20c’及第四导接垫20d’形成在堆叠陶瓷基板的下表面20e，且第一导通孔22a连接第一导接垫20a’与第三导接垫20c’，而第二导通孔22b连接第二导接垫20b’与第四导接垫20d’。
如图8D所示，可采用例如是表面接合技术或是共晶接合技术，设置静电保护元件30在承载基座20’的凹槽21内。静电保护元件30包括第一电极31及第二电极32，其分别电性连接于第一导接垫20a’及第二导接垫20b’。
如图8E所示，提供发光二极管40。发光二极管40至少包括第三电极41及第四电极42。
然后，可采用例如是表面接合技术或是共晶接合技术，设置发光二极管40在承载基座20’上。发光二极管40的第三电极41及第四电极42分别电性连接于第一导接垫20a’及第二导接垫20b’。如此一来，静电保护元件30的第一电极31与发光二极管40的第三电极41共接点，而静电保护元件30的第二电极32与发光二极管40的第四电极42共接点，因此静电保护元件30与发光二极管40并联；如此一来，静电保护元件30可避免发光二极管40受到异常电压或静电放电的破坏。
如图8F所示，可采用例如是封装技术或点胶技术，形成高反射胶体50，以形成图5所示的发光二极管封装结构10d，其中高反射胶体50可填入凹槽21且包覆发光二极管40的侧面40s。
在另一实施例中，高反射胶体50可仅包覆静电保护元件30的至少一部分，但不包覆发光二极管40的侧面40s。在其它实施例中，可省略如图8F所示的高反射胶体50的形成步骤。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (10)

1.一种发光二极管封装结构，其特征在于，包括：
一承载基座，具有一第一导接垫及一第二导接垫；
一静电保护元件，设置在该承载基座上，具有一第一电极及一第二电极，且该第一、第二电极分别电性连接于该第一、第二导接垫；以及
一发光二极管，设置在该静电保护元件上方，具有一第三电极及一第四电极，该第三、第四电极分别电性连接于该第一、第二导接垫。
2.根据权利要求1所述的发光二极管封装结构，其特征在于，该承载基座具有一凹槽，该静电保护元件设置在该凹槽内。
3.根据权利要求2所述的发光二极管封装结构，其特征在于，还包括一高反射胶体，填充在该凹槽内，以固定该静电保护元件。
4.根据权利要求3所述的发光二极管封装结构，其特征在于，该高反射胶体进一步填充在该发光二极管的四周。
5.根据权利要求1所述的发光二极管封装结构，其特征在于，该静电保护元件为一齐纳二极管。
6.根据权利要求1所述的发光二极管封装结构，其特征在于，该静电保护元件的顶部设有一第一反射层。
7.根据权利要求1所述的发光二极管封装结构，其特征在于，该发光二极管的底部设有一第二反射层。
8.一种制作发光二极管封装结构的方法，其特征在于，包括以下步骤：
提供一承载基座，其中该承载基座具有一第一导接垫及一第二导接垫；
设置一静电保护元件在该承载基座上，其中该静电保护元件具有一第一电极及一第二电极；
使该第一电极及该第二电极分别电性连接于该第一导接垫及该第二导接垫；
设置一发光二极管在该静电保护元件的上方，其中该发光二极管具有一第三电极及一第四电极；以及
使该第三电极及该第四电极分别电性连接于该第一导接垫及该第二导接垫。
9.根据权利要求8所述的制作发光二极管封装结构的方法，其特征在于，还包括以下步骤：
设置该静电保护元件在该承载基座的一凹槽中。
10.根据权利要求9所述的制作发光二极管封装结构的方法，其特征在于，还包括以下步骤：
填充一高反射胶体在该凹槽内以固定该静电保护元件。
CN201610157175.2A 2015-03-18 2016-03-18 发光二极管封装结构及其制作方法 Pending CN105990499A (zh)

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