US20120061700A1 - Method and system for providing a reliable light emitting diode semiconductor device - Google Patents

Method and system for providing a reliable light emitting diode semiconductor device Download PDF

Info

Publication number
US20120061700A1
US20120061700A1 US12/878,043 US87804310A US2012061700A1 US 20120061700 A1 US20120061700 A1 US 20120061700A1 US 87804310 A US87804310 A US 87804310A US 2012061700 A1 US2012061700 A1 US 2012061700A1
Authority
US
United States
Prior art keywords
encapsulating material
encapsulating
emitting diode
light emitting
carrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/878,043
Inventor
Andreas Eder
Henrik Ewe
Stefan Landau
Joachim Mahler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to US12/878,043 priority Critical patent/US20120061700A1/en
Assigned to INFINEON TECHNOLOGIES AG reassignment INFINEON TECHNOLOGIES AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: EDER, ANDREAS, EWE, HENRIK, LANDAU, STEFAN, MAHLER, JOACHIM
Priority to DE201110053360 priority patent/DE102011053360A1/en
Publication of US20120061700A1 publication Critical patent/US20120061700A1/en
Priority to US13/921,060 priority patent/US9142739B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H01L33/56—Materials, e.g. epoxy or silicone resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H01L33/54—Encapsulations having a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

Definitions

  • the present invention relates generally to a reliable light emitting diode (LED) semiconductor device.
  • the present disclosure relates to a method and system for encapsulating and embedding LEDs to provide a reliable LED semiconductor device.
  • LEDs have been used widely in many applications due to its light sensing capability. In many current semiconductor applications, LEDs are mounted directly on a printed circuit board as individual components and electrically connected to other components, such as power and logic components, on the board. In other applications, LEDs are placed into semiconductor devices using silicone or silicon-based materials. These materials, however, has poor performances due to its high coefficient of thermal expansion (CTE), poor adhesive to metal and high moisture permeability. Therefore, a need exists for a method and system to provide a reliable LED semiconductor device that provides a better performance.
  • CTE coefficient of thermal expansion
  • FIGS. 1A to 1E are diagrams illustrating an exemplary process for forming a reliable LED semiconductor device accordance with one embodiment of the present disclosure.
  • FIG. 2 is a flowchart of an exemplary process for forming a reliable LED semiconductor in accordance with one embodiment of the present disclosure.
  • FIGS. 3A to 3E are diagrams illustrating a reliable LED semiconductor package in accordance with one embodiment of the present disclosure.
  • FIG. 4 is a flowchart of an exemplary process for forming a reliable LED semiconductor package in accordance with one embodiment of the present disclosure.
  • the present disclosure provides a reliable LED semiconductor device.
  • the device comprises a carrier, a light emitting diode disposed on the carrier, an encapsulating material disposed over the light emitting diode and the carrier, at least one through connection formed in the encapsulating material, and a metallization layer disposed and structured over the at least one through connection.
  • the device comprises a carrier, a light emitting diode and at least one semiconductor chip disposed on the carrier, an encapsulating material disposed over the light emitting diode, the at least one semiconductor device and the carrier, at least one through connection formed in the encapsulating material, and a metallization layer disposed and structured over the at least one through connection.
  • a method for forming a reliable LED semiconductor device comprises providing a carrier, disposing at least one light emitting diode on the carrier, encapsulating the at least one light emitting diode and the carrier with an encapsulating material, forming at least one through connection in the encapsulating material, and forming a metallization layer over the at least one through connection.
  • the semiconductor chips may be of extremely different types, may be manufactured by different technologies and may include for example, integrated electrical or electro-optical circuits or passives or MEMS etc.
  • Semiconductor chips may be configured, for example, as power transistors, power diodes, IGBTs (Isolated Gate Bipolar Transistors).
  • Semiconductor chips may have a vertical structure and may be fabricated in such a way that electrical currents can flow in a direction perpendicular to the main surfaces of the semiconductor chips. These semiconductor chips may have contact elements disposed on its main surfaces, which includes a top surface and a bottom surface. Examples of semiconductor chips having a vertical structure include power transistors and power diodes.
  • the source electrode and the gate electrode may be disposed on a first main surface while the drain electrode may be disposed on a second main surface.
  • the anode electrode may be disposed on a first main surface while the cathode electrode may be disposed on a second main surface.
  • the integrated circuits may, for example, be designed as logic integrated circuits, analog integrated circuits, mixed signal integrated circuits, power integrated circuits, memory circuits or integrated passives.
  • the semiconductor chips may be configured as MEMS (micro-electro mechanical systems) and may include micro-mechanical structures, such as bridges, membranes or tongue structures.
  • the semiconductor chips may be configured as sensors or actuators, for example, pressure sensors, acceleration sensors, rotation sensors, microphones etc.
  • the semiconductor chips may be configured as antennas and/or discrete passives.
  • the semiconductor chips may also include antennas and/or discrete passives.
  • Semiconductor chips, in which such functional elements are embedded generally contain electronic circuits which serve for driving the functional elements or further process signals generated by the functional elements.
  • the semiconductor chips need not be manufactured from specific semiconductor material and, furthermore, may contain inorganic and/or organic materials that are not semiconductors, such as for example, discrete passives, antennas, insulators, plastics or metals. Moreover, the semiconductor chips may be packaged or unpackaged.
  • the semiconductor chips have contact elements which allow electrical contact to be made with the semiconductor chips.
  • the contact elements may be composed of any desired electrically conductive material, for example, of a metal, such as aluminum, nickel, palladium, gold or copper, a metal alloy, a metal stack or an electrically conductive organic material.
  • the contact elements may be situated on the active main surfaces of the semiconductor chips or on other surfaces of the semiconductor chips.
  • the active or passive structures of the semiconductor chips are usually arranged below the active main surfaces and can be electrically contacted via the contact elements. In case of power transistors, the contact elements may be drain, source or date electrodes.
  • the devices described in the following may include external contact elements that are accessible from outside of the devices to allow electrical contact to be made from outside of the devices.
  • the external contact elements may be thermally conductive and serve as heat sinks for heat dissipation of the semiconductor chips.
  • the external contact elements may be composed of any electrically conductive material, for example, a metal such as copper, Pd, Ni, Au, etc.
  • the devices described in the following may include an encapsulating material covering at least parts of the semiconductor chips.
  • the encapsulating material is an electrically insulating material, which is at most marginally electrically conductive relative to the electrically conductive components of the device.
  • Examples of an encapsulating material include a mold material and an epoxy based material.
  • the encapsulating material may be any appropriate duroplastic, thermoplastic, laminate (prepreg) or thermosetting material and may contain filler materials.
  • Various techniques may be employed to cover the semiconductor chips with the mold material, for example, compression molding, lamination or injection molding.
  • the present disclosure provides a method and system for a reliable LED semiconductor device by encapsulating LEDs with a special encapsulating material that is highly transparent, in particular, to the blue color spectrum, and has good adhesion to metals.
  • the transparent encapsulating material has a low coefficient of thermal expansion and stability under high temperature. The resulting device is therefore easily integrated with other semiconductor devices and processes without affecting the performance of the LEDs.
  • a reliable LED semiconductor device 100 which comprises a carrier 102 serving as a lead frame.
  • the carrier 102 may be made of metals, ceramics, plastics or any other types of material.
  • the carrier 102 may be a structured or unstructured lead frame.
  • An adhesive layer 104 is then applied over the carrier 102 for attaching the LED 106 .
  • the adhesive layer 104 may be made of any adhesive material, such as metallic glue.
  • LED 106 is placed onto the carrier 102 over the adhesive layer 104 .
  • the LED 106 may comprise a first electrical contact 108 disposed on the back surface 110 of LED 106 and a second electrical contact 112 disposed on the top surface 114 of LED 106 .
  • a highly transparent encapsulating material 120 is applied to encapsulate carrier 102 and LED 106 .
  • the encapsulating material may be a reliable polymer material, such as acrylic resins, ormocers, epoxy-acrylate copolymer, silicon epoxy copolymer, etc.
  • the encapsulating material may be made of other polymer materials such as epoxy resins, which increases elasticity of the structure and provides good light transmission for a given wavelength range.
  • These types of encapsulating material have a very low light absorption in the full range of LED light wavelengths, but particularly, in a short wavelength range. In one example, these types of encapsulating material have a light absorption of less than five percent, but preferably less than one percent, over a full range of LED light wavelengths.
  • the LED wavelengths may range anywhere from infrared to ultra-violet.
  • these materials provide excellent adhesion to metals, in particular, to copper surfaces, and other types of materials, such as polymers and ceramics. These materials also have a low coefficient of thermal expansion, for example, less than 50 ppm/K, which provides stability even in high temperature, for example, temperature greater than 150° C.
  • the encapsulating material 120 may be applied by molding or other encapsulation methods.
  • a thin metal layer 122 is applied over the encapsulating material 120 .
  • the metal layer 122 may be made of metals such as copper to provide a RCC film.
  • the metal layer 122 may serve as a heat sink or dissipation for the structure or electrical contacts and redistribution layer for the LED 106 .
  • the thickness of the metal layer 122 may be a few micrometers.
  • metal layer 122 may be made of other types of metals or may have different thickness without departing the spirit and scope of the present disclosure.
  • a plurality of via openings 124 , 126 are formed in the encapsulating material 120 and optionally, the metal layer 122 , to provide through connections to the electrical contacts 108 and 112 of LED 106 .
  • via opening 124 is formed to provide a through connection to first electrical contact 108 disposed on the back surface 110 of LED 106 .
  • Via opening 126 is formed to provide a through connection to the second electrical contact 112 disposed on the top surface 114 of LED 106 .
  • the plurality of via openings 124 , 126 may be formed using laser drilling or plasma etching. However, other methods for forming the plurality of via openings may be used without departing the spirit and scope of the present disclosure.
  • the plurality of via openings 124 , 126 may be filled with a metal, such as copper, to form a metallization layer 128 .
  • a barrier layer may first be deposited (e.g. sputtered) over the plurality of via openings, in this example, via openings 124 , 126 and optionally the metal layer 122 .
  • the barrier layer may be composed of an electrically conductive material, such as chrome or titanium or an alloy of different metals like titanium and tungsten.
  • a seed layer may be deposited (e.g. sputtered) onto the barrier layer.
  • the seed layer may be composed of an electrically conductive material, such as copper.
  • electrically conductive material such as copper, or multiple layers of similar or different electrically conductive materials, such as copper, nickel, gold or palladium is galvanically deposited.
  • the electrically conductive material may be copper or any other conductive metal, and may consist of a layer stack of different metals, such as Copper, Nickel and Gold or copper, nickel and copper or copper, nickel and palladium.
  • a plating resist is placed over the barrier and/or seed layer.
  • the plating resist may be placed over the entire barrier and/or seed layer except the plurality of via openings, such as via openings 124 , 126 , and the wafer edge (edge exclusion).
  • the plating resist is exposed and developed after application with photolithography mask (Mask Aligner) or a reticle (Stepper).
  • photolithography mask Mask Aligner
  • a reticle reticle
  • Another possibility would be to structure the resist by laser (e.g. laser direct imaging) or apply the electrically conductive material already structured (e.g. printing). Dual damascene redistribution is possible as well.
  • the plating resist is stripped and the barrier and/or seed layer are removed chemically, for example, by wet etching.
  • the plating resist may be removed easily with common resist stripping technique.
  • the barrier and/or seed layer may be removed by wet etching. However, portions of the barrier and/or seed layer may be removed using other methods without departing the spirit and scope of the present disclosure.
  • metallization layer 128 is formed.
  • the metallization layer 128 is then structured to provide electrical connection to external component, such as a print circuit board.
  • portions of the metallization layer 128 are removed by ablation, such as photolithography.
  • portion 130 of metallization layer 128 is removed by ablation, which in turn exposes the highly transparent encapsulating material 120 .
  • the exposed highly transparent encapsulating material 120 allows LED 106 to absorb a full range of LED light wavelengths 132 , including the blue color spectrum.
  • Process 200 begins at step 202 to provide a carrier as a lead frame.
  • a metal carrier 102 is provided as a lead frame.
  • Process 200 then continues to step 204 to place an LED on the carrier over an adhesive layer.
  • LED 106 is placed onto carrier 102 over adhesive layer 104 .
  • Process 200 then continues to step 206 to encapsulate the LED and the carrier with a highly transparent encapsulating material.
  • encapsulating material 120 is applied to encapsulate LED 106 and carrier 102 .
  • the encapsulating material may be a reliable polymer material, such as acrylic resins, epoxy-acrylate copolymer, or other materials such as epoxy resins, that provides elasticity of the structure and good light transmission in a given wavelength range.
  • Process 200 then continues to step 208 to optionally apply a metal layer over the encapsulating material.
  • a metal layer 122 made of copper, may be applied over the encapsulating material 120 .
  • Process 200 then continues to step 210 to form a plurality of via openings in the encapsulating material and the optional metal layer to provide through connections to electrical contacts of the LED.
  • via openings 124 , 126 may be formed in metal layer 122 and encapsulating material 120 using laser drilling or plasma etching to provide through connections to contacts 114 and 108 of LED 106 .
  • an organic protective layer may be applied over the LED 106 , including at least contacts 114 and 108 of the LED 106 .
  • a thin organic layer referred to as optional conversion layer may be applied between contacts 114 and 108 of LED 106 and the organic sacrificial layer of the LED 106 to adjust the LED emitted light wavelength to a desired color spectrum.
  • Process 200 then continues to step 212 to fill the plurality of via openings with a metal to form a metallization layer.
  • via openings 124 , 126 may be filled with copper to form metallization layer 128 .
  • Process 200 then completes at step 214 to structure the metallization layer. For example, portion 130 of metallization layer 128 is removed by ablation to expose the transparent encapsulating material 120 .
  • the present disclosure provides a method and system for a reliable LED semiconductor package, which embeds the LED semiconductor device along with other semiconductor devices, such as power and logic components.
  • a reliable LED semiconductor package which embeds the LED semiconductor device along with other semiconductor devices, such as power and logic components.
  • FIGS. 3A to 3E diagrams illustrating a reliable LED semiconductor package are depicted in accordance with one embodiment of the present disclosure.
  • a plurality of semiconductor devices may be placed onto a carrier 302 .
  • an LED 306 an integrated circuit 308 for logic operations, and a power semiconductor device 310 may be placed onto carrier 302 .
  • the semiconductor devices 306 , 308 , and 310 may be placed onto carrier 302 over adhesive layer 304 .
  • Semiconductor devices 306 , 308 , and 310 may comprise first electrical contacts 312 on top surfaces 314 and second electrical contacts 316 on back surfaces 318 of devices 306 , 308 , and 310 for electrical connections to external components.
  • a highly transparent encapsulating material 320 is applied to encapsulate carrier 302 , LED 306 , IC 308 , and power component 310 .
  • the highly transparent encapsulating material 320 may be applied to encapsulate the LED 306 , the carrier 302 , the IC 308 and the power component 310 together.
  • the highly transparent encapsulating material may be disposed over the LED 306 alone, to provide low light absorption, low thermal coefficient and good adhesion to metals, while a second type of encapsulating material, or a common encapsulating material, such as epoxy, may be disposed over the carrier 302 , the IC 308 and the power component 310 . In this way, the cost of encapsulation may be reduced.
  • the encapsulating material 320 may be a reliable polymer material, such as acrylic resins, ormocers, silicon epoxy copolymer, epoxy-acrylate copolymer, etc.
  • the encapsulating material 320 may be made of other materials such as epoxy resins, which increases elasticity of the structure and provides good light transmission for a given wavelength range.
  • These types of encapsulating material have a very low light absorption in the full range of LED light wavelengths, but particularly, in a short wavelength range. In one example, these types of encapsulating material have a light absorption of less than five percent, but preferably less than one percent, over a full range of LED light wavelengths.
  • the LED wavelengths may range anywhere from infrared to ultra-violet.
  • these materials provide excellent adhesion to metals, in particular, to copper surfaces, and other types of materials, such as polymers and ceramics. These materials also have a low coefficient of thermal expansion, for example, less than 50 ppm/K, which provides stability even in high temperature, for example, temperature greater than 150° C.
  • the encapsulating material 320 may be applied by molding or other encapsulation methods.
  • a thin metal layer 322 is applied over the encapsulating material 320 .
  • the metal layer 322 may be made of metals such as copper to provide a RCC film.
  • the metal layer 322 may serve as a heat sink or dissipation for the structure or electrical contacts and redistribution layer for devices 306 , 308 , and 310 .
  • the thickness of the metal layer 322 may be a few micronmeters.
  • metal layer 322 may be made of other types of metals or may have different thickness without departing the spirit and scope of the present disclosure.
  • a plurality of via openings 324 , 326 are formed in the encapsulating material 320 and optionally, the metal layer 322 , to provide through connections to the first electrical contacts 312 on top surfaces 314 and second electrical contacts 316 on back surfaces 318 of devices 306 , 308 , and 310 .
  • the plurality of via openings 324 , 326 may be formed using laser drilling or plasma etching. However, other methods for forming the plurality of via openings may be used without departing the spirit and scope of the present disclosure.
  • the plurality of via openings 324 , 326 may be filled with a metal, such as copper, to form a metallization layer 328 .
  • a barrier layer may first be deposited (e.g. sputtered) over the plurality of via openings, in this example, via openings 324 , 326 and the optional metal layer 322 .
  • the barrier layer may be composed of an electrically conductive material, such as chrome or titanium or an alloy of different metals like titanium and tungsten.
  • a seed layer may be deposited (e.g. sputtered) onto the barrier layer.
  • the seed layer may be composed of an electrically conductive material, such as copper.
  • electrically conductive material such as copper, or multiple layers of similar or different electrically conductive materials, such as copper, nickel, gold or palladium is galvanically deposited.
  • the electrically conductive material may be copper or any other conductive metal, and may consist of a layer stack of different metals, such as Copper, Nickel and Gold or copper, nickel and copper or copper, nickel and palladium.
  • a plating resist is placed over the barrier and/or seed layer.
  • the plating resist may be placed over the entire barrier and/or seed layer except the plurality of via openings, such as via openings 324 , 326 and the wafer edge (edge exclusion).
  • the plating resist is exposed and developed after application with photolithography mask (Mask Aligner) or a reticle (Stepper).
  • photolithography mask Mask Aligner
  • a reticle reticle
  • Another possibility would be to structure the resist by laser (e.g. laser direct imaging) or apply the electrically conductive material already structured (e.g. printing). Dual damascene redistribution is possible as well.
  • the plating resist is stripped and the barrier and/or seed layer are removed chemically, for example, by wet etching.
  • the plating resist may be removed easily with common resist stripping technique.
  • the barrier and/or seed layer may be removed by wet etching. However, portions of the barrier and/or seed layer may be removed using other methods without departing the spirit and scope of the present disclosure.
  • metallization layer 328 is formed.
  • the metallization layer 328 is then structured to provide connection to external component, such as a print circuit board.
  • portions of the metallization layer 328 are removed by ablation, such as photolithography.
  • portions 330 of metallization layer 328 are removed by ablation, which in turn exposes the highly transparent encapsulating material 320 .
  • the exposed highly transparent encapsulating material 320 allows LED 306 to absorb a full range of LED light wavelengths 332 , including the blue color spectrum.
  • Process 400 begins at step 402 to provide a carrier as a lead frame.
  • a metal carrier 302 is provided as a lead frame.
  • Process 200 then continues to step 404 to place an LED and at least one semiconductor chip on the carrier over an adhesive layer.
  • LED 306 , integrated circuit 308 , and power semiconductor chip 310 are placed onto carrier 302 over adhesive layer 304 .
  • Process 400 then continues to step 406 to encapsulate the LED, the at least one semiconductor chip and the carrier with a highly transparent encapsulating material.
  • encapsulating material 120 is applied to encapsulate LED 306 , integrated circuit 308 , power semiconductor chip 310 and carrier 302 .
  • the encapsulating material may be a reliable polymer material, such as acrylic resins, epoxy-acrylate copolymer, or other epoxy materials such as epoxy resins, that provides elasticity of the structure and provides good light transmission in a given wavelength range.
  • Process 400 then continues to step 408 to optionally apply a metal layer over the encapsulating material.
  • a copper layer 322 may be applied over the encapsulating material 320 .
  • Process 400 then continues to step 410 to form a plurality of via openings in the encapsulating material and the optional metal layer to provide through connections to electrical contacts of the LED.
  • via openings 324 , 326 may be formed in copper layer 322 and encapsulating material 320 using laser drilling or plasma etching to provide through connections to contacts 312 and 316 of devices 306 , 308 , and 310 .
  • an organic protective layer may be applied over the LED 306 , including at least contacts 312 and 316 of the LED 306 .
  • a thin organic layer, referred to as optional conversion layer may be applied between contacts 312 and 316 of LED 306 and the organic sacrificial layer of the LED 306 to adjust the LED emitted light wavelength to a desired color spectrum.
  • Process 400 then continues to step 412 to fill the plurality of via openings with a metal to form a metallization layer.
  • via openings 324 , 326 may be filled with copper to form metallization layer 328 .
  • Process 400 then completes at step 414 to structure the metallization layer. For example, portions 330 of metallization layer 328 are removed by ablation to expose the transparent encapsulating material 320 .
  • the present disclosure also provides a method and a system for embedding LEDs in a semiconductor package along with other semiconductor devices by using a transparent encapsulating material.
  • the method and system provide a reliable solution for embedding LEDs without damaging the LED surface during the process and provide desirable properties for LED light absorption.
  • embodiments of the invention may be implemented in discrete circuits, partially integrated circuits or fully integrated circuits or programming means.
  • the term “exemplary” is merely meant as an example, rather than the best or optimal. It is also to be appreciated that features and/or elements depicted herein are illustrated with particular dimensions relative to one another for purposes of simplicity and ease of understanding, and that actual dimensions may differ substantially from that illustrated herein.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Led Device Packages (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A method and a system for a reliable LED semiconductor device are provided. In one embodiment, the device comprises a carrier, a light emitting diode disposed on the carrier, an encapsulating material disposed over the light emitting diode and the carrier, at least one through connection formed in the encapsulating material, and a metallization layer disposed and structured over the at least one through connection.

Description

    TECHNICAL FIELD
  • The present invention relates generally to a reliable light emitting diode (LED) semiconductor device. In particular, the present disclosure relates to a method and system for encapsulating and embedding LEDs to provide a reliable LED semiconductor device.
    • BACKGROUND
  • LEDs have been used widely in many applications due to its light sensing capability. In many current semiconductor applications, LEDs are mounted directly on a printed circuit board as individual components and electrically connected to other components, such as power and logic components, on the board. In other applications, LEDs are placed into semiconductor devices using silicone or silicon-based materials. These materials, however, has poor performances due to its high coefficient of thermal expansion (CTE), poor adhesive to metal and high moisture permeability. Therefore, a need exists for a method and system to provide a reliable LED semiconductor device that provides a better performance.
    • BRIEF DESCRIPTION OF DRAWINGS
  • FIGS. 1A to 1E are diagrams illustrating an exemplary process for forming a reliable LED semiconductor device accordance with one embodiment of the present disclosure.
  • FIG. 2 is a flowchart of an exemplary process for forming a reliable LED semiconductor in accordance with one embodiment of the present disclosure.
  • FIGS. 3A to 3E are diagrams illustrating a reliable LED semiconductor package in accordance with one embodiment of the present disclosure.
  • FIG. 4 is a flowchart of an exemplary process for forming a reliable LED semiconductor package in accordance with one embodiment of the present disclosure.
    •  SUMMARY OF INVENTION
  • The present disclosure provides a reliable LED semiconductor device. In one embodiment, the device comprises a carrier, a light emitting diode disposed on the carrier, an encapsulating material disposed over the light emitting diode and the carrier, at least one through connection formed in the encapsulating material, and a metallization layer disposed and structured over the at least one through connection.
  • In another embodiment, the device comprises a carrier, a light emitting diode and at least one semiconductor chip disposed on the carrier, an encapsulating material disposed over the light emitting diode, the at least one semiconductor device and the carrier, at least one through connection formed in the encapsulating material, and a metallization layer disposed and structured over the at least one through connection.
  • In yet another embodiment, a method for forming a reliable LED semiconductor device is provided. The method comprises providing a carrier, disposing at least one light emitting diode on the carrier, encapsulating the at least one light emitting diode and the carrier with an encapsulating material, forming at least one through connection in the encapsulating material, and forming a metallization layer over the at least one through connection.
    • DETAILED DESCRIPTION
  • In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
  • It is to be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically noted otherwise.
  • Devices with semiconductor chips are described below. The semiconductor chips may be of extremely different types, may be manufactured by different technologies and may include for example, integrated electrical or electro-optical circuits or passives or MEMS etc. Semiconductor chips may be configured, for example, as power transistors, power diodes, IGBTs (Isolated Gate Bipolar Transistors). Semiconductor chips may have a vertical structure and may be fabricated in such a way that electrical currents can flow in a direction perpendicular to the main surfaces of the semiconductor chips. These semiconductor chips may have contact elements disposed on its main surfaces, which includes a top surface and a bottom surface. Examples of semiconductor chips having a vertical structure include power transistors and power diodes. In case of power transistors, the source electrode and the gate electrode may be disposed on a first main surface while the drain electrode may be disposed on a second main surface. In case of a power diode, the anode electrode may be disposed on a first main surface while the cathode electrode may be disposed on a second main surface.
  • The integrated circuits may, for example, be designed as logic integrated circuits, analog integrated circuits, mixed signal integrated circuits, power integrated circuits, memory circuits or integrated passives. Furthermore, the semiconductor chips may be configured as MEMS (micro-electro mechanical systems) and may include micro-mechanical structures, such as bridges, membranes or tongue structures. The semiconductor chips may be configured as sensors or actuators, for example, pressure sensors, acceleration sensors, rotation sensors, microphones etc. The semiconductor chips may be configured as antennas and/or discrete passives. The semiconductor chips may also include antennas and/or discrete passives. Semiconductor chips, in which such functional elements are embedded, generally contain electronic circuits which serve for driving the functional elements or further process signals generated by the functional elements. The semiconductor chips need not be manufactured from specific semiconductor material and, furthermore, may contain inorganic and/or organic materials that are not semiconductors, such as for example, discrete passives, antennas, insulators, plastics or metals. Moreover, the semiconductor chips may be packaged or unpackaged.
  • The semiconductor chips have contact elements which allow electrical contact to be made with the semiconductor chips. The contact elements may be composed of any desired electrically conductive material, for example, of a metal, such as aluminum, nickel, palladium, gold or copper, a metal alloy, a metal stack or an electrically conductive organic material. The contact elements may be situated on the active main surfaces of the semiconductor chips or on other surfaces of the semiconductor chips. The active or passive structures of the semiconductor chips are usually arranged below the active main surfaces and can be electrically contacted via the contact elements. In case of power transistors, the contact elements may be drain, source or date electrodes.
  • The devices described in the following may include external contact elements that are accessible from outside of the devices to allow electrical contact to be made from outside of the devices. In addition, the external contact elements may be thermally conductive and serve as heat sinks for heat dissipation of the semiconductor chips. The external contact elements may be composed of any electrically conductive material, for example, a metal such as copper, Pd, Ni, Au, etc.
  • The devices described in the following may include an encapsulating material covering at least parts of the semiconductor chips. The encapsulating material is an electrically insulating material, which is at most marginally electrically conductive relative to the electrically conductive components of the device. Examples of an encapsulating material include a mold material and an epoxy based material. The encapsulating material may be any appropriate duroplastic, thermoplastic, laminate (prepreg) or thermosetting material and may contain filler materials. Various techniques may be employed to cover the semiconductor chips with the mold material, for example, compression molding, lamination or injection molding.
  • The present disclosure provides a method and system for a reliable LED semiconductor device by encapsulating LEDs with a special encapsulating material that is highly transparent, in particular, to the blue color spectrum, and has good adhesion to metals. In addition, the transparent encapsulating material has a low coefficient of thermal expansion and stability under high temperature. The resulting device is therefore easily integrated with other semiconductor devices and processes without affecting the performance of the LEDs.
  • Referring to FIGS. 1A to 1E, diagrams illustrating an exemplary process for forming a reliable LED semiconductor device are depicted in accordance with one embodiment of the present disclosure. As shown in FIG. 1A, a reliable LED semiconductor device 100 is provided which comprises a carrier 102 serving as a lead frame. The carrier 102 may be made of metals, ceramics, plastics or any other types of material. The carrier 102 may be a structured or unstructured lead frame. An adhesive layer 104 is then applied over the carrier 102 for attaching the LED 106. The adhesive layer 104 may be made of any adhesive material, such as metallic glue. LED 106 is placed onto the carrier 102 over the adhesive layer 104. The LED 106 may comprise a first electrical contact 108 disposed on the back surface 110 of LED 106 and a second electrical contact 112 disposed on the top surface 114 of LED 106.
  • Referring to FIG. 1B, a highly transparent encapsulating material 120 is applied to encapsulate carrier 102 and LED 106. In one embodiment, the encapsulating material may be a reliable polymer material, such as acrylic resins, ormocers, epoxy-acrylate copolymer, silicon epoxy copolymer, etc. Alternatively, the encapsulating material may be made of other polymer materials such as epoxy resins, which increases elasticity of the structure and provides good light transmission for a given wavelength range.
  • These types of encapsulating material have a very low light absorption in the full range of LED light wavelengths, but particularly, in a short wavelength range. In one example, these types of encapsulating material have a light absorption of less than five percent, but preferably less than one percent, over a full range of LED light wavelengths. The LED wavelengths may range anywhere from infrared to ultra-violet.
  • In addition, these materials provide excellent adhesion to metals, in particular, to copper surfaces, and other types of materials, such as polymers and ceramics. These materials also have a low coefficient of thermal expansion, for example, less than 50 ppm/K, which provides stability even in high temperature, for example, temperature greater than 150° C. The encapsulating material 120 may be applied by molding or other encapsulation methods.
  • Optionally, a thin metal layer 122 is applied over the encapsulating material 120. The metal layer 122 may be made of metals such as copper to provide a RCC film. The metal layer 122 may serve as a heat sink or dissipation for the structure or electrical contacts and redistribution layer for the LED 106. The thickness of the metal layer 122 may be a few micrometers. However, metal layer 122 may be made of other types of metals or may have different thickness without departing the spirit and scope of the present disclosure.
  • Referring to FIG. 1C, a plurality of via openings 124, 126 are formed in the encapsulating material 120 and optionally, the metal layer 122, to provide through connections to the electrical contacts 108 and 112 of LED 106. For example, via opening 124 is formed to provide a through connection to first electrical contact 108 disposed on the back surface 110 of LED 106. Via opening 126 is formed to provide a through connection to the second electrical contact 112 disposed on the top surface 114 of LED 106.
  • In one embodiment, the plurality of via openings 124, 126 may be formed using laser drilling or plasma etching. However, other methods for forming the plurality of via openings may be used without departing the spirit and scope of the present disclosure.
  • Referring to FIG. 1D, the plurality of via openings 124, 126 may be filled with a metal, such as copper, to form a metallization layer 128. To fill the plurality of via openings, a barrier layer may first be deposited (e.g. sputtered) over the plurality of via openings, in this example, via openings 124, 126 and optionally the metal layer 122. The barrier layer may be composed of an electrically conductive material, such as chrome or titanium or an alloy of different metals like titanium and tungsten. Then, a seed layer may be deposited (e.g. sputtered) onto the barrier layer. The seed layer may be composed of an electrically conductive material, such as copper.
  • After a barrier and/or seed layer is applied, another layer of electrically conductive material, such as copper, or multiple layers of similar or different electrically conductive materials, such as copper, nickel, gold or palladium is galvanically deposited. The electrically conductive material may be copper or any other conductive metal, and may consist of a layer stack of different metals, such as Copper, Nickel and Gold or copper, nickel and copper or copper, nickel and palladium.
  • Before the electrically conductive material is applied, a plating resist is placed over the barrier and/or seed layer. The plating resist may be placed over the entire barrier and/or seed layer except the plurality of via openings, such as via openings 124, 126, and the wafer edge (edge exclusion). Typically, the plating resist is exposed and developed after application with photolithography mask (Mask Aligner) or a reticle (Stepper). Another possibility would be to structure the resist by laser (e.g. laser direct imaging) or apply the electrically conductive material already structured (e.g. printing). Dual damascene redistribution is possible as well.
  • After electrically conductive material is applied into areas not covered by the plating resist, the plating resist is stripped and the barrier and/or seed layer are removed chemically, for example, by wet etching. The plating resist may be removed easily with common resist stripping technique. The barrier and/or seed layer may be removed by wet etching. However, portions of the barrier and/or seed layer may be removed using other methods without departing the spirit and scope of the present disclosure.
  • Referring to FIG. 1E, after the plating resist and the barrier and/or seed layer is removed, metallization layer 128 is formed. The metallization layer 128 is then structured to provide electrical connection to external component, such as a print circuit board. In this example, portions of the metallization layer 128 are removed by ablation, such as photolithography. As shown in FIG. 1E, portion 130 of metallization layer 128 is removed by ablation, which in turn exposes the highly transparent encapsulating material 120. The exposed highly transparent encapsulating material 120 allows LED 106 to absorb a full range of LED light wavelengths 132, including the blue color spectrum.
  • Referring to FIG. 2, a flowchart of an exemplary process for forming a reliable LED semiconductor package is depicted in accordance with one embodiment of the present disclosure. Process 200 begins at step 202 to provide a carrier as a lead frame. For example, a metal carrier 102 is provided as a lead frame. Process 200 then continues to step 204 to place an LED on the carrier over an adhesive layer. For example, LED 106 is placed onto carrier 102 over adhesive layer 104.
  • Process 200 then continues to step 206 to encapsulate the LED and the carrier with a highly transparent encapsulating material. For example, encapsulating material 120 is applied to encapsulate LED 106 and carrier 102. The encapsulating material may be a reliable polymer material, such as acrylic resins, epoxy-acrylate copolymer, or other materials such as epoxy resins, that provides elasticity of the structure and good light transmission in a given wavelength range.
  • Process 200 then continues to step 208 to optionally apply a metal layer over the encapsulating material. For example, a metal layer 122, made of copper, may be applied over the encapsulating material 120. Process 200 then continues to step 210 to form a plurality of via openings in the encapsulating material and the optional metal layer to provide through connections to electrical contacts of the LED. For example, via openings 124, 126 may be formed in metal layer 122 and encapsulating material 120 using laser drilling or plasma etching to provide through connections to contacts 114 and 108 of LED 106.
  • To protect contacts 114 and 108 from laser damage, an organic protective layer may be applied over the LED 106, including at least contacts 114 and 108 of the LED 106. Alternatively, a thin organic layer, referred to as optional conversion layer may be applied between contacts 114 and 108 of LED 106 and the organic sacrificial layer of the LED 106 to adjust the LED emitted light wavelength to a desired color spectrum.
  • Process 200 then continues to step 212 to fill the plurality of via openings with a metal to form a metallization layer. For example, via openings 124, 126 may be filled with copper to form metallization layer 128. Process 200 then completes at step 214 to structure the metallization layer. For example, portion 130 of metallization layer 128 is removed by ablation to expose the transparent encapsulating material 120.
  • In addition to an LED semiconductor device 100 as illustrated above, the present disclosure provides a method and system for a reliable LED semiconductor package, which embeds the LED semiconductor device along with other semiconductor devices, such as power and logic components. Referring to FIGS. 3A to 3E, diagrams illustrating a reliable LED semiconductor package are depicted in accordance with one embodiment of the present disclosure.
  • As shown in FIG. 3A, a plurality of semiconductor devices may be placed onto a carrier 302. For example, an LED 306, an integrated circuit 308 for logic operations, and a power semiconductor device 310 may be placed onto carrier 302. In one embodiment, the semiconductor devices 306, 308, and 310 may be placed onto carrier 302 over adhesive layer 304. Semiconductor devices 306, 308, and 310 may comprise first electrical contacts 312 on top surfaces 314 and second electrical contacts 316 on back surfaces 318 of devices 306, 308, and 310 for electrical connections to external components.
  • Referring to FIG. 3B, a highly transparent encapsulating material 320 is applied to encapsulate carrier 302, LED 306, IC 308, and power component 310. In one embodiment, the highly transparent encapsulating material 320 may be applied to encapsulate the LED 306, the carrier 302, the IC 308 and the power component 310 together. In another embodiment, the highly transparent encapsulating material may be disposed over the LED 306 alone, to provide low light absorption, low thermal coefficient and good adhesion to metals, while a second type of encapsulating material, or a common encapsulating material, such as epoxy, may be disposed over the carrier 302, the IC 308 and the power component 310. In this way, the cost of encapsulation may be reduced.
  • In one embodiment, the encapsulating material 320 may be a reliable polymer material, such as acrylic resins, ormocers, silicon epoxy copolymer, epoxy-acrylate copolymer, etc. Alternatively, the encapsulating material 320 may be made of other materials such as epoxy resins, which increases elasticity of the structure and provides good light transmission for a given wavelength range.
  • These types of encapsulating material have a very low light absorption in the full range of LED light wavelengths, but particularly, in a short wavelength range. In one example, these types of encapsulating material have a light absorption of less than five percent, but preferably less than one percent, over a full range of LED light wavelengths. The LED wavelengths may range anywhere from infrared to ultra-violet.
  • In addition, these materials provide excellent adhesion to metals, in particular, to copper surfaces, and other types of materials, such as polymers and ceramics. These materials also have a low coefficient of thermal expansion, for example, less than 50 ppm/K, which provides stability even in high temperature, for example, temperature greater than 150° C. The encapsulating material 320 may be applied by molding or other encapsulation methods.
  • Optionally, a thin metal layer 322 is applied over the encapsulating material 320. The metal layer 322 may be made of metals such as copper to provide a RCC film. The metal layer 322 may serve as a heat sink or dissipation for the structure or electrical contacts and redistribution layer for devices 306, 308, and 310. The thickness of the metal layer 322 may be a few micronmeters. However, metal layer 322 may be made of other types of metals or may have different thickness without departing the spirit and scope of the present disclosure.
  • Referring to FIG. 3C, a plurality of via openings 324, 326 are formed in the encapsulating material 320 and optionally, the metal layer 322, to provide through connections to the first electrical contacts 312 on top surfaces 314 and second electrical contacts 316 on back surfaces 318 of devices 306, 308, and 310. In one embodiment, the plurality of via openings 324, 326 may be formed using laser drilling or plasma etching. However, other methods for forming the plurality of via openings may be used without departing the spirit and scope of the present disclosure.
  • Referring to FIG. 3D, the plurality of via openings 324, 326 may be filled with a metal, such as copper, to form a metallization layer 328. To fill the plurality of via openings 324, 326, a barrier layer may first be deposited (e.g. sputtered) over the plurality of via openings, in this example, via openings 324, 326 and the optional metal layer 322. The barrier layer may be composed of an electrically conductive material, such as chrome or titanium or an alloy of different metals like titanium and tungsten. Then, a seed layer may be deposited (e.g. sputtered) onto the barrier layer. The seed layer may be composed of an electrically conductive material, such as copper.
  • After a barrier and/or seed layer is applied, another layer of electrically conductive material, such as copper, or multiple layers of similar or different electrically conductive materials, such as copper, nickel, gold or palladium is galvanically deposited. The electrically conductive material may be copper or any other conductive metal, and may consist of a layer stack of different metals, such as Copper, Nickel and Gold or copper, nickel and copper or copper, nickel and palladium.
  • Before the electrically conductive material is applied, a plating resist is placed over the barrier and/or seed layer. The plating resist may be placed over the entire barrier and/or seed layer except the plurality of via openings, such as via openings 324, 326 and the wafer edge (edge exclusion). Typically, the plating resist is exposed and developed after application with photolithography mask (Mask Aligner) or a reticle (Stepper). Another possibility would be to structure the resist by laser (e.g. laser direct imaging) or apply the electrically conductive material already structured (e.g. printing). Dual damascene redistribution is possible as well.
  • After electrically conductive material is applied into areas not covered by the plating resist, the plating resist is stripped and the barrier and/or seed layer are removed chemically, for example, by wet etching. The plating resist may be removed easily with common resist stripping technique. The barrier and/or seed layer may be removed by wet etching. However, portions of the barrier and/or seed layer may be removed using other methods without departing the spirit and scope of the present disclosure.
  • Referring to FIG. 3E, after the plating resist and the barrier and/or seed layer are removed, metallization layer 328 is formed. The metallization layer 328 is then structured to provide connection to external component, such as a print circuit board. In this example, portions of the metallization layer 328 are removed by ablation, such as photolithography. As shown in FIG. 3E, portions 330 of metallization layer 328 are removed by ablation, which in turn exposes the highly transparent encapsulating material 320. The exposed highly transparent encapsulating material 320 allows LED 306 to absorb a full range of LED light wavelengths 332, including the blue color spectrum.
  • Referring to FIG. 4, a flowchart of an exemplary process for forming a reliable LED semiconductor package is depicted in accordance with one embodiment of the present disclosure. Process 400 begins at step 402 to provide a carrier as a lead frame. For example, a metal carrier 302 is provided as a lead frame. Process 200 then continues to step 404 to place an LED and at least one semiconductor chip on the carrier over an adhesive layer. For example, LED 306, integrated circuit 308, and power semiconductor chip 310 are placed onto carrier 302 over adhesive layer 304.
  • Process 400 then continues to step 406 to encapsulate the LED, the at least one semiconductor chip and the carrier with a highly transparent encapsulating material. For example, encapsulating material 120 is applied to encapsulate LED 306, integrated circuit 308, power semiconductor chip 310 and carrier 302. The encapsulating material may be a reliable polymer material, such as acrylic resins, epoxy-acrylate copolymer, or other epoxy materials such as epoxy resins, that provides elasticity of the structure and provides good light transmission in a given wavelength range.
  • Process 400 then continues to step 408 to optionally apply a metal layer over the encapsulating material. For example, a copper layer 322 may be applied over the encapsulating material 320. Process 400 then continues to step 410 to form a plurality of via openings in the encapsulating material and the optional metal layer to provide through connections to electrical contacts of the LED. For example, via openings 324, 326 may be formed in copper layer 322 and encapsulating material 320 using laser drilling or plasma etching to provide through connections to contacts 312 and 316 of devices 306, 308, and 310. To protect contacts 312 and 316 from laser damage, an organic protective layer may be applied over the LED 306, including at least contacts 312 and 316 of the LED 306. Alternatively, a thin organic layer, referred to as optional conversion layer may be applied between contacts 312 and 316 of LED 306 and the organic sacrificial layer of the LED 306 to adjust the LED emitted light wavelength to a desired color spectrum.
  • Process 400 then continues to step 412 to fill the plurality of via openings with a metal to form a metallization layer. For example, via openings 324, 326 may be filled with copper to form metallization layer 328. Process 400 then completes at step 414 to structure the metallization layer. For example, portions 330 of metallization layer 328 are removed by ablation to expose the transparent encapsulating material 320.
  • Thus, the present disclosure also provides a method and a system for embedding LEDs in a semiconductor package along with other semiconductor devices by using a transparent encapsulating material. The method and system provide a reliable solution for embedding LEDs without damaging the LED surface during the process and provide desirable properties for LED light absorption.
  • In addition, while a particular feature or aspect of an embodiment of the invention may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “include”, “have”, “with”, or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term “comprise”. The terms “coupled” and “connected”, along with derivatives may have been used. It should be understood that these terms may have been used to indicate that two elements co-operate or interact with each other regardless whether they are in direct physical or electrical contact, or they are not in direct contact with each other. Furthermore, it should be understood that embodiments of the invention may be implemented in discrete circuits, partially integrated circuits or fully integrated circuits or programming means. Also, the term “exemplary” is merely meant as an example, rather than the best or optimal. It is also to be appreciated that features and/or elements depicted herein are illustrated with particular dimensions relative to one another for purposes of simplicity and ease of understanding, and that actual dimensions may differ substantially from that illustrated herein.
  • Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.

Claims (30)

What is claimed:
1. A semiconductor device comprising:
a carrier;
a light emitting diode disposed on the carrier;
an encapsulating material disposed over the light emitting diode;
at least one through connection formed in the encapsulating material; and
a metallization layer disposed and structured over the at least one through connection.
2. The device of claim 1, further comprising:
a metal layer disposed over the encapsulating material.
3. The device of claim 1, wherein the encapsulating material is a polymer material.
4. The device of claim 3, wherein the polymer material is acrylic resin, ormocers, silicon epoxy copolymer or epoxy-acrylate copolymer.
5. The device of claim 3, wherein the polymer material is epoxy resin.
6. The device of claim 1, wherein the encapsulating material is a low light absorbing material absorbing light in a full wavelength range.
7. The device of claim 6, wherein the encapsulating material is a low light absorbing material absorbing light in a short wavelength range of a full wavelength range.
8. The device of claim 1, wherein the encapsulating material is highly transparent, and has a low coefficient of thermal expansion.
9. The device of claim 1, wherein the at least one through connection is at least one via opening to at least one contact of the light emitting diode.
10. The device of claim 1, further comprising:
an organic protective layer disposed over the light emitting diode.
11. The device of claim 9, further comprising:
an optical conversion layer disposed between the at least one contact and an organic sacrificial layer of the light emitting diode.
12. A semiconductor device comprising:
a carrier;
a light emitting diode and at least one semiconductor chip disposed on the carrier;
a first type of encapsulating material disposed over the light emitting diode;
a second type of encapsulating material disposed over at least one of the at least one semiconductor chip and the carrier;
at least one through connection formed in the encapsulating material; and
a metallization layer disposed and structured over the at least one through connection.
13. The device of claim 12, wherein the first type of encapsulating material is a polymer material.
14. The device of claim 12, wherein the first type of encapsulating material and the second type of encapsulating material is a same material.
15. The device of claim 12, wherein the second type of encapsulating material is an epoxy.
16. The device of claim 12, wherein the first type of encapsulating material is a low light absorbing material absorbing light in a full wavelength range.
17. The device of claim 16, wherein the first type of encapsulating material is a low light absorbing material absorbing light in a short wavelength range of the full wavelength range.
18. The device of claim 12, wherein the first type of encapsulating material is highly transparent and has a low coefficient of thermal expansion.
19. The device of claim 12, wherein the at least one semiconductor chip comprises a power semiconductor chip and an integrated circuit.
20. The device of claim 12, wherein the at least one through connection is at least one via opening to at least one contact of the light emitting diode and at least one of the at least one semiconductor chip.
21. A method for forming a semiconductor device comprising:
providing a carrier;
disposing at least one light emitting diode on the carrier;
encapsulating the at least one light emitting diode with an encapsulating material;
forming at least one through connection in the encapsulating material; and
forming a metallization layer over the at least one through connection.
22. The method of claim 21, wherein encapsulating the at least one light emitting diode and the carrier with an encapsulating material comprises:
encapsulating the at least one light emitting diode and the carrier with an encapsulating material having a low coefficient of thermal expansion.
23. The method of claim 21, wherein encapsulating the at least one light emitting diode with an encapsulating material comprises:
encapsulating the at least one light emitting diode with a low light absorbing material absorbing light in a full wavelength range.
24. The method of claim 23, wherein encapsulating the at least one light emitting diode with an encapsulating material comprises:
encapsulating the at least one light emitting diode with a low light absorbing material absorbing light in a short wavelength range of the full wavelength range.
25. The method of claim 21, wherein encapsulating the at least one light emitting diode with an encapsulating material comprises:
encapsulating the at least one light emitting diode with an encapsulating material that is highly transparent.
26. The method of claim 21, further comprising:
forming a metal layer over the encapsulating material.
27. The method of claim 26, wherein forming at least one through connection in the encapsulating material comprises:
forming at least one via opening in the encapsulating material and the metal layer.
28. The method of claim 21, wherein forming a metallization layer over the at least one through connection comprises:
filling the at least one through connection with a metal; and
removing portions of the metal to expose the encapsulating material.
29. The method of claim 21, further comprising:
encapsulating at least one semiconductor chip and the carrier with the encapsulating material
30. The method of claim 21, further comprising:
encapsulating at least one semiconductor chip and the carrier with an encapsulating material different from the encapsulating material for encapsulating the at least one light emitting diode.
US12/878,043 2010-09-09 2010-09-09 Method and system for providing a reliable light emitting diode semiconductor device Abandoned US20120061700A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US12/878,043 US20120061700A1 (en) 2010-09-09 2010-09-09 Method and system for providing a reliable light emitting diode semiconductor device
DE201110053360 DE102011053360A1 (en) 2010-09-09 2011-09-07 METHOD AND SYSTEM FOR PROVIDING A RELIABLE LIGHT DIODE SEMICONDUCTOR COMPONENT
US13/921,060 US9142739B2 (en) 2010-09-09 2013-06-18 Method and system for providing a reliable light emitting diode semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/878,043 US20120061700A1 (en) 2010-09-09 2010-09-09 Method and system for providing a reliable light emitting diode semiconductor device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13/921,060 Division US9142739B2 (en) 2010-09-09 2013-06-18 Method and system for providing a reliable light emitting diode semiconductor device

Publications (1)

Publication Number Publication Date
US20120061700A1 true US20120061700A1 (en) 2012-03-15

Family

ID=45756226

Family Applications (2)

Application Number Title Priority Date Filing Date
US12/878,043 Abandoned US20120061700A1 (en) 2010-09-09 2010-09-09 Method and system for providing a reliable light emitting diode semiconductor device
US13/921,060 Expired - Fee Related US9142739B2 (en) 2010-09-09 2013-06-18 Method and system for providing a reliable light emitting diode semiconductor device

Family Applications After (1)

Application Number Title Priority Date Filing Date
US13/921,060 Expired - Fee Related US9142739B2 (en) 2010-09-09 2013-06-18 Method and system for providing a reliable light emitting diode semiconductor device

Country Status (2)

Country Link
US (2) US20120061700A1 (en)
DE (1) DE102011053360A1 (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102800585A (en) * 2012-07-09 2012-11-28 厦门飞德利照明科技有限公司 Electroforming manufacturing method for light-emitting diode
US20130089199A1 (en) * 2011-10-11 2013-04-11 Zarlink Semiconductor (U.S.) Inc. Communication System in a Package Formed on a Metal Microstructure
US20150333227A1 (en) * 2014-05-14 2015-11-19 Genesis Photonics Inc. Light emitting device package structure and manufacturing method thereof
US9831399B2 (en) 2014-06-12 2017-11-28 Genesis Photonics Inc. Light emitting component
US9882096B2 (en) 2015-03-18 2018-01-30 Genesis Photonics Inc. Light emitting diode structure and method for manufacturing the same
KR20180016982A (en) * 2015-04-07 2018-02-20 벤자민 기틴스 Programmable memory transfer requesting units
US9922963B2 (en) 2015-09-18 2018-03-20 Genesis Photonics Inc. Light-emitting device
US9953956B2 (en) 2015-03-18 2018-04-24 Genesis Photonics Inc. Package substrate and package structure using the same
US9997676B2 (en) 2014-05-14 2018-06-12 Genesis Photonics Inc. Light emitting device and manufacturing method thereof
US10388838B2 (en) 2016-10-19 2019-08-20 Genesis Photonics Inc. Light-emitting device and manufacturing method thereof
TWI672784B (en) * 2018-07-31 2019-09-21 台達電子工業股份有限公司 Package structures and methods for fabricating the same
CN110431675A (en) * 2017-03-13 2019-11-08 欧司朗光电半导体有限公司 Device with enhancement layer and the method for manufacturing device
US10784423B2 (en) 2017-11-05 2020-09-22 Genesis Photonics Inc. Light emitting device

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102018101813A1 (en) 2018-01-26 2019-08-01 Osram Opto Semiconductors Gmbh OPTOELECTRONIC SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING OPTOELECTRONIC SEMICONDUCTOR COMPONENTS
DE102018120637A1 (en) * 2018-08-23 2020-02-27 Osram Opto Semiconductors Gmbh CIRCUIT BOARD AND METHOD FOR PRODUCING A CIRCUIT BOARD WITH AT LEAST ONE OPTOELECTRONIC COMPONENT INTEGRATED INTO THE CIRCUIT BOARD
EP4012753A1 (en) 2020-12-08 2022-06-15 Hitachi Energy Switzerland AG Semiconductor device, semiconductor module and manufacturing method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080035935A1 (en) * 2006-08-11 2008-02-14 Shum Frank T Surface mountable chip
US20100301367A1 (en) * 2009-06-01 2010-12-02 Nitto Denko Corporation Light-emitting device comprising a dome-shaped ceramic phosphor
US20120104562A1 (en) * 2010-08-27 2012-05-03 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Stepped Interconnect Layer for Stacked Semiconductor Die
US20120322178A1 (en) * 2004-09-13 2012-12-20 Osram Opto Semiconductors Gmbh Method of Producing a Radiation-Emitting Optoelectronic Component

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19954941C2 (en) 1999-11-16 2003-11-06 Fraunhofer Ges Forschung Method for integrating a chip within a printed circuit board
DE102007017831B8 (en) 2007-04-16 2016-02-18 Infineon Technologies Ag Semiconductor module and a method for producing a semiconductor module
US8338936B2 (en) * 2008-07-24 2012-12-25 Infineon Technologies Ag Semiconductor device and manufacturing method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120322178A1 (en) * 2004-09-13 2012-12-20 Osram Opto Semiconductors Gmbh Method of Producing a Radiation-Emitting Optoelectronic Component
US20080035935A1 (en) * 2006-08-11 2008-02-14 Shum Frank T Surface mountable chip
US20100301367A1 (en) * 2009-06-01 2010-12-02 Nitto Denko Corporation Light-emitting device comprising a dome-shaped ceramic phosphor
US20120104562A1 (en) * 2010-08-27 2012-05-03 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Stepped Interconnect Layer for Stacked Semiconductor Die

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130089199A1 (en) * 2011-10-11 2013-04-11 Zarlink Semiconductor (U.S.) Inc. Communication System in a Package Formed on a Metal Microstructure
CN102800585A (en) * 2012-07-09 2012-11-28 厦门飞德利照明科技有限公司 Electroforming manufacturing method for light-emitting diode
US9997676B2 (en) 2014-05-14 2018-06-12 Genesis Photonics Inc. Light emitting device and manufacturing method thereof
US20150333227A1 (en) * 2014-05-14 2015-11-19 Genesis Photonics Inc. Light emitting device package structure and manufacturing method thereof
US9831399B2 (en) 2014-06-12 2017-11-28 Genesis Photonics Inc. Light emitting component
US9882096B2 (en) 2015-03-18 2018-01-30 Genesis Photonics Inc. Light emitting diode structure and method for manufacturing the same
US9953956B2 (en) 2015-03-18 2018-04-24 Genesis Photonics Inc. Package substrate and package structure using the same
KR20180016982A (en) * 2015-04-07 2018-02-20 벤자민 기틴스 Programmable memory transfer requesting units
KR101891686B1 (en) 2015-04-07 2018-08-27 벤자민 기틴스 Programmable memory transfer requesting units
US9922963B2 (en) 2015-09-18 2018-03-20 Genesis Photonics Inc. Light-emitting device
US10497681B2 (en) 2015-09-18 2019-12-03 Genesis Photonics Inc. Light-emitting device
US10957674B2 (en) 2015-09-18 2021-03-23 Genesis Photonics Inc Manufacturing method
US10388838B2 (en) 2016-10-19 2019-08-20 Genesis Photonics Inc. Light-emitting device and manufacturing method thereof
CN110431675A (en) * 2017-03-13 2019-11-08 欧司朗光电半导体有限公司 Device with enhancement layer and the method for manufacturing device
US10784423B2 (en) 2017-11-05 2020-09-22 Genesis Photonics Inc. Light emitting device
TWI672784B (en) * 2018-07-31 2019-09-21 台達電子工業股份有限公司 Package structures and methods for fabricating the same
US10573618B1 (en) 2018-07-31 2020-02-25 Delta Electronics, Inc. Package structures and methods for fabricating the same

Also Published As

Publication number Publication date
US9142739B2 (en) 2015-09-22
DE102011053360A1 (en) 2012-03-15
US20130277704A1 (en) 2013-10-24

Similar Documents

Publication Publication Date Title
US9142739B2 (en) Method and system for providing a reliable light emitting diode semiconductor device
US10446726B2 (en) Wafer level packaging of electronic devices
US9978720B2 (en) Insulated die
US8598709B2 (en) Method and system for routing electrical connections of semiconductor chips
US7019406B2 (en) Thermally enhanced semiconductor package
US8258633B2 (en) Semiconductor package and multichip arrangement having a polymer layer and an encapsulant
US8294275B2 (en) Chip package and method for forming the same
KR102673994B1 (en) Semiconductor package and method of manufacturing the same
US10483133B2 (en) Method for fabricating a semiconductor chip panel
US20170148966A1 (en) Surface-Mountable Semiconductor Component and Method for Producing Same
US8878335B2 (en) Method and system for providing fusing after packaging of semiconductor devices
US9842794B2 (en) Semiconductor package with integrated heatsink
US20190051802A1 (en) Semiconductor component and method for producing a semiconductor component
KR20000074356A (en) Semiconductor chip package and method for fabricating thereof
US9502344B2 (en) Wafer level packaging of electronic device
US8722462B2 (en) Semiconductor package
US8631566B2 (en) Circuit board structure comprising an electrical component and a method for manufacturing a circuit board structure comprising an electrical component
US20170178993A1 (en) Electronic component and methods of manufacturing the same
US10763406B2 (en) Semiconductor component comprising a first and a second shaped body and method for producing a semiconductor component comprising a first and a second shaped body
US20120080706A1 (en) Chip package and method for forming the same
US20230002217A1 (en) Semiconductor devices and related methods
KR101474127B1 (en) Heat sinking structure of semiconductor substrate
CN118737978A (en) Method for preparing semiconductor structure and semiconductor structure

Legal Events

Date Code Title Description
AS Assignment

Owner name: INFINEON TECHNOLOGIES AG, GERMANY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:EDER, ANDREAS;EWE, HENRIK;LANDAU, STEFAN;AND OTHERS;SIGNING DATES FROM 20100830 TO 20100906;REEL/FRAME:026406/0034

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION