CN105990309B - 封装基板及应用其的封装结构 - Google Patents

封装基板及应用其的封装结构 Download PDF

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CN105990309B
CN105990309B CN201610157140.9A CN201610157140A CN105990309B CN 105990309 B CN105990309 B CN 105990309B CN 201610157140 A CN201610157140 A CN 201610157140A CN 105990309 B CN105990309 B CN 105990309B
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metal layer
layer
region
chip
substrate
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CN105990309A (zh
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李皓钧
林育锋
詹勋贤
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Nichia Corp
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Genesis Photonics Inc
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Abstract

本发明提供一种封装基板及应用其的封装结构。其中封装基板，包括一基底层、多个贯孔、一第一金属层以及一第二金属层。基底层具有相对的一第一表面与一第二表面。贯孔穿过基底层。第一金属层设置于第一表面上，且包括一封闭沟槽。第二金属层设置于第二表面上，且通过贯孔与第一金属层电性连接。贯孔位于封闭沟槽的内侧。一种应用其的封装结构亦被提出。本发明藉由在封装基板正面形成沟槽并在封装基板背面形成特定散热结构，能有效防止胶材外流并提升焊接质量。

Description

封装基板及应用其的封装结构
技术领域
本发明涉及一种封装基板及应用其的封装结构，尤其涉及一种具有沟槽的封装基板及应用其的封装结构。
背景技术
在一般封装结构中，可使用胶材固定芯片并防止芯片发出的光线自侧向射出。然而，在封装结构的制造过程中，不易控制胶材，常发生胶材外流。此外，制程中在封装基板上涂上含助焊剂的锡膏时，常会产生气泡，降低焊接质量。
因此，需要提供一种可有效解决上述问题发生的封装基板。
发明内容
本发明提供一种具有沟槽的封装基板及应用其的封装结构，藉由在封装基板正面形成沟槽并在封装基板背面形成特定散热结构，能有效防止胶材外流并提升焊接质量。
根据本发明的一方面，提出一种封装基板，包括一基底层、多个贯孔、一第一金属层以及一第二金属层。基底层具有相对的一第一表面与一第二表面。贯孔穿过基底层。第一金属层设置于第一表面上，且包括一封闭沟槽。第二金属层设置于第二表面上，且通过贯孔与第一金属层电性连接。贯孔位于封闭沟槽的内侧。
根据本发明的另一方面，提出一种封装结构，包括一封装基板、一芯片组与一胶体层。封装基板包括一基底层、多个贯孔、一第一金属层及一第二金属层。基底层具有相对的一第一表面与一第二表面。贯孔穿过基底层。第一金属层设置于第一表面上，且包括一封闭沟槽。第二金属层设置于第二表面上，且通过贯孔与第一金属层电性连接。芯片组与胶体层设置于第一金属层上，且位于封闭沟槽的内侧。
根据本发明的又一方面，提出一种封装结构的制造方法，包括以下步骤。提供一封装基板，其中封装基板包括一基底层、一第一金属层及一第二金属层，基底层具有相对的一第一表面与一第二表面，第一金属层设置于第一表面上且包括一封闭沟槽，第二金属层设置于该第二表面上。提供一芯片组于第一金属层上。提供一胶体层于第一金属层上。芯片组与胶体层位于封闭沟槽的内侧。
为了对本发明的上述及其他方面有更佳的了解，下文特举实施例，并配合附图，作详细说明如下。
附图说明
图1显示本发明一实施例的封装结构的俯视图；
图2A显示本发明一实施例的封装结构沿着图1的A-A’线段所切的剖面图；
图2B显示本发明另一实施例的封装结构沿着图1的A-A’线段所切的剖面图；
图3A显示本发明一实施例的封装结构的仰视图；
图3B显示本发明另一实施例的封装结构的仰视图；
图4A至图4C显示本发明的封装结构的一制造实施例；
图4D至图4E显示本发明的封装结构的另一制造实施例。
附图标记：
100：封装结构
10：封装基板
11：基底层
111：第一表面
112：第二表面
13：第一金属层
14：第二金属层
141：正极区
142：负极区
21：分隔结构
23：封闭沟槽
231：封闭沟槽的内侧壁
232：封闭沟槽的外侧壁
31：贯孔
50、50’：胶体层
80：芯片组
81：芯片
85：静电保护元件
90：散热区
91：沟槽
93、93’：波长转换层
A-A’：剖面线
B-B’：剖面线
W：封闭沟槽的宽度
D：封闭沟槽的深度
S1：封闭沟槽与芯片组的最短距离
S2：正极区与负极区之间的间距
X、Y、Z：坐标轴
具体实施方式
以下参照附图详细叙述本发明的实施方式。需注意的是，实施例所提出的结构和内容仅为举例说明之用，本揭示欲保护的范围并非仅限于所述的实施例。实施例中相同或类似的标号用以标示相同或类似的部分。需注意的是，本发明并非显示出所有可能的实施例。可在不脱离本发明的精神和范围内对结构加以变化与修饰，以符合实际应用所需。因此，未于本发明提出的其他实施例也可能可以应用。再者，附图已简化以利清楚说明实施例的内容，附图的尺寸比例并非按照实际产品等比例绘制。因此，说明书和附图内容仅作叙述实施例之用，而非作为限缩本发明保护范围之用。
图1显示本发明一实施例的封装结构100的俯视图。图2A显示本发明一实施例的封装结构100沿着图1的A-A’线段所切的剖面图。图2B显示本发明另一实施例的封装结构100沿着图1的A-A’线段所切的剖面图。要注意的是，为了更清楚显示位于封装基板10上的元件的关系，图1省略了部分元件。
如图1、图2A所示，本发明实施例的封装结构100包括一封装基板10、一芯片组80以及一胶体层50。在本实施例中，封装基板10可包括一基底层11、多个贯孔(via hole)31、一第一金属层13及一第二金属层14。基底层11具有相对的一第一表面111与一第二表面112。贯孔31穿过基底层11。第一金属层13设置于基底层11的第一表面111上。第二金属层14设置于基底层11的第二表面112上，且通过贯孔31与第一金属层13电性连接。芯片组80与胶体层50设置于第一金属层13上。
如图1所示，第一金属层13藉由一封闭沟槽23来区分内外部分。在本实施例中，贯孔31、芯片组80与胶体层50位于封闭沟槽23的内侧。在此，封闭沟槽23的内侧定义为封闭沟槽23的外侧壁232内的空间。也就是说，胶体层50可填满封闭沟槽23，但不会超过封闭沟槽23的外侧壁232。此外，位于封闭沟槽23内的第一金属层13，可藉由该封闭沟槽23，将第一金属层13内外部分绝缘，即位于封闭沟槽23内部的第一金属层13与封闭沟槽23外的第一金属层13绝缘，避免发生短路。
在一实施例中，基底层11可例如由陶瓷材料所形成，陶瓷材料可例如包括氮化铝、氧化铝。第一金属层13与第二金属层14可例如为铜层。在某些实施例中，封装基板10可进一步包括一镀层(未显示)，例如为金、或银。镀层可形成于第一金属层13与第二金属层14上，以防止第一金属层13与第二金属层14硫化。
如图1、图2A所示，封装基板10可设有多个分隔结构21，分隔结构21设置于基底层11的第一表面111上。举例来说，可藉由蚀刻第一金属层13并裸露部分基底层11的第一表面111，以形成分隔结构21。在本发明实施例中，分隔结构21连接封闭沟槽23。此外，芯片组80设置于分隔结构21上。
在本实施例中，芯片组80包括多个芯片81。多个芯片81之间的间距可例如为50μm。此外，芯片81可为发光二极管(light-emitting diode)芯片，并以覆晶芯片(flip chip)、水平式芯片(lateral chip)、垂直芯片(vertical chip)的形式形成于第一金属层13上。
要注意的是，虽然图1、图2A显示芯片组80包括五个芯片81，且芯片81为正方形，但本揭示并未限定于此。在某些实施例中，芯片组80可仅包括单一芯片，且此单一芯片为矩形。若芯片组中仅包括单一芯片，由于单一芯片中没有间距，搭配其他反射元件、透镜组并发射光线时不会形成暗区。也就是说，芯片组中芯片的数量、形状可视设计需求而改变。
在一实施例中，封闭沟槽23的宽度W可例如为80至300μm，封闭沟槽的深度D可依据第一金属层13的厚度进行调整，举例来说，封闭沟槽的深度D可例如为40至80μm。在此，封闭沟槽23的宽度W可定义为封闭沟槽23的内侧壁231与外侧壁232之间的距离，封闭沟槽23的深度D可定义为封闭沟槽23在垂直基底层11的第一表面111的方向(Z方向)的深度。再者，封闭沟槽23与芯片组80的最短距离S1可例如为500至2000μm。
由于封闭沟槽23的设计以及胶体层50的表面张力，胶体层50可受到控制，在制程中填满封闭沟槽23，但不会超过封闭沟槽23的外侧壁232，因而能有效防止胶体层50外流及溢流至封闭沟槽23所环绕外的区域。此外，由于本发明实施例的分隔结构21连接封闭沟槽23，因此胶体层50也会填满分隔结构21。
在一实施例中，胶体层50可为透明硅胶，或者胶体层50可包括硅胶与荧光粉。如图2A所示，胶体层50可覆盖芯片组80。然而，本发明并未限定于此。
如第2B图所示，在本发明另一实施例中，胶体层50’并未覆盖芯片组80。也就是说，胶体层50’可位于芯片组80的侧表面，并裸露出芯片组80的顶表面。在此实施例中，可形成一波长转换层93于芯片组80的顶表面。举例来说，可以喷涂或表面贴合荧光胶片的方式形成波长转换层93于芯片组80的顶表面。利用喷涂的方式可形成较薄的波长转换层93，并均匀形成于芯片组80的顶表面，因而也可薄化胶体层50’。
此外，位于芯片组80的侧表面的胶体层50’可例如包括硅胶与二氧化钛(TiO2)，胶体层50’的黏度可例如为1000～20000mPa·s，反射率可为90％～99％，例如95％。
在一实施例中，封装结构100可包括一静电保护元件85。保护元件85设置于基底层11的第一表面111上，可用以保护芯片组80，免于受到损害。
图3A显示本发明一实施例的封装结构100的仰视图。图3B显示本发明另一实施例的封装结构100的仰视图。也就是说，图1可表示本发明实施例的封装结构100的正面结构，图3A、图3B可表示本发明实施例的封装结构100的背面结构。
在本实施例中，封装基板10的第二金属层14可包括一散热区90、一正极区141与一负极区142，散热区90、正极区141与负极区142设置于基底层10的第二表面122。散热区90对应于芯片组80的位置，且正极区141与负极区142与散热区90分隔。散热区90可用以传导芯片组80所发出的热量至芯片组80外来散热，且散热区90并未电性连接至任何元件。
散热区90由多个沟槽91所形成，这些沟槽91排列为多边形或弧形数组，且沟槽91可与散热区90的外部连通。举例来说，沟槽91可形成由三边形、四边形、五边形、六边形(如图3A所示)等多边形所组成的数组图案，或者，前述多边形组成的数组图案可由具有弧形所组成的数组图案取代。
如图3A所示，由于多个沟槽91的设计，散热区90可被分割为类似蜂巢图案，有助于芯片组80的散热。在后续制程中，封装结构100可涂上含助焊剂的锡膏并连接至一电路板，在加热并连接电路板得过程中，含助焊剂的锡膏可能会产生气体，而形成焊接部位的气泡，导致焊接质量降低。藉由对外连接的多个沟槽91的设计，能将产生的气泡排出，有效提升焊接质量。
封装基板10的正极区141与负极区142为第二金属层14的两个部分。因此，封装基板10的正极区141与负极区142可通过贯孔31与第一金属层13电性连接。
再者，封装基板10的正极区141与负极区142之间的间距、正极区141与散热区90之间的间距、负极区142与散热区90之间的间距至少为400μm。举例来说，如图3A所示，封装基板10的正极区141与负极区142之间的间距S2可例如为400μm。
本发明并未限定于图3A所示的结构。图3B可表示本发明另一实施例的封装结构100的背面结构。图3B所示的结构相较于图3A所示的结构具有更大面积的散热区90。须注意的是，虽然图3A、图3B皆显示沟槽91排列为六边形数组，但本发明并未限定于此。沟槽91的形状与数量可视设计需求而改变。
图4A至图4C显示本发明的封装结构100的一制造实施例，其中图4C可例如为本发明的封装结构100沿着图1的B-B’线所切的剖面图。要注意的是，为了更清楚显示封装结构100的制造步骤，以下附图可能省略部分元件。
如图4A所示，提供一封装基板10。类似地，封装基板10可例如具有图2B所显示的结构，包括一基底层11、一第一金属层13及一第二金属层14，基底层11具有相对的一第一表面111与一第二表面112，第一金属层13设置于第一表面111上且包括一封闭沟槽23，第二金属层14设置于第二表面112上。接着，提供一芯片组80于封装基板10(第一金属层13)上。
如图4B所示，形成一波长转换层93于芯片组80的表面。在本实施例中，波长转换层93可覆盖芯片组80。波长转换层93可以喷涂的方式形成于芯片组80的表面。
最后，形成一胶体层50于封装基板10(第一金属层13)上。如图4C所示，芯片组80与胶体层50皆位于封闭沟槽23的内侧，且胶体层50仅位于波长转换层93与芯片组80的侧表面，并裸露出部分波长转换层93的顶表面。
然而，本发明并未限定于此。图4D至图4E显示本揭示的封装结构100的另一制造实施例，其中图4E可例如为本揭示的封装结构100沿着图1的B-B’线所切的剖面图。类似地，为了更清楚显示封装结构100的制造步骤，以下附图可能省略部分元件。
图4D的步骤可接续图4A的步骤。如图4D所示，形成一波长转换层93’于芯片组80裸露的顶表面。举例来说，波长转换层93’可以贴合的方式形成于芯片组80的顶表面。
最后，如图4E所示，提供一胶体层50于芯片组80与波长转换层93’的侧表面，胶体层50位于封闭沟槽23的内侧，并裸露出波长转换层93’的顶表面。
承上述实施例，本发明藉由在封装基板10的正面形成封闭沟槽23，在封装基板10的背面形成散热区90，能有效防止胶材外流并提升焊接质量。
综上所述，虽然本发明已以实施例揭示如上，然其并非用以限定本发明。本发明所属技术领域中普通技术人员，在不脱离本发明的精神和范围内，当可作各种的改动与润饰。因此，本发明的保护范围当视所附权利要求界定范围为准。

Claims (18)

1.一种封装基板，其特征在于，包括：
一基底层，具有相对的一第一表面与一第二表面；
多个贯孔，穿过所述基底层；
一第一金属层，设置于所述第一表面上，且包括一环绕部和多个分离排列的上垫部，其中所述环绕部包围所述上垫部而在所述环绕部与所述上垫部之间形成一封闭沟槽，且所述上垫部之间的间隙与所述封闭沟槽相连通；以及
一第二金属层，设置于所述第二表面上，且包括分离排列的下垫部，其中所述下垫部分别通过所述多个贯孔与所述上垫部电性连接；
其中所述多个贯孔位于所述上垫部的下方，且所述第一金属层的所述环绕部是电性浮置。
2.根据权利要求1所述的封装基板，其特征在于，该第二金属层还包括：
一散热区，包括被多个沟槽所分隔的多个散热垫。
3.根据权利要求1所述的封装基板，其特征在于，该封闭沟槽的宽度为80至300μm。
4.根据权利要求1所述的封装基板，其特征在于，该封闭沟槽的深度为40至80μm。
5.根据权利要求1所述的封装基板，其特征在于，该基底层由陶瓷材料所形成。
6.根据权利要求1所述的封装基板，其特征在于，还包括一镀层，形成于所述第一金属层与所述第二金属层上，其中所述镀层为金或银所形成。
7.根据权利要求2所述的封装基板，其特征在于，所述散热垫是电性浮置。
8.根据权利要求2所述的封装基板，其特征在于，所述第二金属层的所述下垫部被分成一正极区与一负极区，与所述散热区分隔且包围所述散热区。
9.一种封装结构，其特征在于，包括：
一封装基板，包括：
一基底层，具有相对的一第一表面与一第二表面；
多个贯孔，穿过所述基底层；
一第一金属层，设置于所述第一表面上，且包括一环绕部和多个分离排列的上垫部，其中所述环绕部包围所述上垫部而在所述环绕部与所述上垫部之间形成一封闭沟槽，且所述上垫部之间的间隙与所述封闭沟槽相连通；及
一第二金属层，设置于所述第二表面上，且包括分离排列的下垫部，其中所述下垫部分别通过所述多个贯孔与所述上垫部电性连接，且所述第一金属层的所述环绕部是电性浮置；以及
至少一芯片，设置于所述上垫部且与其电性连接；以及
一胶体层，设置于所述封装基板上，并覆盖所述芯片及所述上垫部、或者覆盖所述芯片的外侧表面及覆盖所述上垫部的位于所述芯片外侧的部分且裸露出所述芯片的顶表面，其中所述胶体层未延伸超过所述封闭沟槽的一外侧壁。
10.根据权利要求9所述的封装结构，其特征在于，所述第二金属层还包括：
一散热区，对应所述芯片的位置设置，包括被多个沟槽所分隔的多个散热垫。
11.根据权利要求10所述的封装结构，其特征在于，所述第二金属层的所述下垫部被分成：
一正极区与一负极区，与所述散热区分隔且包围所述散热区。
12.根据权利要求9所述的封装结构，其特征在于，所述芯片包括一覆晶芯片。
13.根据权利要求9所述的封装结构，其特征在于，当所述芯片的数量为多个时，所述芯片之间的间距为50μm。
14.根据权利要求9所述的封装结构，其特征在于，所述封闭沟槽与所述芯片间的距离为500至2000μm。
15.根据权利要求9所述的封装结构，其特征在于，所述胶体层包括硅胶与荧光粉。
16.根据权利要求9所述的封装结构，其特征在于，所述封装基板还包括：
一镀层，形成于所述第一金属层与所述第二金属层上；
其中所述镀层为金或银所形成。
17.根据权利要求10所述的封装结构，其特征在于，所述散热垫是电性浮置。
18.一种封装结构，其特征在于，包括：
一封装基板，包括：
一基底层，具有相对的一第一表面与一第二表面；
多个贯孔，穿过所述基底层；
一第一金属层，设置于所述第一表面上，且包括一封闭沟槽；及
一第二金属层，设置于所述第二表面上，其中所述第二金属层通过所述多个贯孔与所述第一金属层电性连接；以及
一芯片组及一胶体层，设置于所述第一金属层上且位于所述封闭沟槽的内部，
其中所述第二金属层还包括对应所述芯片组的一散热区，且所述散热区是由多个沟槽排列在一垫部阵列中，
其中所述第二金属层还包括与该散热区分隔的一正极区与一负极区，其中该正极区与该负极区之间的间距、该正极区与该散热区之间的间距、该负极区与该散热区之间的间距至少为400μm。
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