CN105590900B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN105590900B
CN105590900B CN201510831260.8A CN201510831260A CN105590900B CN 105590900 B CN105590900 B CN 105590900B CN 201510831260 A CN201510831260 A CN 201510831260A CN 105590900 B CN105590900 B CN 105590900B
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substrate
internal connection
wire structure
base material
layer
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CN105590900A (zh
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沈文维
施应庆
陈承先
陈明发
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明包括一种半导体装置及其制造方法，该半导体装置包括：一第一基材，具有一第一内连线结构；以及一第二基材，具有一第二内连线结构，该第一内连线结构连接该第二内连线结构，该第一内连线结构的第一宽度与该第二内连线结构的第二宽度不同。本发明提供一种用于使一基材与另一基材接合的凸块结构。一导电柱体形成于第一基材上，以使此导电柱体具有与一第二基材的接触表面不同的宽度。在一实施例中，第一基材的导电柱体为梯形或具有锥形侧壁，因而提供底部部分较顶部部分宽的导电柱体。所述基材均可为集成电路芯片、转接板、印刷电路板、高密度内连线或其类似物。本发明可减低关于交界处应力所产生的脱层问题。

Description

半导体装置及其制造方法
本申请是申请号为201010546183.9、申请日为2010年11月10日、发明名称为“半导体装置及其制造方法”的发明专利申请的分案申请。
技术领域
本发明涉及集成电路、半导体装置及其制造方法，尤其涉及用于半导体芯片的凸块结构。
背景技术
自集成电路发明以来，由于各种电子元件(例如晶体管、二极管、电阻、电容等)的集积度持续改良，半导体产业已经历快速的成长。主要来说，这些集积度的改良来自重复地缩减元件最小尺寸，而使更多元件能整合至单位面积中。
这些集积度的改良本质上仍在二维(2D)中，集成电路所占据的体积基本上仅在半导体晶片的表面上。虽然光刻技术的大幅改良使二维集成电路的制造仍为可行，但在二维中所能达到的密度仍有其物理限制。限制之一即为制造这些元件所需的最小尺寸。此外，当置入更多元件至同一芯片中，需要更复杂的设计。
为了增加集成密度，已发展出三维集成电路。在三维集成电路的一般工艺中，两个芯片互相接合，且在每一芯片与基材上的接触垫之间形成电性连接。例如，其中一种方法包含将两芯片的顶部相互接合。接着，将此堆叠芯片与承载基材接合，并以导线电性连接每一芯片上的接触垫至承载基材上的接触垫。然而，此方法需要较芯片大的承载基材以作导线连接。
近来有更多方法聚焦在倒装芯片内连线及导电球/凸块的使用，以在芯片及其下的基材之间形成连接，因而在相对较小的封装体中具有较高的导线密度。此情况下，于一表面上形成导电凸块，并与其他表面上的立柱或垫直接接触。然而，在相对表面的接触点之间经常产生错位(misalignment)。错位可造成接触点之间的短路及/或装置的损坏。
此外，材料的不同及其所对应的热膨胀系数不同产生应力于其交界处，应力会使交界处(joint)破裂及/或造成其他问题，例如介电层的脱层问题。
发明内容
为了解决现有技术的问题，本发明提供一种半导体装置，包括：一第一基材，具有一第一内连线结构；以及一第二基材，具有一第二内连线结构，该第一内连线结构连接该第二内连线结构，该第一内连线结构的第一宽度与该第二内连线结构的第二宽度不同。
本发明也提供一种半导体装置，包括：一第一基材，具有一第一导电柱体，该第一导电柱体具有一第一宽度W1；一第二基材，具有一接触表面，该接触表面具有一第二宽度W2，其中该第一宽度W1小于该第二宽度W2；以及一导电材料，连接该第一导电柱体及该接触表面。
本发明还提供一种半导体装置的制造方法，包括：提供具有一第一内连线结构形成于其上的一第一基材，该第一内连线结构具有一第一宽度；提供具有一第二内连线结构形成于其上的一第二基材，该第二基材具有与该第一宽度不同的一第二宽度；以及连接该第一基材的该第一内连线结构及该第二基材的该第二内连线结构。
本发明可减低关于交界处应力所产生的脱层问题。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出优选实施例，并配合所附附图，作详细说明如下：
附图说明
图1～图7显示依照本发明一实施例制造具有凸块结构的半导体装置的各种中间阶段。
图8～图9显示依照本发明一实施例接合两基材。
图10～图11显示依照本发明另一实施例接合两基材。
图12显示依照本发明一实施例的贯穿过渡堆叠排列。
图13显示依照本发明一实施例的贯穿中介堆叠排列。
其中，附图标记说明如下：
100～基材102～导电垫
104～第一保护层106～接合垫
108～第二保护层210～籽晶层
312～第一图案化掩模掩模314～开口
416～导电柱体518～导电盖层
620～焊料622～介金属化合物层
724～导电凸块800～第一基材
801～第一内连线结构850～第二基材
851～第二内连线结构854～第一保护层
856～导电垫858～籽晶层
860～第二保护层862～籽晶层
864～导电柱体866～导电盖层
868～阻焊层1000～第一基材
1001～第一内连线结构1002～被覆层
1050～第二基材1051～第二内连线结构
1202～第一集成电路芯片1204～第二集成电路芯片
1206～基材1208～贯通孔
1210～超低介电常数介电膜
1212～第一内连线结构1214～第二内连线结构
1310～转接板1312～贯通孔
1314～超低介电常数介电膜
1316～超低介电常数介电膜
1318～内连线结构1320～内连线结构
具体实施方式
本发明接下来将会提供许多不同的实施例以实施本发明中不同的特征。值得注意的是，这些实施例提供许多可行的发明概念并可实施于各种特定情况。然而，在此所讨论的这些特定实施例仅用于举例说明本发明的制造及使用方法，但非用于限定本发明的范围。
在此所述的实施例关于凸块或球的使用(在此通称为凸块)，用以使一基材与另一基材相互连接，其中每一基材均可为集成电路芯片、转接板(interposer)、封装基材、印刷电路板、高密度内连线(high-density interconnect)等。以下将详细讨论使用梯形凸块的实施例，并可发现到在此所讨论的实施例可减少错位，因而增加产能及可靠度。在此也揭示凸块制造的各种中间阶段。上述实施例均可适于用于三维集成电路或电堆叠芯片结构。本发明所举例的实施例及各种图示中，相似元件以相似附图标记表示。
图1至图7显示依照本发明实施例制造具有梯形凸块的半导体装置的各种中间阶段。参见图1，显示依照本发明一实施例的一部分的基材100。基材100可包含，例如块材硅、掺杂或未掺杂的基材、或绝缘体上覆半导体(semiconductor-on-insulator，SOI)基材的有源层。通常，绝缘体上覆半导体(SOI)基材包含于绝缘层上形成半导体材料层，例如硅。绝缘层可例如为深埋氧化(buried oxide，BOX)层或氧化硅层。此绝缘层位于基材上，通常为硅或玻璃基材。或者，也可使用其他基材，例如多层或梯度基材。在另一实施例中，基材100可包含一基材连接至一集成电路芯片。例如，基材100可包含转接板、封装基材、高密度内连线、印刷电路板、另一集成电路芯片或其类似物。
值得注意的是，在某些实施例中，特别是基材100为集成电路芯片的实施例，基材100可包含电路装置(electrical circuitry)(未显示)。在一实施例中，电路装置可包含形成于基材上100的电子装置及此电子装置上方的一或多层介电层。可在这些介电层之间形成金属层，以在电子装置之间传递电子信号。电子装置也可形成于一或多层介电层中。在一实施例中，基材100包含一或多个低介电常数(low-k)及/或超低介电常数(extremely low-k)介电层。
例如，电路装置可包含各种N型金属氧化物半导体(NMOS)及/或P型金属氧化物半导体(PMOS)装置，例如晶体管、电容、电阻、光二极管、熔丝及其类似物，彼此相互连接以进行一或多种功能。这些功能可包含作为存储器结构、处理器结构、传感器、扩大器、配电线路(power distribution circuitry)、输入/输出线路等。本领域普通技术人员应可知上述实施例仅用于举例以详加解释某些实施例的应用，但非以各种形式限制本发明。在特定用途中可使用其他电路装置。
导电垫102设于基材100的上表面上，以提供对外的电性连接。值得注意的是，导电垫102代表与形成在基材100上的电路装置的电性连接、与贯通孔的电性连接、重分布导线及/或其类似物。导电垫102可包含导电材料，例如铜，或其他导电材料，例如钨、铝、铜合金等。导电垫102可由镶嵌或双镶嵌工艺形成，此工艺可包含以铜填满超过开口，并以例如化学机械研磨(CMP)等工艺移除过多的铜。或者，也可使用其他任何合适材料(例如铝)及任何合适工艺(例如沉积及蚀刻)来形成导电垫102。
第一保护层104可形成(例如聚亚酰胺、聚合物、氧化物、氮化物等介电材料)于基材100表面上并作图案化，以于导电垫102上方提供开口且保护底下膜层不受各种环境污染物污染。在一实施例中，第一保护层104包含氮化硅层及氧化层的复合层。氮化硅层可由使用硅烷及氨气作为前驱物气体的化学气相沉积技术(CVD)形成，其厚度约为氧化层可由任何氧化工艺形成，例如在含氧气、水、一氧化氮或前述组合的环境下所进行的湿或干热氧化工艺，或由使用四乙氧基硅烷(TEOS)及氧气作为前驱物的化学气相沉积技术形成。在一实施例中，氧化层的厚度为约也可使用其他材料、工艺及厚度。
在第一保护层104包含氮化硅层及氧化层的实施例中，可以使用磷酸的湿式蚀刻工艺蚀刻氮化硅层及以使用稀氢氟酸的湿式蚀刻工艺蚀刻二氧化硅层，形成一开口而暴露导电垫102。
随后，形成接合垫106于第一保护层104上并作图案化。接合垫106可用以提供与随后工艺中所形成的凸块下金属(UBM)结构电性连接，以连接至外部。接合垫106可由任何导电材料，例如铜、钨、铝、银、前述的组合或其类似物形成。
一或多层保护层(例如第二保护层108)可形成于如图1所示的接合垫106上，并作图案化。第二保护层108可由介电材料形成，例如聚合物、氮化物、氧化物等，且可由任何合适方法形成，例如化学气相沉积、物理气相沉积等。在一实施例中，第二保护层108为包含厚度约的等离子体增强式氮氧化硅(plasma-enhanced silicon oxynitride，PESION)层、厚度约的未掺杂硅玻璃(undoped silicate glass，USG)层及厚度约的等离子体增强式氮化硅(plasma-enhanced silicon nitride，PESIN)层的复合层。
本发明普通技术人员应可知，在此所示的单一层的导电/接合垫及保护层仅用于举例。因此，其他实施例中也可包含任意层数的导电层及/或保护层。此外，可知的是，一或多层的导电层可作为重分布层(redistribution layer，RDL)以提供所欲的节距(pitch)或球状布局(ball layout)。
前述结构可使用任何合适的工艺形成，将不再详加赘述。本领域普通技术人员可知的是，上述仅提供对实施例中的各元件的概略描述，但也可存在有各种其他元件。例如，可存在有其他电路、衬层、阻障层、凸块下金属结构及其类似物。上述仅代表提供在此所讨论的实施例的内容，但不用以限制本发明或任何专利保护范围至上述特定实施例中。
现请参见图2，沉积顺应性的籽晶层(conformal seed layer)210于第二保护层108的表面上及接合垫106的暴露部分。籽晶层210为导电材料形成的薄层，以帮助在随后工艺中能形成较厚的膜层。在一实施例中，籽晶层210可由例如化学气相沉积或物理气相沉积技术沉积例如铜、钛、钽、氮化钛、氮化钽等薄层而形成。例如，在一实施例中，籽晶层210包含由物理气相沉积工艺所沉积的钛层(厚度为约)及由物理气相沉积工艺所沉积的铜层(厚度为约)。或者，也可使用其他材料、工艺及厚度。
图3显示依照本发明一实施例形成第一图案化掩模312于籽晶层210上。第一图案化掩模312将作为在随后工艺中用以形成导电柱体(conductive pillars)的模具。第一图案化掩模312可为图案化的光掩模、硬掩模或其类似物。在一实施例中，沉积光致抗蚀剂材料并将其图案化，以形成开口314。
值得注意的是，图3所示的实施例使用具有斜度，以使开口314的底部(沿着籽晶层210)较开口314的顶部部分宽，因而形成梯形。此梯形轮廓可由任何合适技术形成，例如使用多个具有不同图案化性质的光致抗蚀剂层并进行一或多次曝光、扩散技术、图像反转工艺(image reversal process)、使用不同掩模的多重曝光或其类似技术。
随后，如图4所示，形成导电柱体416于开口314(参见图3)中。导电柱体416包含一或多种导电材料，例如铜、钨、其他导电材料等，并可由例如电镀、无电电镀等技术形成。在一实施例中，使用电镀工艺。将晶片浸入或沉浸(submerged or immersed)于电镀溶液中。晶片表面电性连接至负极的外部直流电(DC)电源供应源，以使晶片在电镀工艺中作为阴极(cathode)。固态的导电阳极(anode)，例如铜，也沉浸于此溶液中并连接至电源供应源的正极。自阳极释出的原子溶解至溶液中，阳极(例如晶片)自溶液中得到这些原子，因而电镀至晶片所暴露的导电区域，例如开口314中籽晶层210的暴露部分。
图5显示视需要形成导电盖层518于导电柱体416上。如以下的详细讨论，焊料将形成于导电柱体416上。在回焊工艺(soldering process)期间，自然地形成介金属化合物(inter-metallic compound，IMC)于焊料与其底下表面的交界处。可发现到某些材料，相较于其他材料，可形成更坚固且更耐用的介金属化合物层。如此，较佳需形成盖层，例如导电盖层518，以提供性质更佳的介金属化合物层。在一实施例中，导电柱体416由铜形成，导电盖层518较佳为由镍形成，或也可由其他材料，例如铂、金、银前述的组合形成。导电盖层518可由任何合适工艺形成，例如物理气相沉积、化学气相沉积、电化学沉积(electricalchemical deposition，ECD)、分子束外延(molecular beam epitaxy，MBE)、原子层沉积等。
图6显示形成焊料620及介金属化合物层622。在一实施例中，焊料622包含锡铅合金(SnPb)、高铅材料、锡基焊料(Sn-based solder)、无铅焊料或其他合适导电材料。
图7显示依照本发明一实施例移除第一图案化掩模312(参见图3)。在一实施例中，第一图案化掩模312为光掩模，可使用等离子体灰化(plasma ashing)或湿剥除(wetstrip)工艺予以移除。例如，其中一种合适的等离子体灰化工艺条件包括：约300mTorr至600mTorr的压力，流速约1000sccm至2000sccm的氧气、约500瓦至2000瓦的功率及约80℃至200℃的温度。可视需要湿浸晶片至硫酸溶液中以清洁晶片并移除光致抗蚀剂材料。可进行回焊工艺，其可使焊料620具有圆球状(rounded shape)。
导电柱体416及视需要形成的导电盖层518形成梯形的导电凸块724，以使导电凸块724具有锥形(tapered)侧壁。在此情况下，较宽的底部尺寸可降低电流密度，且较窄的顶部可减少第一基材100连接至另一基材的错位发生机率。
图8-图9显示依照本发明一实施例接合两基材。第一基材800具有一内连线结构801，代表如图1至图7所讨论的基材100，其中相似元件以相似附图标记表示。第二基材850代表将与第一基材800接合的基材，且其可为集成电路芯片、转接板、封装基材、高密度内连线、印刷电路板等。
举例而言，第二基材850显示一用以接合第一基材800的第二内连线结构851的例子。值得注意的是，其他形态的内连线结构也可用以连接第一基材800及第二基材850。在本实施例中，第二基材850包含由一或多层介电层所形成的第一保护层854，例如聚亚酰胺、聚合物、氧化物、氮化物等。在一实施例中，第一保护层854包含一复合层，例如厚度约的氮化硅层及其上厚度约的氧化层。氮化硅层可由使用以硅烷及氨气作为前驱物气体的化学气相沉积技术形成。氧化层可由任何氧化工艺形成，例如在含氧气、水、一氧化氮或前述的组合的环境下所进行的湿或干热氧化工艺，或由使用四乙氧基硅烷(TEOS)及氧气作为前驱物的化学气相沉积技术形成。
导电垫856形成于第一保护层854上。导电垫856可由任何合适导电材料形成，例如铜、钨、铝、银、前述的组合等。值得注意的是，导电垫856可为一部分的重分布层或贯穿孔(through-substrate via)。在一实施例中，可使用前述形成导电柱体416的类似技术形成导电垫856。例如，可于第一保护层854上形成顺应性的籽晶层(conformal seed layer)858，其包含厚度约的钛层及厚度约的铜层。可形成掩模层并作图案化，以定义导电垫856的形状，随后，可使用电镀工艺形成厚度约3μm的铜层以形成导电垫856。掩模层及多余的籽晶层可被移除。
导电垫856可由其他方法及材料形成。例如，可包含以化学电镀法(ECP)、无电电镀或其他常用的沉积方法，例如溅镀、印刷及化学气相沉积。此外，导电材料可包含铜合金、铝、银、金、前述的组合或其类似物。
如图8所示，形成一或多层第二保护层(例如第二保护层860)于导电垫856上并作图案化。第二保护层860可由例如聚合物、氧化物、氮化物等介电材料形成，并可由化学气相沉积、物理气相沉积等任何合适技术形成。在一实施例中，第二保护层860包含由化学气相沉积技术所形成的厚度约的氮化硅层。
随后，形成籽晶层862、导电柱体864、导电盖层866及阻焊层868于导电垫856上。籽晶层862、导电柱体864、导电盖层866、阻焊层868各自可使用与如前述形成籽晶层210、导电柱体416、导电盖层518、阻焊层620的类似技术形成，然而，相较于梯形的导电凸块416及导电盖层518，位在第二基材850上的导电柱体864及导电盖层866为矩形。值得注意的是，阻焊层868为相对较薄的阻焊层，以使第一基材800及第二基材850之间的导电性更佳，且减少或预防错位。介金属化合物层870可形成于焊料层868及盖层866之间。
图9显示接合后的第一基材800及第二基材850。如图8所示，第一基材800的第一内连线结构801的接触表面的第一宽度W1小于第二基材850的第二内连线结构851的接触表面的第二宽度W2。在一实施例中，第一宽度W1与第二宽度W2的比例(W1/W2)大于或等于0.1，且小于1.0。
图10及图11显示本发明两基材接合的另一实施例。具有第一内连线结构1001的第一基材1000，代表如前述图1-图7所讨论的基材100，其中相似元件以相似附图标记表示。第二基材1050代表欲通过第二内连线结构1051与第一基材1000连接的基材，其可为集成电路芯片、转接板、封装基材、高密度内连线、印刷电路板或其类似物。
图10及图11所显示的第二基材1050可由与图8所示的第二基材850使用类似方法及类似材料形成，其中除了第二基材1050省略了导电盖层866及阻焊层868，相似附图标记代表相似元件。此外，图10及图11所示的实施例使用被覆层(finish layer)1002。在一实施例中，被覆层1002包含镍层，其直接位于该导电柱体864上并与其接触。此外，可视需要形成额外的膜层，以使被覆层1002可为化学镍金(electroless nickel immersion gold，ENIG)、化学镍钯金(nickel electroless palladium immersion gold，ENEPIG)或镍钯层。被覆层1002的形成方法可包含化学电镀法(ECP)、无电电镀等类似技术。图11显示接合后的第一基材1000及第二基材1050。
图12及图13各自显示依照本发明实施例的贯穿过渡堆叠(through transitionstacking，TTS)排列及贯穿中介堆叠(through interposer stacking，TIS)排列。通常，如图12所示的贯穿过渡堆叠(TTS)排列包含一第一集成电路芯片1202及一第二集成电路芯片1204，以使第二集成电路芯片1204一面与第一集成电路芯片1202接合，另一面与基材1206接合。第二集成电路芯片1204中的贯通孔1208提供第一集成电路芯片1202与第二集成电路芯片1204底部上的接触点之间的电性连接。第一集成电路芯片1202及第二集成电路芯片1204可为任何合适的集成电路芯片。在一实施例中，第一集成电路芯片1202为存储器芯片，且第二集成电路芯片1204为逻辑芯片、其他种类的芯片或前述的组合。
在图12所述的实施例中，第二集成电路芯片1204与基材1206接合，基材1206可为印刷电路板、转接板、层压基材(laminate substrate)、封装基材等。在另一实施例中，基材1206可为第三集成电路芯片，因而形成三个芯片的堆叠芯片结构。
图12也显示以较大的接触表面作接合的内连线结构位于底部芯片上。例如，第一集成电路芯片1202可具有一第一内连线结构1212，其具有第一宽度W1(参见例如图8-图11)；第二集成电路芯片1204具有第二内连线结构1214，其具有较大的宽度W2(参见例如图8-图11)。
图12还显示了一基材，例如第二集成电路芯片1204，包含超低介电常数(extremely low-k，ELK)介电膜1210的实施例，其中超低介电常数介电膜的介电常数小于或等于2.5。在使用超低介电常数介电膜的实施例中，最好将具有较大宽度的内连线结构设置于具有超低介电常数介电膜的基材上。可相信的是，将具有较大宽度的内连线结构设置于具有超低介电常数介电膜的基材上可降低应力，其因此可减低关于交界处应力所产生的脱层问题。因此，如图12所示的实施例中，第二集成电路芯片1204可具有宽度较大的内连线结构。参见图10及图11，第二集成电路芯片1204可具有宽度为W2的内连线结构，且与第二集成电路芯片1204接合的基材1206具有宽度为W1的内连线结构，其中W2大于W1。
图13显示近似于图12所示实施例的实施例，其中除了使用转接板1310，相似元件以相似附图标记表示。在此实施例中，第一集成电路芯片1202及第二集成电路芯片1204连接至转接板1310，转接板另一面则与基材1206连接。转接板1310中的贯通孔1312提供第一集成电路芯片1202、第二集成电路芯片1204及/或基材1206之间的电性连接。
值得注意的是，任何在第一集成电路芯片1202、第二集成电路芯片1204、基材1206及/或转接板1310之间的连线可使用如前述的锥形导电元件。
图13也显示各自包含超低介电常数介电膜1314、1316的第一集成电路芯片1202及第二集成电路芯片1204。如前述，在某些实施例中，当使用超低介电常数介电膜时，将具有较大宽度的内连线结构设置于具有超低介电常数介电膜的基材上可降低超低介电常数介电膜因接合应力所造成的脱层问题。因此，第一集成电路芯片1202及第二集成电路芯片1204可具有宽度为W2的内连线结构1318(参见例如图8-图11)，且与第一集成电路芯片1202及第二集成电路芯片1204连接的转接板1310具有宽度为W1的内连线结构1320(参见例如图8-图11)，其中W2大于W1。
虽然本发明已以数个优选实施例揭示如上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视所附的权利要求所界定的范围为准。此外，本领域普通技术人员将可依照本发明所揭示的现有或未来所发展的特定程序、机器、制造、物质的组合、功能、方法或步骤达成相同的功能或相同的结果。因此本发明的保护范围包含这些程序、机器、制造、物质的组合、功能、方法或步骤。

Claims (7)

1.一种半导体装置，包括：
一第一基材，具有从该第一基材的一第一表面延伸的一第一内连线结构，该第一内连线结构包括一第一导电柱体及一第一导电盖层，该第一导电柱体具有随着从该第一基材的第一表面延伸而逐渐变窄的一第一侧壁，该第一导电柱体具有远离该第一基材并与该第一侧壁连接的一第一远端柱体表面，该第一导电盖层仅位于该第一导电柱体的第一远端柱体表面上，该第一导电盖层具有随着从该第一导电柱体延伸而逐渐变窄的一第二侧壁；
一第二基材，具有从该第二基材的一第二表面延伸的一第二内连线结构；以及
一焊料，将该第一内连线结构附着到该第二内连线结构，其中该焊料不延伸到该第一侧壁上。
2.如权利要求1所述的半导体装置，其中该焊料为圆球状。
3.如权利要求1所述的半导体装置，其中该第一基材及该第二基材至少其一为一集成电路芯片，且另一基材为一转接板、封装基材、高密度内连线或印刷电路板。
4.如权利要求1所述的半导体装置，其中该第一内连线结构及该第二内连线结构至少其一为梯形。
5.一种半导体装置的制造方法，包括：
提供一第一基材，该第一基材具有从该第一基材的一第一表面延伸的一第一内连线结构，该第一内连线结构包括一第一导电柱体及一第一导电盖层，该第一导电柱体具有随着从该第一基材的第一表面延伸而逐渐变窄的一第一侧壁，该第一导电柱体具有远离该第一基材并与该第一侧壁连接的一第一远端柱体表面，该第一导电盖层仅位于该第一导电柱体的第一远端柱体表面上，该第一导电盖层具有随着从该第一导电柱体延伸而逐渐变窄的一第二侧壁；
提供一第二基材，该第二基材具有从该第二基材的一第二表面延伸的一第二内连线结构；以及
提供一焊料，该焊料将该第一内连线结构附着到该第二内连线结构，其中该焊料不延伸到该第一侧壁上。
6.如权利要求5所述的半导体装置的制造方法，其中该焊料为圆球状。
7.如权利要求5所述的半导体装置的制造方法，其中该第一内连线结构及该第二内连线结构至少其一为梯形。
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US9142533B2 (en) 2015-09-22
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US9773755B2 (en) 2017-09-26
CN105590900A (zh) 2016-05-18

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