CN105453424A - 具有提供高品质因数的多个互耦金属化层的矢量电感器 - Google Patents

具有提供高品质因数的多个互耦金属化层的矢量电感器 Download PDF

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CN105453424A
CN105453424A CN201480037474.1A CN201480037474A CN105453424A CN 105453424 A CN105453424 A CN 105453424A CN 201480037474 A CN201480037474 A CN 201480037474A CN 105453424 A CN105453424 A CN 105453424A
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inductor
conductor
conducting
capacitor
dielectric
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D.V.格普塔
M.S.穆萨
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TDK Corp
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Newlans Inc
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Abstract

一种电感器组件，包括：多个导电元件，均形成为导电材料的单独片块，其中，所述导电元件被布置在垂直堆叠中并且彼此紧密耦合。介电质被部署在多个相邻导电元件之间，所述介电质具有电容率并且足够薄，从而提供所述导电元件中的各相邻导电元件之间的至少二分之一或更大的互感系数。所述介电质典型地比相邻导体更薄。

Description

具有提供高品质因数的多个互耦金属化层的矢量电感器
技术领域
该专利申请涉及电感器，更具体地说，涉及以小形状因子来提供非常高的品质因数的矢量电感器。
背景技术
电感器是无源的二端电组件，其当电流通过它时临时存储电能量。当流过电感器的电流随着时间而改变时，所得时变磁场感生电压。电感器可以由其电感——该电压对于电流的改变速率的比率来表征。
电感器一般用在很多不同类型的交流(AC)电路中，并且尤其是射频(RF)电路中。电感器与电容器和其它组件组合以实现滤波器、谐振器、调谐器以及其它功能。在同时尽可能小并且廉价的同时，电子设备(例如智能电话、平板、膝上型计算机等)现在典型地期待使用很多不同的无线电通信协议并且在宽的各种频率上操作。电感器设计变为实现这些目标的关键方面。
发明内容
问题描述
品质或Q因数是关于组件的电感与电阻之间的比率表征电感器的无量纲参数。在RF设计中，Q一般被看作表征谐振电路相对于其中心频率的带宽。更高的Q指示更低的相对于所存储的能量的能量损耗率。因此期望实现具有更高Q因数的谐振器，其中，相对于中心频率的带宽必须增加。对于高Q的需求因此是必须处理越来越高的数据率的现今通信设备的特性。高Q调谐电路还提供更大的选择性；也就是说，其在滤除来自相邻信道的信号方面做得更好。高Q振荡器也在更小的频率范围内谐振，并且因此更稳定。
关于组件设计的附加考虑是其占据的物理空间。可以在还改进Q的同时增加特定量的电路面积中可用的给定的电感量的任何方法将通常是优选的。
如果对于特定的基于集成电路(IC)的设计需要电感器集合，则使用与IC分离的分立式电感器可能归因于需要在电感器集合与其它组件之间进行很多互连而导致实现方式问题。这种情形已经在将尽可能多的所需电感器集成到半导体器件自身中的方向上激发很多电路设计者。
然而，电感器集成到IC中归因于电感器的固有磁性质而产生其它问题。可以使用采用经典分立式电感器组件中所使用的“线圈”或“螺旋”形状的导体来实现IC电感器。因为用于电流在这些结构中流动的路径必须是弯曲的或有角的，因此所感生的磁场倾向于沿着螺旋导电路径的最短可能路径(即沿着最内边沿)逼迫电子。这进而限制用于在增加频率的情况下改进电感器的Q的能力。
因此，通常据信，我们必须增加导电路径必须增加的大小或各相邻匝之间的磁耦合，以提供增加的Q。
在电感器必须尽可能小的情况下，螺旋形状的电感器因此据信对于提供高Q是较不理想的。
也可以通过包括晶体管的有源电路组件来实现电感器。但基于有源电路的电感器关于线性度带来其它挑战。
优选解决方案的概述
上述和其它有关问题激励本发明的各方面，以小形状因子展现非常高Q的矢量电感器组件，其易于合并到基于IC的设计和印制电路板设计中。
在一种布置中，所述矢量电感器包括多个导电元件，均形成为导电材料的单独条带或片块。所述导电元件被布置在垂直堆叠中并且彼此紧密耦合。介电质提供于所述堆叠中的每一对相邻导电元件之间。所述介电质具有电容率并且足够薄，从而提供各相邻导电元件之间的至少二分之一或更大(并且优选地接近0.9或更高)的互感系数。可以通过将介电质构造为非常薄(典型地至少比相邻导体更薄)来实现高互导。
部署在两个或更多个导电元件之间的介电质可以展现远小于1的介电损耗角正切(Tand)。
在电感器充当分立式组件的情况下，各导体可以彼此连接。在所述电感器待包括为并联LC谐振电路或串联LC谐振电路的部分的情况下，所述电感器可以在所述垂直堆叠中仅经由顶部导电元件和底部导电元件直接连接到电容器。
在一种配置中，所述电感器包括多个部件，其中，每个部件包括(i)印制电路板衬底所提供的介电层中的给定介电层；以及(ii)作为所述衬底的任一侧上所部署的金属条带的两个导体。然后以经由粘接层彼此附连的多个部件来形成所述电感器。
所述导体通常是具有从输入端延伸到输出端以激励最大电流流动的至少两个并联侧壁的金属的矩形条带，避免弯曲的路径或有角的路径。这样确保所述导电场路径从输入端到输出端尽可能是笔直的。
附图说明
以下的详细描述参照附图，其中：
图1是以所堆叠的导体和介电层形成的矢量电感器的截面图；
图2是矢量电感器的部分的更详细截面视图；
图3A和图3B是用于导体的两种不同形状的顶视图；
图4是以粘接在一起的多个印制电路板部件形成的矢量电感器的具体实施例的更详细截面视图；
图5A和图5B示出在1吉赫兹(GHz)的用于16个和32个所堆叠的元件的矢量电感器的所建模的电感和品质因数；
图6是矢量电感器组件的等距视图；
图7A和图7B分别示出用于在并联谐振电路和串联谐振电路中连接矢量电感器的一种可能方式；
图8A和图8B示出用于在并联谐振电路和串联谐振电路中连接矢量电感器的另一方式；
图9是使用印制电路板衬底和集成电路电容器的矢量电感器的串联谐振电路实现方式的截面图；以及
图10是使用矢量电感器和集成电路电容器在印制电路板上所实现的示例Chebyshev滤波器的顶层图。
具体实施方式
简言之，用于矢量电感器的优选设计使用印制电路板衬底上和/或其内所形成的紧密耦合的分层导电片块集合。紧密耦合的导体展现高互感系数，至少二分之一或优选地甚至0.9或更高。在一个示例实施例中，与(值N*L的)一个无耦合电感器所占据的大小相比，具有这种非常紧密耦合的电感L的N个互耦的电感器配合到大小1/N的面积中。这样对于电感L的电感器在大小方面产生N2的总减小因数。对于N＝16，大小方面的减小因此比无耦合非分层电感器小256倍。
图1是以在此称为导体102的导电材料的多个紧靠地间隔的片块形成的一个这样的矢量电感器100的高级截面图。N个导体102可以形成为部署在印制电路板衬底上和/或其内的分离的铜层。导体102彼此垂直地对准，并且通过多个介电层104彼此间隔开。对于N个导体102的矢量电感器，将存在N-1个介电层104。
介电层104可以包括任何合适的介电质材料和/或粘接层(例如环氧体)。在导体以机械方式悬停在各端处的实现方式中，介电质甚至可以是空气。
图1中的层厚度并非是按比例示出的。为了激励互耦，介电层104的厚度典型地小于导体102的厚度。在一个示例实现方式中，导体102厚度(或高度H1)对于四分之一盎司铜片块导体可以大约为0.33密耳(对于半盎司铜，0.67)，但介电质104厚度可以仅为0.1密耳。虽然可能的是，介电层中的一些比另一些更厚或更薄，但通常各个介电层104的厚度将是相同的。四分之一盎司和半盎司指代用于印制电路板结构的金属厚度的行业标准术语。
图2示出包括两个相邻导体102以及它们之间所部署的介电质104的矢量电感器100的一个部件或区段105的更详细视图。介电质104具有相对电容率εr。可以示出，以下方程对电压和电流的所得关系进行建模：
V 1 = L d i 2 d t + M d i 2 d t = ( L 2 + M 2 ) d i d t
其中，L是每个导体102的电感，i是流过区段的总电流(从而每个导体102携带i/2的电流)，并且我们可以作出结论：
V 1 = ( L 2 + k L 2 ) d i d t ≈ L d i d t 对于k≈1
其中，V1是穿过电感器结构区段105的电压，M是由下式所给出的互感系数：
M = k L 1 L 2 = k L 因为L1＝L2＝L
其中，L1是第一层的电感，L2是第二层的电感。
因此，当互感相对高时，这种关系将保持成立，从而互感系数k至少为0.5，并且优选地接近0.90或更高。
应注意，在将图2的紧靠地耦合的电感器配对架构与简单金属条带进行比较中，电感器的实数电阻减半，而总电感尚未改变。结果是，对于给定的面积，品质因数Q加倍，而总电感保持在近似L。对于单对导体102，如图2所示，大约150的Q是可能的。
关于每个导电元件102之间所部署的介电质104所选取的材料是这样的：其展现远小于1(典型地接近小于或等于2e-5的某值)的介电损耗角正切(Tand)。
导体102可以假设各种形状；再次，重要的是，导体102彼此紧密耦合。图3A是导体102的一种可能实现方式的顶视图。在此，导体102成形为金属的加长矩形或“条带”。这种矩形条带形状通过消除任何曲线或角度来为电场传输提供最笔直的可能路径。这样进而使得用于给定配置的品质因数最大化。然而，用于导体102的其它形状也可以足以满足所增加的Q的在此的需求。图3B所示的一个这种可能的形状仍具有仍通常矩形主要导电部分155，但现在在每个相对端上具有支路区段157-1、157-2。支路区段157-1、157-2可以有助于对相邻组件和/或电路连接的阻抗匹配。重要的是，尽可能多地避免逼迫电流通过导体102沿着弯曲的传输路径流动以及偏离矩形的任何形状的侧壁中的锐角。
经由导体(例如导电片块102)传输的射频信号的“趋肤效应”使得电流通常在表面或边沿上或其附近流动，而非流过导体102的整个厚度。增加导体102的厚度因此将对所携带的电流的量或传输通过导体的信号所经历的电阻没有任何显著影响。这种趋肤效应因此一般限制以导电材料的条带形成的电感器102中的用于增加Q和总电感的能力。
然而，图2的电感器配对配置可以扩展为图4所示的多层矢量电感器配置。在此，数量P个紧靠地耦合的电感器配对或部件212-1、212-2、……、212-g、……212-P堆叠在一起。至于图1和图2的实施例，示例电感器元件212-g形成为部署在介电质222的任一侧上的导电材料片块220-1、220-2的配对。在此，可以通过印制电路板衬底的“A级”材料来形成介电质222，其中，导体220-1、220-2是部署在其顶部侧和底部侧上的铜片块。所得P部件构造得以相对于彼此垂直地布置，并且使用“B级”材料(例如环氧粘接剂223)而彼此粘接。
以此方式堆叠多个电感器配对212以形成矢量电感器100逼迫电流中的至少一些除了最外部导体层228-1、228-2上的趋肤效应之外还在结构的中部中流过导体220。与相同尺寸的单个固态导体相比，这样改进矢量电感器100的总体电导率。
粘接层223被部署在电感器配对212中的相邻电感器之间；粘接剂223选取为相对薄并且具有相对低的静态相对电容率(介电常数)εr，从而给定的电感器配对212-g将展现对位于紧接之上(电感器配对212-g-1)和之下(电感器配对212-g+1)的其邻近电感器配对的紧密耦合。
各层之间的距离以及各导体之间所部署的材料的介电常数确定整个矢量电感器结构的互耦。图4示出一些典型尺寸。对于近似0.66密耳(16.74μm)的厚度(或高度)的内部导电层220以及近似0.315密耳(8μm)的介电衬底层222，我们将偏好具有大约3.5的介电衬底的εr和大约2.7的粘接层223的εr(如果粘接剂223是0.3密耳(7.62μm)厚)。再次，总介电层厚度小于导电层的厚度。
最外导体228-1、228-2可以优选地稍微比内部导电层220更厚——在此，外部导体可以是2.7密耳(67.54μm)厚。
优选的是，在构成矢量电感器结构的堆叠中，每个导体220具有与相邻导体102(并且实际上，所有其它内部导体220)相同的大小和形状。然而，单独导体的大小和形状方面的变化将不脱离设计的精神。
图4的所堆叠的电感器设计提供优于其它方法的重要优点。一般，包括值L的P个独立电感器的结构将消耗比单个电感器L所消耗的空间更大P倍的空间。然而，与(值P*L的)单个无耦合电感器将占据的空间相比，在图4的互耦合矢量电感器的情况下，配备有非常紧密耦合的大小L的P个互耦的电感器仅需要大小1/P的空间。大小方面的总体减小因此是P2，其中，N是电感器配对的数量。因此，如果P等于16，则大小方面的对应减小比单个电感器的情况小256倍。
在此所示的具有0.95或更高的互感的紧密耦合的矢量电感器倾向于提供可用Q因数方面的重大改进，实现200或更大的Q。
图5A和图5B分别示出对于不同导电片块宽度(以密耳为单位)并且对于两个不同电感器配对的数量(P＝16以及P＝32)在1GHz的操作频率处所提供的所建模的电感和品质因数。该模型假设在顶部外部导体层228-1和底部外部导体层228-2附近提供250密耳厚的空气柱。
图5A中的曲线502示出对于层的数量P＝16作为矩形导体条带220的宽度的函数而变化的所建模的电感，并且对于P＝32，曲线504是电感的相似图线。图5B中的曲线512示出对于P＝16作为导体条带220的宽度的函数而变化的品质因数Q，并且对于P＝32，曲线514是Q的变化。
也可以考虑矢量电感器100如何理想地被配置为连接到其它组件以构成各种类型的RF电路。
图6是意图用于封装为分离分立式组件或单独分立式组件的矢量电感器100的实现方式。在该等距视图(其中，垂直标度距实际标度稍微放大)中可见，如前述实施例那样，再次可见彼此上下堆叠并且通过介电层104紧靠地间隔开的导体102。在各导体102之间和/或沿着支撑导体102的另一结构的各侧部署导电侧壁108。导电侧壁108所提供的这些附加连接可以进一步有助于激励各导体102之间的互感。在此，输入端子118和输出端子119连接得与导体102中的最底部导体相邻。
为了保持总体紧凑大小，对于待合并到串联谐振电路或并联谐振电路的矢量电感器，特定设计是优选的。本领域技术人员应理解，谐振电路可以实现典型地包括若干电感器和电容器的滤波器，其中，滤波器中的电感器和电容器的数量以及它们的具体互连取决于所期望的滤波的类型(带通、低通、高通、带阻等)，并且还取决于对于该滤波器所期望的极点和零点的数量。以下讨论并不涉及滤波器设计的此方面，而是每个单独电感器和电容器组件的物理配置和电连接。
图7A是并联LC谐振电路702的这种可能实现方式的示意图。所示出的是包括导体102和介电层104的矢量电感器100；电感器100再次包括最下导体228-1和最上导体228-2。电容均为C/2的电容器元件704-1和704-2的配对提供电容器C，其中，每个电容器分别与底部导体228-1和顶部导体228-2中的相应一个并联。注意，矢量电感器100的最内导体102在该实现方式中既不彼此连接，它们也不彼此连接。该配置被认为可以提供最高可能Q。
图7B是与图7A的并联LC电路相似的用于串联LC电路的实现方式。再次，电容器706-1、706-2仅连接到最底部228-1和最顶部228-2导体。电容器706-1和706-2可以均具有串联LC电路中所期望的电容C的二分之一。
也可以实现在图8A的情况下的并联LC电路以及在图8B的情况下的串联LC电路。与图7A和图7B的差别在于，使用导电侧壁108来实现矢量电感器100。虽然该配置可能不提供优化的性能特性，但其在一些应用中仍是可接受的，以使得构造更容易。
图9是构成单个矢量电感器100以及电容C1和C2的配对的串联谐振电路900的更详细截面图。根据图7B所示但现在更详细地示出的原理来构造串联谐振电路900，其中，集成电路(IC)芯片类型电容器706-1-1、706-1-2提供电容C1，电容器706-2-1、706-2-2提供电容C2。这种布局特别适用于实现多层印制电路板(PCB)衬底770(图7b)(其可以是FaradFlex)或其它合适的多层衬底中的矢量电感器100。电容器706-1和706-2可以是贴装在PCB衬底750的顶部作为“倒装芯片”的IC芯片组件。电容器芯片706的一个优选实现方式使用以上通过引用合并的专利申请中所描述的CMOS电容器阵列架构。
图10是使用图9的相同原理的更复杂的滤波器设计的顶层图。在此，芯片电容器集合C1、C2、C3、C4、C5、C6与电感器集合I1、I2、I3、I4连接，以提供Chebychev滤波器。电感器I1、I2、I3、I4中的每一个可以实现于PCB衬底内作为矢量电感器100。电感器中的每一个可以具有不同形状，以实现不同的电感，从而实现期望的滤波器响应。
虽然本发明各个实施例现在已经特定地示出于附图中并且描述于上述文本中，但本领域技术人员应理解，在不脱离本发明的范围的情况下，可以在形式和细节方面在其中进行各种改变。因此，意图本发明仅由所附权利要求限定。

Claims (17)

1.一种电感器装置，包括：
多个导电元件，每个形成为导电材料的单独片块，所述导电元件相对于彼此被布置在垂直堆叠中；以及
介电质，部署在至少两个或更多个相邻导电元件之间，所述介电质足够薄，从而提供所述导电元件中的各相邻导电元件之间的至少二分之一(1/2)或更大的互感系数。
2.如权利要求1所述的装置，其中，部署在两个或更多个导电元件之间的所述介电质的相对电容率展现远小于1的介电损耗角正切(Tand)。
3.如权利要求1所述的装置，其中，所述导电元件每个电连接到两个或更多个相邻导电元件。
4.如权利要求1所述的装置，其中，所述电感器还包括并联谐振电路的部分，其中，在所述垂直堆叠中，所述电感器仅经由顶部导电元件直接连接到第一电容器，并仅经由底部导电元件直接连接第二电容器，并且其中，部署在底部导电层与顶部导电层之间的其它导电元件不经由直接导体路径连接到第一电容器或第二电容器。
5.如权利要求4所述的装置，其中，其它导电元件中的两个或更多个彼此连接。
6.如权利要求1所述的装置，其中，所述电感器还包括串联谐振电路的部分，其中，在所述垂直堆叠中，所述电感器仅经由顶部导电元件直接连接到第一电容器，以及底部导电元件直接连接到仅第二电容器，并且其中，部署在底部导电层与顶部导电层之间的其它导电元件不经由直接导体路径连接到第一电容器或第二电容器。
7.如权利要求6所述的装置，其中，其它导电元件中的两个或更多个彼此连接。
8.如权利要求1所述的装置，其中，所述电感器包括部件，其包括(i)作为印制电路板衬底的介电层中的给定介电层以及(ii)作为部署在所述衬底的任一侧上的金属的两个导体。
9.如权利要求8所述的装置，其中，所述印制电路板衬底具有所嵌入的电容器层。
10.如权利要求8所述的装置，其中，所述电感器包括多个部件，通过粘接层彼此附连。
11.一种电感器装置，包括：
多个导体，每个形成为导电材料的单独片块，所述导体相对于彼此垂直地被布置，以形成导体堆叠；以及
薄介电质，部署在两个或更多个相邻导电元件之间，所述介电质具有小于紧接相邻导电元件的厚度的厚度。
12.如权利要求11所述的装置，其中，所述导体形成自具有从输入端延伸到输出端的至少两个并联侧壁的金属的通常矩形条带。
13.如权利要求11所述的装置，其中，所述具有这样的形状：导电场路径从输入端到输出端是笔直的。
14.如权利要求11所述的装置，其中，所述导体具有在从大约0.33密耳到0.7密耳的范围中的厚度。
15.如权利要求11所述的装置，其中，所述介电层具有在从大约0.3到0.315密耳的范围中的厚度。
16.如权利要求11所述的装置，其中，所述堆叠的最顶部导体和最底部导体中的至少一个比所述堆叠的内部导体更厚。
17.如权利要求11所述的装置，其中，所述导体具有在从40到80密耳的范围中的宽度。
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