CN105280591B - 具有保护层的自对准互连件 - Google Patents

具有保护层的自对准互连件 Download PDF

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CN105280591B
CN105280591B CN201410441782.2A CN201410441782A CN105280591B CN 105280591 B CN105280591 B CN 105280591B CN 201410441782 A CN201410441782 A CN 201410441782A CN 105280591 B CN105280591 B CN 105280591B
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dielectric
contact plunger
contact
interlayer dielectric
layer
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CN105280591A (zh
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严佑展
傅劲逢
李佳颖
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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Abstract

集成电路结构包括：第一层层间电介质(ILD)、位于第一ILD中的栅极堆叠件、位于第一ILD上方的第二ILD、位于第二ILD中的接触插塞、以及位于接触插塞的相对两侧上并且与接触插塞相接触的介电保护层。接触插塞和介电保护层位于第二ILD中。介电覆盖层位于接触插塞上方并且与接触插塞相接触。本发明还涉及具有保护层的自对准互连件。

Description

具有保护层的自对准互连件
技术领域
本发明涉及集成电路器件，更具体地，涉及具有保护层的自对准互连件。
背景技术
随着集成电路的制造技术的发展，集成电路器件变得越来越小。集成电路通过导电部件(诸如金属线、通孔和接触插塞)互连以形成功能电路。因此，导电部件之间的间距也变得越来越小。
发明内容
为了解决现有技术中的问题，本发明提供了一种集成电路结构，包括：第一层间电介质(ILD)；栅极堆叠件，位于所述第一ILD中；第二ILD，位于所述第一ILD上方；第一接触插塞，位于所述第二ILD中；介电保护层，位于所述第一接触插塞的相对两侧上并且与所述第一接触插塞接触，其中，所述第一接触插塞和所述介电保护层位于所述第二ILD中；以及介电覆盖层，位于所述第一接触插塞上方并且与所述第一接触插塞接触。
在上述集成电路结构中，其中，所述集成电路结构进一步包括：第三ILD，位于所述第二ILD上方；以及第二接触插塞，从所述第三ILD的顶面延伸到所述第二ILD的底面，其中，所述第二接触插塞电连接至所述栅极堆叠件。
在上述集成电路结构中，其中，所述集成电路结构进一步包括：第三ILD，位于所述第二ILD上方；以及第二接触插塞，从所述第三ILD的顶面延伸到所述第二ILD的底面，其中，所述第二接触插塞电连接至所述栅极堆叠件；其中，所述第二接触插塞包括与所述介电保护层的顶部边缘接触的第一底面。
在上述集成电路结构中，其中，所述第一接触插塞包括与所述第一ILD的顶面接触的底面。
在上述集成电路结构中，其中，所述介电保护层和所述介电覆盖层由相同的介电材料形成。
在上述集成电路结构中，其中，所述集成电路结构进一步包括：源极/漏极区；第三接触插塞，位于所述源极/漏极区上方并且电连接至所述源极/漏极区，其中，所述第三接触插塞位于所述第一ILD中；第四接触插塞，位于所述第三接触插塞上方并且接触所述第三接触插塞，其中，所述第四接触插塞位于所述第二ILD中；以及第五接触插塞，位于所述第四接触插塞上方并且与所述第四接触插塞接触，其中，所述第五接触插塞从第三ILD的顶面延伸到所述第二ILD内。
在上述集成电路结构中，其中，所述集成电路结构进一步包括：源极/漏极区；第三接触插塞，位于所述源极/漏极区上方并且电连接至所述源极/漏极区，其中，所述第三接触插塞位于所述第一ILD中；第四接触插塞，位于所述第三接触插塞上方并且接触所述第三接触插塞，其中，所述第四接触插塞位于所述第二ILD中；以及第五接触插塞，位于所述第四接触插塞上方并且与所述第四接触插塞接触，其中，所述第五接触插塞从第三ILD的顶面延伸到所述第二ILD内；其中，所述第五接触插塞的底面与所述第一接触插塞的顶面基本共平面。
在上述集成电路结构中，其中，所述介电覆盖层的顶面与所述第二ILD的顶面基本共平面。
根据本发明的另一个方面，提供了一种集成电路结构，包括：第一层间电介质(ILD)；蚀刻停止层，位于所述第一ILD上方；第二ILD，位于所述蚀刻停止层上方；第一狭槽式接触插塞，位于所述第二ILD中，其中，所述第一狭槽式接触插塞穿透所述蚀刻停止层以接触所述第一ILD的顶面；介电保护层，包括位于所述第一狭槽式接触插塞的相对两侧上并且与所述第一狭槽式接触插塞接触的部分；以及介电覆盖层，位于所述第一狭槽式接触插塞上方并且与所述第一狭槽式接触插塞接触，其中，所述第一狭槽式接触插塞、所述介电保护层和所述介电覆盖层均位于所述第二ILD中。
在上述集成电路结构中，其中，所述介电覆盖层包括与所述介电保护层的相对部分接触的相对边缘。
在上述集成电路结构中，其中，所述介电覆盖层的顶面、所述介电保护层的顶部边缘以及所述第二ILD的顶面基本共平面。
在上述集成电路结构中，其中，所述集成电路结构进一步包括：第一源极/漏极区，位于所述第一ILD下方；栅极堆叠件，位于所述第一ILD中；第三ILD，位于所述第二ILD上方；以及栅极接触插塞，位于所述第二ILD和所述第三ILD中。
在上述集成电路结构中，其中，所述集成电路结构进一步包括：第二源极/漏极区，位于所述第一ILD下方；第二狭槽式接触插塞，位于所述第二源极/漏极区上方并且电连接至所述第二源极/漏极区，其中，所述第二狭槽式接触插塞位于所述第一ILD中；第三狭槽式接触插塞，位于所述第二狭槽式接触插塞上方并且接触所述第二狭槽式接触插塞，其中，所述第三狭槽式接触插塞位于所述第二ILD中；第三ILD，位于所述第二ILD上方；以及接触插塞，穿透所述第三ILD，其中，所述接触插塞与所述第三狭槽式接触插塞接触。
在上述集成电路结构中，其中，所述集成电路结构进一步包括：第二源极/漏极区，位于所述第一ILD下方；第二狭槽式接触插塞，位于所述第二源极/漏极区上方并且电连接至所述第二源极/漏极区，其中，所述第二狭槽式接触插塞位于所述第一ILD中；第三狭槽式接触插塞，位于所述第二狭槽式接触插塞上方并且接触所述第二狭槽式接触插塞，其中，所述第三狭槽式接触插塞位于所述第二ILD中；第三ILD，位于所述第二ILD上方；以及接触插塞，穿透所述第三ILD，其中，所述接触插塞与所述第三狭槽式接触插塞接触；其中，所述接触插塞的底面低于所述第二ILD的顶面。
根据本发明的又一方面，提供了一种方法，包括：在第一ILD上方形成第二层间电介质(ILD)，栅极堆叠件位于所述第一ILD中；蚀刻所述第二ILD以形成第一接触开口；在所述第一接触开口的相对侧壁上形成介电保护层；在所述第一接触开口中形成第一接触插塞，所述第一接触插塞位于所述介电保护层的相对部分之间；形成位于所述第一接触插塞上方并且接触所述第一接触插塞的介电覆盖层；在所述第二ILD上方形成第三ILD；在所述第二ILD和所述第三ILD中形成第二接触开口；以及填充所述第二接触开口以形成第二接触插塞。
在上述方法中，其中，形成所述介电覆盖层包括：使所述第一接触插塞凹进以形成凹槽；在所述凹槽中填充所述介电覆盖层；以及平坦化所述介电覆盖层，其中，所述介电覆盖层的顶面与所述第二ILD的顶面基本平齐。
在上述方法中，其中，在形成所述第二接触开口中，所述介电保护层暴露于所述第二接触开口，并且其中，在形成所述第二接触开口期间，基本不蚀刻所述介电保护层。
在上述方法中，其中，在形成所述第一接触开口之后，所述第一ILD暴露于所述第一接触开口。
在上述方法中，其中，所述方法进一步包括：在形成所述第二ILD之前，在所述第一ILD上方形成蚀刻停止层，其中，所述第一接触开口穿透所述蚀刻停止层。
在上述方法中，其中，所述方法进一步包括：当形成所述第二接触插塞时，同时在所述第二ILD和所述第三ILD中形成源极/漏极接触插塞。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的各方面。应该注意，根据工业中的标准实践，各种部件没有被按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以任意地增大或减小。
图1至图12示出了根据一些实施例形成包括接触插塞的互连结构的中间阶段的截面图；以及
图13示出了根据一些实施例的接触插塞的顶视图；以及
图14示出了根据一些实施例的用于形成互连结构的工艺流程。
具体实施方式
为了实施本发明的不同特征，以下公开提供了许多不同的实施例或实例。以下描述部件和布置的具体实例以简化本发明。当然这些仅仅是实例并不旨在限定。例如，在以下描述中，第一部件形成在第二部件上方或上可包括第一部件和第二部件以直接接触的方式形成的实施例，并且也可包括在第一部件和第二部件之间可以形成额外的部件，使得第一部件和第二部件不直接接触的实施例。另外，本发明可在各个实施例中重复参考标号和/或字符。这种重复只是为了简明的目的且其本身并不指定各个实施例和/或所讨论的结构之间的关系。
另外，为了便于描述，在本文中可以使用诸如“在…之下”、“下方”、“下部”、“在…之上”、“上部”等的空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位之外，这些空间相对术语旨在包括器件在使用或操作过程中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文中使用的空间相对描述符可以同样地作出相应的解释。
根据不同的示例性实施例，提供了包括接触插塞的互连结构及其形成方法。示出了形成互连结构的中间阶段。讨论了实施例的变化。在各个视图和说明性实施例中，相同的参考标号用于表示相同的元件。
图1至图12示出了根据一些实施例形成互连结构的中间阶段的截面图。在图14中示出的工艺流程200中也示意性地示出了图1至图12中示出的步骤。在后续讨论中，参考图14中的工艺步骤来论述图1至图12中的工艺步骤。
图1示出了晶圆100，晶圆100包括半导体衬底20和形成于半导体衬体20的顶面处的部件。根据一些实施例，半导体衬底20包括晶体硅、晶体锗、硅锗、III-V族化合物半导体等。半导体衬底20也可以是块状硅衬底或绝缘体上硅(SOI)衬底。浅沟槽隔离(STI)区22可以形成在半导体衬底20中以隔离半导体衬底20中的有源区。
多个栅极堆叠件26(包括26A、26B、26C、26D和26E)形成在半导体衬底20上方。根据一些实施例，栅极堆叠件26是通过形成伪栅极堆叠件(未示出)，然后以替代栅极代替伪栅极堆叠件而形成的替代栅极。因此，每一个栅极堆叠件26均包括栅极电介质28和位于栅极电介质28上方的栅电极30。栅极电介质28进一步包括位于相应的栅电极30下面的底部和位于相应的栅电极30的侧壁上的侧壁部分。根据本发明的一些实施例，栅极电介质28包括氧化硅、氮化硅、高k介电材料(诸如氧化铪、氧化镧、氧化铝)、它们的组合和/或它们的多层。栅电极30可以是包括例如TiAl、钴、铝、氮化钛、氮化钽等的金属栅极，并且可以包括不同材料的多层。根据包括栅电极30的相应晶体管是P型金属氧化物半导体(PMOS)晶体管还是N型金属氧化物半导体(NMOS)晶体管，栅电极30的材料选择为具有适合于相应的MOS晶体管的功函数。栅极间隔件32形成在栅极堆叠件26的侧壁上。栅极间隔件32可以包括氧化硅、氮化硅等。
如图1所示，诸如栅极堆叠件26A、26B、26D及26E的一些栅极堆叠件由介电层36覆盖。栅极堆叠件的这些部分可以用作路由线，并且可以形成图1所示出的或图1未示出的平面中的晶体管。根据一些实施例，介电层36包括诸如氧化硅、氮化硅、碳化硅、氮氧化硅等的介电材料。诸如栅极堆叠件26C的其他栅极堆叠件由导电层38覆盖。应当理解，栅极堆叠件26C也可以具有形成在其上的介电层36，其中，导电层38形成在相应的上面的介电层36的开口中。然而，由于覆盖栅极堆叠件26C的介电层36不在如图1所示的同一平面中，因此相应的介电层36在图1中未示出。
层间电介质(ILD)34形成在半导体衬底20上方，并且填充栅极间隔件32之间的间隔。因此，ILD 34和栅极堆叠件26形成在相同的水平面处。本说明书中，ILD 34也被称为ILD0 34。在一些示例性实施例中，ILD0 34包括磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)、氟掺杂的硅酸盐玻璃(FSG)、正硅酸乙酯(TEOS)等。
MOS晶体管的源极区和漏极区(下文称为源极/漏极区)24形成于半导体衬底20中。根据一些实施例，源极/漏极区24包括p型或n型杂质，这取决于相应的晶体管是p型MOS晶体管还是n型MOS晶体管。当相应的晶体管为n型MOS晶体管时，源极/漏极区24可以包括SiP；当相应的晶体管为p型MOS晶体管时，源极/漏极区24可以包括SiGe。源极/漏极区24的形成可以包括在半导体衬底20中形成凹槽，以及在凹槽中外延生长源极/漏极区24。在一些示例性实施例中，栅极堆叠件26D和位于栅极堆叠件26D的相对两侧的源极/漏极区24形成晶体管。
源极/漏极接触插塞42(包括42A和42B)形成于ILD0 34中。源极/漏极接触插塞42的顶面可以与介电层36和ILD0 34的顶面共平面或基本共平面。虽然图1示意性地示出了源极/漏极接触插塞42与栅极间隔件32相接触，但是源极/漏极接触插塞42可以通过ILD0 34与栅极间隔件32分隔开。根据一些实施例，源极/漏极接触插塞42由钨、铜、铝或它们的合金形成。源极/漏极接触插塞42也可以包括粘合/阻挡层(未示出)，该粘合/阻挡层由钛、氮化钛、钽、氮化钽等形成。源极/漏极接触插塞42电连接至相应的下面的源极/漏极区24。源极/漏极硅化物区(未示出)可以形成在源极/漏极区24与相应的上面的源极/漏极接触插塞42A和42B之间且与它们相接触。
图13示出了根据一些实施例的包括栅极堆叠件26和源极/漏极接触插塞42A和42B的结构的顶视图。在示出的实施例中，栅极堆叠件26形成为相互平行的条状物。平行的栅极堆叠件26可以具有均匀的节距和均匀的间距。源极/漏极接触插塞42A、42B示出为长度明显大于相应宽度的条状狭槽式接触插塞。狭槽式接触插塞除了连接至源极/漏极区24(图1)的功能外也可以用作路由线。在可选实施例中，在顶视图中，源极/漏极接触插塞42A和42B的长度和宽度也可以彼此接近。
再次参照图1所示的工艺步骤，蚀刻停止层44形成在栅极堆叠件26、源极/漏极接触插塞42和ILD0 34上方。蚀刻停止层44可以包括碳化硅、氮氧化硅、碳氮化硅等。ILD 46(下文称为ILD1 46)形成在蚀刻停止层44上方。根据一些实施例，ILD1 46包括选自PSG、BSG、PBSG、FSG、TEOS及其他无孔低k介电材料中的材料。ILD1 46和ILD0 34可以由相同的材料或不同的材料形成，并且可以选自同组的候选材料。ILD1 46可以使用旋涂、可流动化学汽相沉积(FCVD)等形成。在本发明的可选实施例中，ILD1 46使用诸如等离子体增强化学汽相沉积(PECVD)、低压化学汽相沉积(LPCVD)等的沉积方法形成。
参照图2所示的工艺步骤(图14中的工艺流程中的步骤202)，蚀刻ILD1 46和蚀刻停止层44以形成接触开口48(包括48A和48B)。例如，使用反应离子蚀刻(RIE)实施蚀刻。在蚀刻工艺之后，接触插塞42A和ILD0 34分别暴露于接触开口48A和48B。蚀刻可以是各向异性的，从而使得接触开口48的侧壁是基本垂直的。
接下来，参照图3所示的工艺步骤(图14中的工艺流程中的步骤204)，形成介电保护层50。根据一些实施例，介电保护层50包括选自SiN、SiON、SiCN、SiOCN、AlON、AlN、它们的组合的介电材料和/或它们的多层。介电保护层50的厚度T1和T2可以介于约3nm和约10nm的范围内。然而，应当理解，本说明书中所列举的值仅为实例且可以改变为不同的值。
根据本发明中的一些实施例，使用PECVD、等离子体增强原子层沉积(PEALD)、原子层沉积(ALD)、高密度等离子体化学汽相沉积(HDP CVD)或类似的方法形成介电保护层50。
介电保护层50可以是其水平部分的厚度T1与垂直部分的厚度T2彼此相似的共形层。例如，差值|T1-T2|可以小于厚度T1和厚度T2的约20％或约10％。介电保护层50包括位于ILD1 46上方的一些部分和延伸到接触开口48A和48B内的其他部分。此外，介电保护层50覆盖接触开口48A和48B的底部。
接下来，参照图4中所示的工艺步骤(也是图14中的工艺流程中的步骤204)，例如，使用干蚀刻来实施蚀刻步骤。去除介电保护层50的水平部分，并且保留接触开口48中的介电保护层50的垂直部分。在图4中的结构的顶视图中，剩余的介电保护层50可以形成完整的环，每个环均环绕接触开口48A和48B中的一个(图13)。去除介电保护层50的位于接触开口48A和48B的底部的部分，并且因此，源极/漏极接触插塞42A和ILD034再次暴露于相应的接触开口48A和48B。
参照图5中所示的工艺步骤(图14中的工艺流程中的步骤206)，接触插塞52(包括52A和52B)分别形成在接触开口48A和48B(图4)中。根据本发明的一些实施例，接触插塞52由选自钨、铝、铜、钛、钽、氮化钛、氮化钽、它们的合金的材料和/或它们的多层形成。接触插塞52的形成可以包括将导电材料填充到接触开口48A和48B(图4)内，直至导电材料充满整个接触开口48A和48B，以及实施平坦化(诸如化学机械抛光(CMP))以使接触插塞52的顶面与ILD1 46的顶面平齐。如图13中的顶视图所示，在产生的结构中，介电保护层50形成环绕每个接触插塞52的完整的环。
如图13所示，根据一些实施例，接触插塞52A的宽度和长度可以与下面的接触插塞42A的宽度和长度相同或不同。此外，由于接触插塞52A和42A在不同的工艺步骤中形成，因此接触插塞52A和42A可以是彼此不同的。
接下来，如图6中示出的工艺步骤(图14中的工艺流程中的步骤208)所示，根据本发明的一些实施例，回蚀刻接触插塞52A和52B，从而在ILD146中形成凹槽54(包括54A和54B)。凹槽54A和54B的深度D1大于约5nm,并且可以介于约5nm和约20nm的范围内。
图7示出了介电覆盖层56的沉积(图14中的工艺流程中的步骤210)。根据一些实施例，介电覆盖层56完全填充凹槽54A和54B(图6)，并且介电覆盖层56的顶面高于ILD1 46的顶面。因此，介电覆盖层56的厚度T3大于约5nm，并且可以介于约5nm和约20nm的范围内。根据一些实施例，介电覆盖层56包括选自SiN、SiON、SiCN、SiOCN、AlON、AlN、它们的组合的介电材料和/或它们的多层。介电覆盖层56可以使用PECVD、PEALD、ALD、HDP CVD或类似的方法形成。根据一些实施例，介电覆盖层56和介电保护层50由相同的介电材料形成。根据可选实施例，介电覆盖层56和介电保护层50由不同的材料形成。然而，介电覆盖层56和介电保护层50的特性与ILD1 46的特性不同，从而使得在ILD1 46的后续蚀刻中，介电覆盖层56和介电保护层50的蚀刻速率比ILD1 46的蚀刻速率低。
再次参照图8中所示的工艺步骤(图14中的工艺流程中的步骤210)，实施诸如CMP的平坦化以去除介电覆盖层56的多余部分，其中介电覆盖层56的多余部分位于ILD1 46的顶面上方。从而，介电覆盖层56的剩余部分的顶面与ILD1 46的顶面平齐。此外，根据本发明的一些实施例，介电覆盖层56的剩余部分的顶面可以与介电保护层50的顶部边缘平齐。在一些示例性实施例中，介电覆盖层56的剩余部分的侧边也可以与接触插塞52B的相应边缘对准。此外，介电覆盖层56的剩余部分的侧边与介电保护层50相接触。
因为形成了介电覆盖层56和介电保护层50，介电覆盖层56和介电保护层50从所有的侧壁和顶部完全地保护了接触插塞52B。介电覆盖层56和介电保护层50共同形成了反向池(inversed basin)，接触插塞52B位于该反向池中。
如图8中的工艺步骤所示，接触插塞52B形成在ILD0 34上方，并可以与ILD0 34相接触。也如图13所示，图13为顶视图，接触插塞52可以是狭槽式接触插塞。接触插塞52B可以用作用于互连目的的路由线。连接至接触插塞52B的相对两端的连接件并未示出，其中接触插塞52B的相对两端可以电连接至源极/漏极(硅化物)区(未示出)和/或上面的接触插塞(未示出)，上面的接触插塞可与图12所示的接触插塞64C相似。
根据示例性实施例，图13示出了接触插塞52A和52B、介电覆盖层56和保护层50的顶视图。如图13所示，接触插塞52A和52B以及介电覆盖层56可以形成为狭槽式接触插塞，该狭槽式接触插塞的长度远远大于相应的宽度。在可选实施例中，接触插塞52和介电覆盖层56的长度也可以接近于相应的宽度，并且接触插塞52和介电覆盖层56具有接近正方形的顶视形状。接触插塞52A和52B也可以由上面的介电覆盖层56的剩余部分完全覆盖。根据一些实施例，接触插塞52A和52B至少分别覆盖相应的下面的接触插塞42A和42B。
参照图9所示的工艺步骤，形成ILD2 58。ILD2 58可以使用旋涂、FCVD等方法形成。在本发明的可选实施例中，ILD2 58可以使用诸如PECVD、LPCVD等的沉积方法形成。在一些实施例中，ILD2 58位于ILD146上方并与ILD1 46相接触。在可选实施例中，在ILD1 46与ILD2 58之间形成蚀刻停止层(未示出)。如果形成了蚀刻停止层，则蚀刻停止层可以包括碳化硅、氮氧化硅、碳氮化硅等。ILD2 58形成在蚀刻停止层上方。ILD2 58可以包括选自PSG、BSG、PBSG、FSG、TEOS或其他无孔低k介电材料中的材料。ILD2 58、ILD1 46和ILD0 34可以由相同的材料或不同的材料形成。
参照图10所示的工艺步骤，蚀刻ILD2 58以形成接触开口60。相应的步骤也如图14中示出的工艺流程中的步骤212所示。接触开口60与介电覆盖层56(图9)和接触插塞52A对准。在ILD 58的蚀刻之后，蚀刻介电覆盖层56，并且暴露接触插塞52A。在一些实施例中，开口60的底部低于介电保护层50的顶部边缘。开口60的底部可以与接触插塞52B的顶面共平面。
接下来，参照图11所示的工艺步骤，实施额外的蚀刻步骤以在ILD2 58和ILD1 46中形成开口62。相应的步骤也如图14中示出的工艺流程中的步骤214所示。在该步骤中，将蚀刻剂选择为使得蚀刻剂侵蚀ILD2 58和ILD146但不侵蚀介电覆盖层56和介电保护层50。例如，蚀刻剂的蚀刻选择性(即，ILD2 58和ILD1 46的蚀刻速率与介电覆盖层56和介电保护层50的蚀刻速率的比值)大于约10。蚀刻选择性也可以大于约50或大于约100。期望的蚀刻选择性与ILD1 46的厚度T4和介电覆盖层56的厚度T5有关，并且至少大于厚度比T4/T5。期望的蚀刻选择性也可以大于厚度比T4/T5的两倍。这确保在发生未对准并且开口62A偏移到63所标记的位置时，则介电覆盖层56和介电保护层50不被蚀刻穿，并且随后形成的接触插塞64A(图12)不会与接触插塞52B电短路。
在蚀刻ILD2 58和ILD1 46之后，通过开口62A和62B进一步蚀刻蚀刻停止层44以暴露下面的导电层38和接触插塞42B。
图12示出了分别在开口62A、62B和60(图11)中的接触插塞64(包括64A、64B和64C)的形成。相应的步骤也如图14中示出的工艺流程中的步骤216所示。形成工艺可以包括将导电材料填充到开口62A、62B和60内，直到导电材料的顶面高于ILD2 58的顶面，以及实施诸如CMP的平坦化以去除导电材料的多余部分。导电材料的剩余部分是接触插塞64。如图12所示，接触插塞64A是电连接至栅极堆叠件26C的栅电极30的栅极接触插塞。接触插塞64B是电连接至接触插塞42B的源极/漏极接触插塞，该接触插塞42B进一步连接至相应的下面的源极/漏极区24。接触插塞64C是电连接至接触插塞52A和42A的源极/漏极接触插塞，接触插塞52A和42A进一步连接至相应的下面的源极/漏极区24。
参照图13，其示意性地示出了图12中示出的结构的顶视图，接触插塞64A、64B和64C的顶视形状可以为诸如正方形的非细长的形状，但是可以使用细长的形状。此外，接触插塞64A靠近接触插塞52B。因此，如果发生了未对准，接触插塞64A的位置可能不期望地偏移，从而与接触插塞52B的一部分发生重叠。如图12所示，即使在形成开口62A中发生这样的未对准，在ILD2 58和ILD1 46的蚀刻中，介电覆盖层56和介电保护层50将用作蚀刻停止层，并且介电覆盖层56和介电保护层50不会被蚀刻穿。因此，如图12所示，当形成接触插塞64A时，介电覆盖层56和介电保护层50将使接触插塞64A与接触插塞52B电绝缘，且将不会发生接触插塞64A与接触插塞52B之间的不期望的短路。
图12所示，当发生未对准时，如虚线所示的产生的接触插塞64A将具有底面65，该底面65定位在介电保护层50的顶部边缘上并且也可能定位在介电覆盖层56的顶面上。作为比较，如果未形成介电覆盖层56和介电保护层50，则在图12所示的步骤中，因未对准，接触插塞64A偏移到位置63，接触插塞64A和接触插塞52B将会短路。
图14示意性地示出了用于图1至图12中的工艺的工艺流程200。本文简要地讨论了该工艺流程。工艺流程的细节可在图1至图12的讨论中找到。如图2所示，在步骤202中，在ILD1 46中形成接触开口48A和48B。在图14中的工艺流程的步骤204中，形成了介电层50，并且图3和图4中示出了相应的形成工艺。在图14中的工艺流程的步骤206中，在ILD1 46中形成接触插塞52，并且图5中示出了相应的形成工艺。在图14中的工艺流程的步骤208中，使接触插塞52凹进以形成凹槽54，并且图6中示出了相应的形成工艺。在图14中的工艺流程的步骤210中，形成介电覆盖层56以覆盖接触插塞52，并且图7和图8中示出了相应的形成工艺。在图14中的工艺流程的步骤212中，形成接触开口60，并且图10中示出了相应的形成工艺。在图14中的工艺流程的步骤214中，形成接触开口62，并且图11中示出了相应的形成工艺。在图14中的工艺流程的步骤216中，填充接触开口60和62以形成接触插塞64，并且图12中示出了相应的形成工艺。
本发明的实施例具有一些有利的特征。通过形成介电保护层和介电覆盖层以保护接触插塞，即使邻近接触插塞的相邻的接触插塞具有未对准，介电保护层和介电覆盖层将保留以使位置相近的接触插塞绝缘。
根据本发明的一些实施例，一种集成电路结构包括：第一ILD、位于第一ILD中的栅极堆叠件、位于第一ILD上方的第二ILD、位于第二ILD中的接触插塞、以及位于接触插塞的相对两侧上并且与接触插塞相接触的介电保护层。接触插塞和介电保护层位于第二ILD中。介电覆盖层位于接触插塞上方并与接触插塞相接触。
根据本发明的可选实施例，一种集成电路结构包括：第一ILD、位于第一ILD上方的蚀刻停止层、位于蚀刻停止层上方的第二ILD以及第二ILD中的狭槽式接触插塞。狭槽式接触插塞穿透蚀刻停止层以接触第一ILD的顶面。介电保护层包括位于狭槽式接触插塞的相对两侧且与狭槽式接触插塞接触的部分。介电覆盖层位于狭槽式接触插塞上方且与狭槽式接触插塞接触，其中，狭槽式接触插塞、介电保护层和介电覆盖层均位于第二ILD中。
根据本发明的又可选实施例，一种方法包括：在第一ILD上方形成第二ILD，其中栅极堆叠件位于第一ILD中，蚀刻第二ILD以形成第一接触开口，在第一接触开口的相对侧壁上形成介电保护层，以及在第一接触开口中形成第一接触插塞，其中第一接触插塞位于介电保护层的相对部分之间。该方法进一步包括：形成位于第一接触插塞上方并接触第一接触插塞的介电覆盖层，在第二ILD上方形成第三ILD，在第二ILD和第三ILD中形成第二接触开口，以及填充第二接触开口以形成第二接触插塞。
上面论述了若干实施例的特征，使得本领域普通技术人员可以更好地理解本发明的各个方面。本领域普通技术人员应该理解，他们可以容易地使用本发明作为基础来设计或更改用于与本文所介绍的实施例实施相同的目的和/或实现相同优点的其他工艺和结构。本领域普通技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，他们可以作出多种变化、替换以及改变。

Claims (18)

1.一种集成电路结构，包括：
第一层间电介质；
栅极堆叠件，位于所述第一层间电介质中；
第二层间电介质，位于所述第一层间电介质上方；
第一接触插塞，位于所述第二层间电介质中；
介电保护层，位于所述第一接触插塞的相对两侧上并且与所述第一接触插塞接触，其中，所述第一接触插塞和所述介电保护层位于所述第二层间电介质中；以及
介电覆盖层，位于所述第一接触插塞上方并且与所述第一接触插塞接触，
其中，所述介电覆盖层的顶面、所述介电保护层的顶部边缘以及所述第二层间电介质的顶面共平面。
2.根据权利要求1所述的集成电路结构，进一步包括：
第三层间电介质，位于所述第二层间电介质上方；以及
第二接触插塞，从所述第三层间电介质的顶面延伸到所述第二层间电介质的底面，其中，所述第二接触插塞电连接至所述栅极堆叠件。
3.根据权利要求2所述的集成电路结构，其中，所述第二接触插塞包括与所述介电保护层的顶部边缘接触的第一底面。
4.根据权利要求1所述的集成电路结构，其中，所述第一接触插塞包括与所述第一层间电介质的顶面接触的底面。
5.根据权利要求1所述的集成电路结构，其中，所述介电保护层和所述介电覆盖层由相同的介电材料形成。
6.根据权利要求1所述的集成电路结构，进一步包括：
源极/漏极区；
第三接触插塞，位于所述源极/漏极区上方并且电连接至所述源极/漏极区，其中，所述第三接触插塞位于所述第一层间电介质中；
第四接触插塞，位于所述第三接触插塞上方并且接触所述第三接触插塞，其中，所述第四接触插塞位于所述第二层间电介质中；以及
第五接触插塞，位于所述第四接触插塞上方并且与所述第四接触插塞接触，其中，所述第五接触插塞从第三层间电介质的顶面延伸到所述第二层间电介质内。
7.根据权利要求6所述集成电路结构，其中，所述第五接触插塞的底面与所述第一接触插塞的顶面共平面。
8.一种集成电路结构，包括：
第一层间电介质；
蚀刻停止层，位于所述第一层间电介质上方；
第二层间电介质，位于所述蚀刻停止层上方；
第一狭槽式接触插塞，位于所述第二层间电介质中，其中，所述第一狭槽式接触插塞穿透所述蚀刻停止层以接触所述第一层间电介质的顶面；
介电保护层，包括位于所述第一狭槽式接触插塞的相对两侧上并且与所述第一狭槽式接触插塞接触的部分；以及
介电覆盖层，位于所述第一狭槽式接触插塞上方并且与所述第一狭槽式接触插塞接触，其中，所述第一狭槽式接触插塞、所述介电保护层和所述介电覆盖层均位于所述第二层间电介质中。
9.根据权利要求8所述的集成电路结构，其中，所述介电覆盖层包括与所述介电保护层的相对部分接触的相对边缘。
10.根据权利要求8所述的集成电路结构，其中，所述介电覆盖层的顶面、所述介电保护层的顶部边缘以及所述第二层间电介质的顶面共平面。
11.根据权利要求8所述的集成电路结构，进一步包括：
第一源极/漏极区，位于所述第一层间电介质下方；
栅极堆叠件，位于所述第一层间电介质中；
第三层间电介质，位于所述第二层间电介质上方；以及
栅极接触插塞，位于所述第二层间电介质和所述第三层间电介质中。
12.根据权利要求8所述的集成电路结构，进一步包括：
第二源极/漏极区，位于所述第一层间电介质下方；
第二狭槽式接触插塞，位于所述第二源极/漏极区上方并且电连接至所述第二源极/漏极区，其中，所述第二狭槽式接触插塞位于所述第一层间电介质中；
第三狭槽式接触插塞，位于所述第二狭槽式接触插塞上方并且接触所述第二狭槽式接触插塞，其中，所述第三狭槽式接触插塞位于所述第二层间电介质中；
第三层间电介质，位于所述第二层间电介质上方；以及
接触插塞，穿透所述第三层间电介质，其中，所述接触插塞与所述第三狭槽式接触插塞接触。
13.根据权利要求12所述的集成电路结构，其中，所述接触插塞的底面低于所述第二层间电介质的顶面。
14.一种形成集成电路结构的方法，包括：
在第一层间电介质上方形成第二层间电介质，栅极堆叠件位于所述第一层间电介质中；
蚀刻所述第二层间电介质以形成第一接触开口；
在所述第一接触开口的相对侧壁上形成介电保护层；
在所述第一接触开口中形成第一接触插塞，所述第一接触插塞位于所述介电保护层的相对部分之间；
形成位于所述第一接触插塞上方并且接触所述第一接触插塞的介电覆盖层；
在所述第二层间电介质上方形成第三层间电介质；
在所述第二层间电介质和所述第三层间电介质中形成第二接触开口；
以及
填充所述第二接触开口以形成第二接触插塞，
其中，形成所述介电覆盖层包括：
使所述第一接触插塞凹进以形成凹槽；
在所述凹槽中填充所述介电覆盖层；和
平坦化所述介电覆盖层，其中，所述介电覆盖层的顶面与所述第二层间电介质的顶面平齐。
15.根据权利要求14所述的形成集成电路结构的方法，其中，在形成所述第二接触开口中，所述介电保护层暴露于所述第二接触开口，并且其中，在形成所述第二接触开口期间，不蚀刻所述介电保护层。
16.根据权利要求14所述的形成集成电路结构的方法，其中，在形成所述第一接触开口之后，所述第一层间电介质暴露于所述第一接触开口。
17.根据权利要求14所述的形成集成电路结构的方法，进一步包括：
在形成所述第二层间电介质之前，在所述第一层间电介质上方形成蚀刻停止层，其中，所述第一接触开口穿透所述蚀刻停止层。
18.根据权利要求14所述的形成集成电路结构的方法，进一步包括：当形成所述第二接触插塞时，同时在所述第二层间电介质和所述第三层间电介质中形成源极/漏极接触插塞。
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