CN102859649B - 外延硅晶片及其制造方法、以及贴合soi晶片及其制造方法 - Google Patents

外延硅晶片及其制造方法、以及贴合soi晶片及其制造方法 Download PDF

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CN102859649B
CN102859649B CN201180017235.6A CN201180017235A CN102859649B CN 102859649 B CN102859649 B CN 102859649B CN 201180017235 A CN201180017235 A CN 201180017235A CN 102859649 B CN102859649 B CN 102859649B
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wafer
epitaxial
angle
soi
layer
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CN102859649A (zh
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加藤正弘
冈哲史
小林德弘
石塚徹
能登宣彦
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Shin Etsu Handotai Co Ltd
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Shin Etsu Handotai Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02576—N-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)
CN201180017235.6A 2010-04-01 2011-03-01 外延硅晶片及其制造方法、以及贴合soi晶片及其制造方法 Active CN102859649B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2010-085381 2010-04-01
JP2010085381A JP5544986B2 (ja) 2010-04-01 2010-04-01 貼り合わせｓｏｉウェーハの製造方法、及び貼り合わせｓｏｉウェーハ
PCT/JP2011/001175 WO2011125282A1 (ja) 2010-04-01 2011-03-01 シリコンエピタキシャルウェーハ及びその製造方法、並びに貼り合わせｓｏｉウェーハ及びその製造方法

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CN102859649A CN102859649A (zh) 2013-01-02
CN102859649B true CN102859649B (zh) 2015-06-24

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US (1) US8823130B2 (enExample)
EP (1) EP2555227B1 (enExample)
JP (1) JP5544986B2 (enExample)
KR (1) KR101729474B1 (enExample)
CN (1) CN102859649B (enExample)
WO (1) WO2011125282A1 (enExample)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6200273B2 (ja) * 2013-10-17 2017-09-20 信越半導体株式会社 貼り合わせウェーハの製造方法
US20150270344A1 (en) * 2014-03-21 2015-09-24 International Business Machines Corporation P-fet with graded silicon-germanium channel
CN103871902A (zh) 2014-03-24 2014-06-18 上海华力微电子有限公司 半导体处理工艺及半导体器件的制备方法
CN105869991B (zh) 2015-01-23 2018-05-11 上海华力微电子有限公司 用于改善SiGe厚度的均匀性的方法和系统
CN105990172B (zh) 2015-01-30 2018-07-31 上海华力微电子有限公司 嵌入式SiGe外延测试块的设计
CN105990342B (zh) 2015-02-13 2019-07-19 上海华力微电子有限公司 具有用于嵌入锗材料的成形腔的半导体器件及其制造工艺
CN104851884A (zh) 2015-04-14 2015-08-19 上海华力微电子有限公司 用于锗硅填充材料的成形腔
CN104821336B (zh) 2015-04-20 2017-12-12 上海华力微电子有限公司 用于使用保形填充层改善器件表面均匀性的方法和系统
FR3036845B1 (fr) * 2015-05-28 2017-05-26 Soitec Silicon On Insulator Procede de transfert d'une couche d'un substrat monocristallin
CN105097554B (zh) 2015-08-24 2018-12-07 上海华力微电子有限公司 用于减少高浓度外延工艺中的位错缺陷的方法和系统
EP3179093A1 (en) * 2015-12-08 2017-06-14 Winfoor AB Rotor blade for a wind turbine and a sub-member
JP6474048B2 (ja) * 2015-12-25 2019-02-27 信越半導体株式会社 エピタキシャルウェーハの製造方法
KR102181277B1 (ko) * 2016-08-10 2020-11-20 가부시키가이샤 사무코 에피택셜 실리콘 웨이퍼의 제조 방법
CN109844938B (zh) * 2016-08-12 2023-07-18 Qorvo美国公司 具有增强性能的晶片级封装
JP6662250B2 (ja) * 2016-09-07 2020-03-11 信越半導体株式会社 シリコンエピタキシャルウェーハの製造方法及び半導体デバイスの製造方法
KR102279113B1 (ko) * 2017-04-06 2021-07-16 가부시키가이샤 사무코 에피택셜 실리콘 웨이퍼의 제조 방법 및 에피택셜 실리콘 웨이퍼
US11152363B2 (en) 2018-03-28 2021-10-19 Qorvo Us, Inc. Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process
WO2019195428A1 (en) 2018-04-04 2019-10-10 Qorvo Us, Inc. Gallium-nitride-based module with enhanced electrical performance and process for making the same
US12046505B2 (en) 2018-04-20 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same utilizing localized SOI formation
CN112534553B (zh) 2018-07-02 2024-03-29 Qorvo美国公司 Rf半导体装置及其制造方法
US11646242B2 (en) 2018-11-29 2023-05-09 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
US12046570B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12046483B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12057374B2 (en) 2019-01-23 2024-08-06 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
CN113632209A (zh) 2019-01-23 2021-11-09 Qorvo美国公司 Rf半导体装置和其制造方法
US12125825B2 (en) 2019-01-23 2024-10-22 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11387157B2 (en) 2019-01-23 2022-07-12 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12074086B2 (en) 2019-11-01 2024-08-27 Qorvo Us, Inc. RF devices with nanotube particles for enhanced performance and methods of forming the same
US11646289B2 (en) 2019-12-02 2023-05-09 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11923238B2 (en) 2019-12-12 2024-03-05 Qorvo Us, Inc. Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive
US12129168B2 (en) 2019-12-23 2024-10-29 Qorvo Us, Inc. Microelectronics package with vertically stacked MEMS device and controller device
DE102020209092A1 (de) * 2020-07-21 2022-01-27 Sicrystal Gmbh Kristallstrukturorientierung in Halbleiter-Halbzeugen und Halbleitersubstraten zum Verringern von Sprüngen und Verfahren zum Einstellen von dieser
US12482731B2 (en) 2020-12-11 2025-11-25 Qorvo Us, Inc. Multi-level 3D stacked package and methods of forming the same
WO2022186857A1 (en) 2021-03-05 2022-09-09 Qorvo Us, Inc. Selective etching process for si-ge and doped epitaxial silicon
US20250069945A1 (en) * 2023-08-24 2025-02-27 Globalwafers Co., Ltd. Methods of preparing silicon-on-insulator structures using epitaxial wafers

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06338464A (ja) * 1993-05-31 1994-12-06 Toshiba Corp 半導体装置用基板
CN101151708A (zh) * 2005-04-06 2008-03-26 信越半导体股份有限公司 Soi晶圆制造方法及用该方法制造的soi晶圆
JP2008159667A (ja) * 2006-12-21 2008-07-10 Siltronic Ag Ｓｏｉ基板及びｓｏｉ基板の製造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62226891A (ja) * 1986-03-28 1987-10-05 Shin Etsu Handotai Co Ltd 半導体装置用基板
JPH03194921A (ja) * 1989-12-22 1991-08-26 Showa Denko Kk 半導体エピタキシャルウェハー及びその製造方法
JP2772183B2 (ja) * 1991-11-30 1998-07-02 東芝セラミックス株式会社 シリコンウェハの製造方法
JP2000260711A (ja) * 1999-03-11 2000-09-22 Toshiba Corp 半導体基板製造方法
JP2001274049A (ja) * 2000-03-27 2001-10-05 Toshiba Microelectronics Corp 半導体基板及びその製造方法
US6743495B2 (en) * 2001-03-30 2004-06-01 Memc Electronic Materials, Inc. Thermal annealing process for producing silicon wafers with improved surface characteristics
JP2003204048A (ja) * 2002-01-09 2003-07-18 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ
JP4089354B2 (ja) * 2002-08-30 2008-05-28 株式会社Ｓｕｍｃｏ エピタキシャルウェーハとその製造方法
JP2004339003A (ja) * 2003-05-15 2004-12-02 Shin Etsu Handotai Co Ltd シリコンエピタキシャルウェーハ及びシリコンエピタキシャルウェーハの製造方法
JP4423903B2 (ja) * 2003-07-17 2010-03-03 信越半導体株式会社 シリコンエピタキシャルウェーハ及びその製造方法
JP2008171958A (ja) * 2007-01-10 2008-07-24 Hitachi Kokusai Electric Inc 半導体装置の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06338464A (ja) * 1993-05-31 1994-12-06 Toshiba Corp 半導体装置用基板
CN101151708A (zh) * 2005-04-06 2008-03-26 信越半导体股份有限公司 Soi晶圆制造方法及用该方法制造的soi晶圆
JP2008159667A (ja) * 2006-12-21 2008-07-10 Siltronic Ag Ｓｏｉ基板及びｓｏｉ基板の製造方法

Also Published As

Publication number Publication date
KR20130023207A (ko) 2013-03-07
US8823130B2 (en) 2014-09-02
KR101729474B1 (ko) 2017-04-24
EP2555227B1 (en) 2019-07-03
US20120326268A1 (en) 2012-12-27
CN102859649A (zh) 2013-01-02
EP2555227A4 (en) 2015-08-26
WO2011125282A1 (ja) 2011-10-13
EP2555227A1 (en) 2013-02-06
JP5544986B2 (ja) 2014-07-09
JP2011216780A (ja) 2011-10-27

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