JP5544986B2 - 貼り合わせｓｏｉウェーハの製造方法、及び貼り合わせｓｏｉウェーハ - Google Patents

貼り合わせｓｏｉウェーハの製造方法、及び貼り合わせｓｏｉウェーハ Download PDF

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JP5544986B2
JP5544986B2 JP2010085381A JP2010085381A JP5544986B2 JP 5544986 B2 JP5544986 B2 JP 5544986B2 JP 2010085381 A JP2010085381 A JP 2010085381A JP 2010085381 A JP2010085381 A JP 2010085381A JP 5544986 B2 JP5544986 B2 JP 5544986B2
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wafer
angle
silicon
single crystal
main surface
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Japanese (ja)
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JP2011216780A (ja
JP2011216780A5 (enExample
Inventor
正弘 加藤
哲史 岡
徳弘 小林
徹 石塚
宣彦 能登
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Shin-Etsu Handotai Co Ltd
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Shin-Etsu Handotai Co Ltd
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Priority to JP2010085381A priority Critical patent/JP5544986B2/ja
Application filed by Shin-Etsu Handotai Co Ltd filed Critical Shin-Etsu Handotai Co Ltd
Priority to US13/582,614 priority patent/US8823130B2/en
Priority to CN201180017235.6A priority patent/CN102859649B/zh
Priority to PCT/JP2011/001175 priority patent/WO2011125282A1/ja
Priority to EP11765184.4A priority patent/EP2555227B1/en
Priority to KR1020127024972A priority patent/KR101729474B1/ko
Publication of JP2011216780A publication Critical patent/JP2011216780A/ja
Publication of JP2011216780A5 publication Critical patent/JP2011216780A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2926—Crystal orientations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3438—Doping during depositing
    • H10P14/3441—Conductivity type
    • H10P14/3442—N-type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Recrystallisation Techniques (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
JP2010085381A 2010-04-01 2010-04-01 貼り合わせｓｏｉウェーハの製造方法、及び貼り合わせｓｏｉウェーハ Active JP5544986B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2010085381A JP5544986B2 (ja) 2010-04-01 2010-04-01 貼り合わせｓｏｉウェーハの製造方法、及び貼り合わせｓｏｉウェーハ
CN201180017235.6A CN102859649B (zh) 2010-04-01 2011-03-01 外延硅晶片及其制造方法、以及贴合soi晶片及其制造方法
PCT/JP2011/001175 WO2011125282A1 (ja) 2010-04-01 2011-03-01 シリコンエピタキシャルウェーハ及びその製造方法、並びに貼り合わせｓｏｉウェーハ及びその製造方法
EP11765184.4A EP2555227B1 (en) 2010-04-01 2011-03-01 Bonded soi wafer and method for producing the same
US13/582,614 US8823130B2 (en) 2010-04-01 2011-03-01 Silicon epitaxial wafer, method for manufacturing the same, bonded SOI wafer and method for manufacturing the same
KR1020127024972A KR101729474B1 (ko) 2010-04-01 2011-03-01 접합 ｓｏｉ 웨이퍼의 제조방법 및 접합 ｓｏｉ 웨이퍼

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010085381A JP5544986B2 (ja) 2010-04-01 2010-04-01 貼り合わせｓｏｉウェーハの製造方法、及び貼り合わせｓｏｉウェーハ

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JP2011216780A JP2011216780A (ja) 2011-10-27
JP2011216780A5 JP2011216780A5 (enExample) 2012-10-18
JP5544986B2 true JP5544986B2 (ja) 2014-07-09

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US (1) US8823130B2 (enExample)
EP (1) EP2555227B1 (enExample)
JP (1) JP5544986B2 (enExample)
KR (1) KR101729474B1 (enExample)
CN (1) CN102859649B (enExample)
WO (1) WO2011125282A1 (enExample)

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US20150270344A1 (en) * 2014-03-21 2015-09-24 International Business Machines Corporation P-fet with graded silicon-germanium channel
CN103871902A (zh) 2014-03-24 2014-06-18 上海华力微电子有限公司 半导体处理工艺及半导体器件的制备方法
CN105869991B (zh) 2015-01-23 2018-05-11 上海华力微电子有限公司 用于改善SiGe厚度的均匀性的方法和系统
CN105990172B (zh) 2015-01-30 2018-07-31 上海华力微电子有限公司 嵌入式SiGe外延测试块的设计
CN105990342B (zh) 2015-02-13 2019-07-19 上海华力微电子有限公司 具有用于嵌入锗材料的成形腔的半导体器件及其制造工艺
CN104851884A (zh) 2015-04-14 2015-08-19 上海华力微电子有限公司 用于锗硅填充材料的成形腔
CN104821336B (zh) 2015-04-20 2017-12-12 上海华力微电子有限公司 用于使用保形填充层改善器件表面均匀性的方法和系统
FR3036845B1 (fr) * 2015-05-28 2017-05-26 Soitec Silicon On Insulator Procede de transfert d'une couche d'un substrat monocristallin
CN105097554B (zh) 2015-08-24 2018-12-07 上海华力微电子有限公司 用于减少高浓度外延工艺中的位错缺陷的方法和系统
EP3179093A1 (en) * 2015-12-08 2017-06-14 Winfoor AB Rotor blade for a wind turbine and a sub-member
JP6474048B2 (ja) * 2015-12-25 2019-02-27 信越半導体株式会社 エピタキシャルウェーハの製造方法
WO2018030352A1 (ja) * 2016-08-10 2018-02-15 株式会社Sumco エピタキシャルシリコンウェーハ、および、エピタキシャルシリコンウェーハの製造方法
CN116884928A (zh) * 2016-08-12 2023-10-13 Qorvo美国公司 具有增强性能的晶片级封装
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CN110603350B (zh) * 2017-04-06 2021-07-16 胜高股份有限公司 外延硅晶片的制造方法及外延硅晶片
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US11646242B2 (en) 2018-11-29 2023-05-09 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
US12057374B2 (en) 2019-01-23 2024-08-06 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
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US12046483B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
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US12074086B2 (en) 2019-11-01 2024-08-27 Qorvo Us, Inc. RF devices with nanotube particles for enhanced performance and methods of forming the same
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Publication number Publication date
JP2011216780A (ja) 2011-10-27
KR101729474B1 (ko) 2017-04-24
WO2011125282A1 (ja) 2011-10-13
KR20130023207A (ko) 2013-03-07
US8823130B2 (en) 2014-09-02
EP2555227A4 (en) 2015-08-26
CN102859649A (zh) 2013-01-02
EP2555227A1 (en) 2013-02-06
CN102859649B (zh) 2015-06-24
EP2555227B1 (en) 2019-07-03
US20120326268A1 (en) 2012-12-27

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