CN102651357A - 半导体装置、传感器以及电子设备 - Google Patents

半导体装置、传感器以及电子设备 Download PDF

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CN102651357A
CN102651357A CN2012100342175A CN201210034217A CN102651357A CN 102651357 A CN102651357 A CN 102651357A CN 2012100342175 A CN2012100342175 A CN 2012100342175A CN 201210034217 A CN201210034217 A CN 201210034217A CN 102651357 A CN102651357 A CN 102651357A
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electrode
substrate
semiconductor substrate
recess
semiconductor device
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CN102651357B (zh
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今井英生
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Seiko Epson Corp
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Seiko Epson Corp
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Abstract

本发明提供半导体装置、传感器以及电子设备，该传感器具有该半导体装置。在形成有突起电极的第二基板上层叠形成有贯通电极的第一基板，在贯通电极中具有凹部，突起电极进入并层叠在凹部，突起电极的顶端宽度比凹部的开口宽度小。

Description

半导体装置、传感器以及电子设备
技术领域
本发明涉及半导体装置、以及具有半导体装置的传感器以及电子设备。
背景技术
已知有将形成有贯通电极的半导体基板层叠并通过贯通电极将上下的半导体基板电连接的半导体装置。
在现有技术中，例如，如专利文献1所记载，已知有下述方法，即，在一个半导体基板上设置贯通电极，在另一个半导体基板上设置突起电极，将突起电极压接在贯通孔中使其塑性变形，从而在铆接状态下将上下的半导体基板电连接。
现有技术文献
专利文献
专利文献1：日本专利第4441328号公报
发明内容
发明所要解决的技术问题
但是，在专利文献1所记载的半导体装置中，当将突起电极压接在半导体基板的贯通孔中时，存在在半导体基板上产生裂缝的问题。
解决技术问题的手段
本发明是为了解决至少一部分上述问题的而进行的，能够作为以下的方式或者适用例而实现。
(适用例1)本适用例涉及的半导体装置的特征在于，具备：具有相互位于相反侧的主面以及背面的第一基板、以及层叠于所述第一基板并且具有相互位于相反侧的主面以及背面的第二基板，所述第一基板设有贯通所述第一基板的厚度方向的贯通孔、形成在所述贯通孔的内侧的贯通电极、以及形成在所述主面上的第一电极，所述第二基板设有形成于所述第二基板的所述主面的第二电极、以及配置在所述第二电极上并且从所述第二基板的所述主面突出的突出电极，所述贯通电极在所述背面侧具有凹部，与所述第一基板的所述背面相比，所述凹部的底部的位置位于所述主面侧，所述贯通电极从所述第一基板的所述背面连接于配置在所述主面上的所述第一电极，所述突起电极进入所述凹部，所述第一基板和所述第二基板层叠，所述凹部的开口宽度a和所述突起电极的顶端宽度b形成a＞b的关系。
根据本适用例，由于形成于第二基板的突起电极的顶端宽度比形成于第一基板的凹部的开口宽度小，因此当第一基板和第二基板层叠时，突起电极容易进入凹部，能够以基板不会破损的方式进行连接。
(适用例2)优选在上述适用例记载的半导体装置中，所述第一基板的所述凹部的深度c和所述第二基板的所述突起电极的高度d形成c＜d的关系。
根据本适用例，由于突起电极的高度比凹部的深度高，因此能够适当地保持第一基板和第二基板的间隙，能够提高第一基板和第二基板的连接可靠性。
(适用例3)优选在上述适用例记载的半导体装置中，所述第一基板的所述凹部的开口从所述底部向所述背面变宽。
根据本适用例，由于凹部从底部向背面变宽，因此当层叠时，突起电极更容易进入凹部，当第一基板和第二基板层叠时，能够以基板不会破损的方式进行连接。
(适用例4)优选在上述适用例记载的半导体装置中，在所述第一基板的所述贯通孔的内壁上形成绝缘膜，具有导电层的所述贯通电极在所述绝缘膜的内侧，所述凹部配置在所述导电层中，所述导电层由两种以上的材料形成，所述凹部的所述背面侧的表面的材料由熔点最低的材料形成，所述熔点低的材料和形成于所述第二基板的所述突起电极进行金属间接合。
根据本适用例，由于导电层由两种以上的材料形成，并且凹部的背面侧的表面的材料为熔点最低的材料，因此能够以较低的温度进行与突起电极的金属间接合，并能够降低热应力，由此能够提高第一基板和第二基板的连接可靠性。
(适用例5)优选在上述适用例记载的半导体装置中，所述熔点低的材料为钎料。
根据本适用例，由于使用钎料，所以金属间接合容易进行，由此能够提高第一基板和第二基板的连接可靠性。
(适用例6)优选在上述适用例记载的半导体装置中，形成在所述第二基板的所述第二电极上的所述突起电极的顶端宽度b和所述第二电极侧的所述突起电极的宽度e形成b＜e的关系。
根据本适用例，由于第二电极侧的宽度比突起电极的顶端宽度大，因此即使顶端宽度较窄，也能够提高突起电极的强度，从而能够提高第一基板和第二基板的连接可靠性。
(适用例7)本适用例涉及的传感器的特征在于安装有上述半导体装置。
根据本适用例，由于安装有上述半导体装置，因此能够提供可靠性较高的传感器。
(适用例8)本适用例涉及的电子设备的特征在于具有上述半导体装置。
根据本适用例，由于具有上述半导体装置，因此能够提供可靠性较高的电子设备。
附图说明
图1(A)～(D)是说明实施方式一中的第一基板的制造工序的剖面图。
图2(A)～(C)是说明实施方式一中的第一基板的制造工序的剖面图。
图3是说明实施方式一中的第二基板的制造工序的剖面图。
图4是示出实施方式一中的贯通电极和突起电极的关系的图。
图5是示出将实施方式一中的第一基板和第二基板层叠的状态的图。
图6是示出实施方式二中的半导体基板的层叠状态的图。
图7是示出变形例1中的突起电极的形状的图。
图8是示出将变形例1中的第一基板和第二基板层叠的状态的图。
图9是示出变形例1中的基板的另一层叠状态的图。
图10(A)、(B)是示出实施方式的应用中涉及的传感器的图。
图11是示出实施方式的应用中涉及的电子设备的图。
图12是示出实施方式的应用中涉及的另一电子设备的图。
符号说明
10作为第一基板的半导体基板  14作为第一电极的电极
114作为第二电极的电极       21贯通孔
22绝缘膜                    25、26、225、226导电层
28、228凹部                 30、230钎料层
40、240贯通电极             100作为第二基板的半导体基板
117、118、217、218突起电极
具体实施方式
以下，参照附图对本发明的实施方式进行说明。并且，在以下的各图中，为了使各层和各部件为能够识别程度的大小，各层和各部件的尺度与实际不同。
(实施方式一)
图1(A)～(D)以及图2(A)～(C)是说明本实施方式的第一基板的制造工序的剖面图。图3是说明本实施方式的第二基板的制造工序的剖面图。
在本实施方式中，使用半导体基板10作为第一基板。图1(A)示出的半导体基板10是半导体晶片，也可以是半导体芯片。在半导体基板10上，至少一个(在半导体晶片上为多个，在半导体芯片上为一个)集成电路(例如具有晶体管和存储器的电路(未示出))形成在作为主面的第一面12上。在半导体基板10上，形成多个作为第一电极的电极(例如电极片)14。各电极14与集成电路电连接。各电极14可以由铝(Al)等形成。电极14的表面形状没有特别的限定，为矩形的情况较多。在半导体基板10是半导体晶片的情况下，在形成多个半导体芯片的各区域中形成两个以上(一组)的电极14。
在半导体基板10上，形成一层或一层以上的钝化膜16。钝化膜16例如可以由SiO2、SiN、聚酰亚胺树脂等形成。在覆盖着电极14的表面形成钝化膜16之后，可以将其一部分蚀刻而露出电极14的一部分。在蚀刻中，可以使用干蚀刻以及湿蚀刻的任一种。当进行钝化膜16的蚀刻时，电极14的表面也可以被蚀刻。
在本实施方式中，如图1(A)所示，以从半导体基板10的背面即第二面(与第一面12相反侧的面)20到达电极14上的绝缘层15的方式形成贯通孔21。在贯通孔21的形成中，可以使用蚀刻(干蚀刻或者湿蚀刻)。蚀刻可以在通过平版印刷工序形成图案化的抗蚀层(レジスト)(未示出)之后进行。或者，在贯通孔21的形成中可以使用激光(例如CO2激光、YAG激光等)。绝缘层15例如可以是SiO2或SiN。
接着，如图1(B)所示，在贯通孔21的内表面形成绝缘膜22。绝缘膜22可以是氧化膜。例如，在半导体基板10的基材是Si的情况下，绝缘膜可以是SiO2或SiN，也可以是树脂。第二面20上和贯通孔21的底部(绝缘层15上)也可以形成绝缘膜。
接着，如图1(C)所示，从贯通孔21的底部形成与电极14相连的开口23。开口23可以形成得比贯通孔21小。蚀刻(干蚀刻或者湿蚀刻)可用于开口23的形成。蚀刻可以在通过平版印刷工序在绝缘膜22上形成图案化的抗蚀层(未示出)之后进行。
如图1(D)所示，在贯通孔21上形成导电层25。在导电层25的形成中，可以使用溅射。导电层25可以至少包括阻隔层。阻隔层防止形成在其上的层的材料扩散至半导体基板10(例如Si)。阻隔层例如可以由TiW、TiN形成。第二面20上和贯通孔21的内表面(内侧面以及底部)可以通过导电层形成。导电层25可以含有籽晶层。籽晶层在形成阻隔层之后形成。籽晶层例如由Cu形成。导电层25可以与电极14接触。
接着，如图2(A)所示，以形成凹部28的方式在贯通孔21内形成导电层26。导电层26可以使用导电层25作为籽晶层并通过电解电镀而设置。导电层26例如可以由Cu形成。凹部28可以以开口从底部向第二面20扩大的方式形成。
接着，如图2(B)所示，以不完全将凹部28掩埋的方式在导电层26的表面形成钎料层30。钎料层30可以在导电层25上形成图案化的抗蚀层(未示出)之后将导电层25作为籽晶层并通过电解电镀而进行。或者可以将钎料熔化，通过喷射方式等将其喷出或滴下至凹部28。凹部28可以以开口从底部向第二面20扩大的方式形成。钎料层30例如可以由Sn、Ag、Cu、Zn、In、Bi、Ni、Pb等至少一个或者多个以上的材料构成。钎料采用熔点比导电层25、26低的材料。并且，钎料层30的厚度为2μm～10μm左右。
并且，如图2(C)所示，将形成在半导体基板10的第二面20上的导电层25去除。在导电层25的去除中，可以使用蚀刻(干蚀刻或者湿蚀刻)。
通过以上的工序，能够在作为第一基板的半导体基板10上形成贯通电极40。在图1、图2中示出了一个贯通电极，但是在半导体基板10上具有多个贯通电极40。贯通电极40从第一面(主面)12的电极14贯通至第二面(背面)20。并且，贯通电极40在第二面20侧具有凹部28。凹部28可以以开口从底部向第二面20扩大的方式形成。
图3示出作为第二基板的半导体基板100。半导体基板100是半导体晶片，也可以是半导体芯片。在半导体基板100上，至少一个(在半导体晶片上为多个，在半导体芯片上为一个)集成电路(例如具有晶体管和存储器的电路(未示出))形成于作为主面的第一面112上。在电路上形成绝缘层115。例如在半导体基板100的基材为Si的情况下，绝缘层可以是SiO2或SiN。并且，在半导体基板100上，形成多个作为第二电极的电极(例如电极片)114。各电极114与集成电路电连接。各电极114可以由铝(Al)等形成。电极114的表面形状没有特别的限定，为矩形的情况较多。在半导体基板100是半导体晶片的情况下，在成为多个半导体芯片的各区域中形成两个以上(一组)的电极114。
在半导体基板100上，形成一层或一层以上的钝化膜116。钝化膜116例如可以由SiO2、SiN、聚酰亚胺树脂等形成。可以在覆盖着电极114的表面形成钝化膜16之后，将其一部分蚀刻而使电极114的一部分露出。在蚀刻中，可以使用干蚀刻以及湿蚀刻的任一种。当进行钝化膜116的蚀刻时，电极114的表面也可以被蚀刻。
在露出的电极114上形成突起电极117。突起电极117在半导体基板100的厚度方向上突出而形成圆柱状。突起电极117可以通过电镀(电解电镀/无电解电镀)而设置。突起电极117例如可以由金(Au)形成。
图4是示出本实施方式中贯通电极和突起电极的关系的图。
如图4所示，作为第一基板的半导体基板10的贯通电极40的凹部28的开口宽度a和作为第二基板的半导体基板100的突起电极117的顶端宽度b为a＞b。并且，半导体基板10的贯通电极40的凹部28的深度c和半导体基板100的突起电极117的高度d为c＜d。并且，凹部28的深度c为未包括钎料层30的深度。
如图5所示，使用上述的半导体基板10和半导体基板100，将作为第一基板的半导体基板10层叠于作为第二基板的半导体基板100。此时，半导体基板100的突起电极117进入半导体基板10的贯通电极40的凹部28。由于半导体基板100的突起电极117的顶端宽度b比半导体基板10的贯通电极40的凹部28的开口宽度a狭窄，因此能够容易进入，能够防止基板的破损。并且，凹部28以开口从底部向第二面20扩大的方式形成。由此，能够使半导体基板100的突起电极117容易进入半导体基板10的凹部28。
半导体基板10的钎料层30和半导体基板100的突起电极117可以进行金属间接合。这样，制造了半导体装置5。
由于钎料层30比半导体基板10的导电层25、26的熔点低，因此能够以较低的温度进行接合，并且能够容易地进行金属间接合，由于这样能够降低应力，从而能够提高半导体基板间的连接可靠性。
并且，由于半导体基板100的突起电极117的高度d比半导体基板10的贯通电极40的凹部28的深度c高，因此能够适当地保持半导体基板10和半导体基板100的间隙，能够提高连接可靠性。并且，也可以在半导体基板10和半导体基板100之间(半导体基板10的第二面20和半导体基板100的第一面112之间)填充密封树脂(未示出)。
如上所述，根据本实施方式，能够得到以下的效果。
将作为第一基板的半导体基板10层叠于作为第二基板的半导体基板100。此时，半导体基板100的突起电极117进入半导体基板10的贯通电极40的凹部28，但是由于半导体基板100的突起电极117的顶端宽度b比半导体基板10的贯通电极40的凹部28的开口宽度a狭窄，因此能够容易进入，能够防止半导体基板10、100的破损。凹部28以从底部向开口扩大的方式形成，因此能够使半导体基板100的突起电极117容易进入半导体基板10的凹部28。并且由于半导体基板100的突起电极117的高度d比半导体基板10的贯通电极40的凹部28的深度c高，因此能够适当地保持半导体基板10和半导体基板100的间隙，能够提高连接可靠性。
(实施方式二)
图6是示出实施方式二涉及的半导体基板的层叠状态的图。
参照该图对本实施方式涉及的半导体装置进行说明。并且，对与实施方式一相同的构成部位使用相同的标号，并省略重复的说明。
在本实施方式中，在作为第一基板的半导体基板10和作为第二基板的半导体基板100之间，层叠作为第三基板的半导体基板200。
半导体基板200具有贯通电极240，其构成与半导体基板10的贯通电极40相同。在半导体基板200的电极214上，形成一层或者一层以上的钝化膜216。钝化膜216例如可以由SiO2、SiN、聚酰亚胺树脂等形成。可以在覆盖着电极214的表面形成钝化膜216之后，将其一部分蚀刻而使电极214的一部分露出。在蚀刻中，可以使用干蚀刻以及湿蚀刻的任一种。当进行钝化膜216的蚀刻时，电极214的表面也可以被蚀刻。
在露出的电极214上形成突起电极217。突起电极217可以通过电镀(电解电镀/无电解电镀)而设置。突起电极217例如可以由金(Au)形成。
在半导体基板200的贯通电极240上具有凹部228，半导体基板100的突起电极117进入凹部228。半导体基板200的突起电极217进入半导体基板10的贯通电极40的凹部28中。由于半导体基板100的突起电极117的顶端宽度比半导体基板200的贯通电极240的凹部228的开口宽度狭窄，因此能够容易进入，能够防止半导体基板的破损。并且凹部228、凹部28可以以从底部向开口扩大的方式形成。因此，半导体基板100的突起电极117能够容易地进入半导体基板200的凹部228，半导体基板200的突起电极217能够容易地进入半导体基板10的凹部28。
半导体基板10的钎料层30和半导体基板200的突起电极217、半导体基板20的钎料层230和半导体基板100的突起电极117分别可以进行金属间接合。这样，制造了半导体装置6。
由于钎料层30比半导体基板10的导电层25、26的熔点低，并且钎料层230比半导体基板200的导电层225、226的熔点低，因此能够以较低的温度进行接合，能够容易地进行金属间接合，由于这样能够降低应力，从而能够提高连接可靠性。
并且，由于半导体基板200的突起电极217的高度比半导体基板10的贯通电极40的凹部28的深度高，并且半导体基板100的突起电极117的高度比半导体基板200的贯通电极240的凹部228的深度高，因此能够适当地保持半导体基板10和半导体基板200的间隙、以及半导体基板200和半导体基板100的间隙，能够提高连接可靠性。也可以在半导体基板10和半导体基板200之间、以及半导体基板200和半导体基板100之间分别填充密封树脂(未示出)。
如上所述，根据本实施方式，除了实施方式一的效果以外，能够得到以下的效果。
将作为第三基板的半导体基板200层叠于作为第二基板的半导体基板100，并将作为第一基板的半导体基板10层叠于半导体基板200。此时，由于半导体基板200的突起电极217的顶端宽度比半导体基板10的贯通电极40的凹部28的开口宽度狭窄，并且半导体基板100的突起电极117的顶端宽度比半导体基板200的贯通电极240的凹部228的开口宽度狭窄，因此能够容易地进入，即使层叠数比实施方式一多，也能够防止半导体基板10、100、200的破损。与凹部28相同，凹部228以从底部向开口扩大的方式形成，因此半导体基板100的突起电极117能够容易地进入半导体基板200的凹部228，半导体基板200的突起电极217能够容易地进入半导体基板10的凹部28。并且由于半导体基板200的突起电极217的高度比半导体基板10的贯通电极40的凹部28的深度高，并且半导体基板100的突起电极117的高度比半导体基板200的贯通电极240的凹部228的深度高，因此能够适当地保持半导体基板10和半导体基板200的间隙、以及半导体基板200和半导体基板100的间隙，能够提高半导体基板间连接可靠性。
并且，本发明并不限定于上述的实施方式，可以在上述实施方式中加入各种变更和改良等。变形例在下面描述。
(变形例1)
图7、图8、图9是变形例1涉及的图。以下，对变形例1进行说明。并且，对与实施方式一、二相同的构成部位标记相同的标号，并省略重复的说明。
图7、图8为实施方式一的变形例。
半导体基板100的突起电极118的顶端宽度b和电极114侧的宽度e的关系为b＜a。在本实施方式中，突起电极118形成圆锥台形形状。由于电极114侧的宽度e比较大，即使顶端宽度较细，也能够提高突起电极相对于半导体基板100的强度，从而能够提高半导体基板间的连接可靠性。
如图8所示，在半导体装置7中，形成有贯通电极40的半导体基板10层叠于形成有突起电极118的半导体基板100。相对于突起电极118的电极114侧的宽度，顶端宽度较小，半导体基板100的突起电极118的顶端宽度相对于贯通电极40的凹部28的开口宽度足够狭窄，因此能够容易进入，能够防止基板的破损。并且，由于凹部28以开口从底部向第二面20扩大的方式形成，因此能够使半导体基板100的突起电极118容易地进入半导体基板10的凹部28。半导体基板10的钎料层30和半导体基板100的突起电极118可以进行金属间接合。
由于半导体基板100的突起电极118的高度比半导体基板10的贯通电极40的凹部28的深度高，因此能够适当地保持半导体基板10和半导体基板100的间隙，能够提高连接可靠性。也可以在半导体基板10和半导体基板100之间(半导体基板10的第二面20和半导体基板100的第一面112之间)填充密封树脂(未示出)。
图9是实施方式二的变形例。在半导体装置8中，除了半导体基板100的突起电极118外，半导体基板200的突起电极218也是顶端宽度比电极214侧的宽度小。半导体基板10的钎料层30和半导体基板200的突起电极218、以及半导体基板200的钎料层230和半导体基板100的突起电极118分别可以进行金属间接合。也可以在半导体基板10和半导体基板200之间、以及半导体基板200和半导体基板100之间分别填充密封树脂(未示出)。
如上所述，根据本变形例，除了实施方式一、二的效果外，能够得到以下的效果。
由于突起电极的顶端宽度相对于贯通电极的凹部的开口宽度逐渐变细并且足够狭窄，因此能够容易进入，能够防止基板的破损。并且，由于凹部以从底部向开口扩大的方式形成，因此能够使突起电极容易地进入半导体基板的凹部。
图10示出了安装了本发明的半导体装置的传感器300。
图10(A)示出传感器300的构成例。该传感器包括传感器阵列310、行选择电路(行驱动器)320以及读出电路330。并且，可以包括A/D变换部340以及控制电路350。通过使用该传感器，例如能够实现在夜视仪等中使用的红外线照相机等。
在传感器阵列310上，在两轴方向上排列(配置)多个传感器单元。并且设置多个行线(字线，扫描线)和多个列线(数据线)。并且行线以及列线中一者的条数可以是一条。例如在行线为一条的情况下，在图10(A)中，在沿行线的方向(横向)上排列多个传感器单元。另一方面，在列线为一条的情况下，在沿列线的方向(纵向)上排列多个传感器单元。
如图10(B)所示，传感器阵列310的各传感器单元配置(形成)在与各行线和各列线的交叉位置相对应之处。例如图10(B)的传感器单元配置在与行线WL1和列线DL1的交叉位置相对应之处。其他的传感器单元也同样。行选择电路320连接于一条或者多条行线。并且进行各行线的选择操作。例如，如果以如图10(B)的QVGA(320×240像素)的传感器阵列310(焦平面阵列)为例，进行依次选择(扫描)行线WL0、WL1、WL2····WL239的操作。即，将选择这些行线的信号(字选择信号)输出至传感器阵列310。
读出电路330连接于一条或者多条列线。并且进行各列线的读出操作。如果以QVGA的传感器阵列310为例，进行读出来自列线DL0、DL1、DL2····DL319的检测信号(检测电流，检测电荷)的操作。
A/D变换部340进行将在读出电路330中取得的检测电压(测定电压，到达电压)A/D变换为数字数据的处理。并且将A/D变换后的数字数据DOUT输出。具体来说，在A/D变换部340中，对应于多条列线的各列线设置各A/D变换器。并且，各A/D变换器在对应的列线中进行通过读出电路330取得的检测电压的A/D变换处理。并且，也可以对应于多条列线设置一个A/D变换器，并使用该一个A/D变换器将多条列线的检测电压分时进行A/D变换。
控制电路350(定时生成电路)生成各种控制信号，并输出至行选择电路320、读出电路330、A/D变换部340。例如生成充电和放电(复位)的控制信号并输出。或者，生成控制各电路的定时的信号并输出。
作为本发明涉及的电子设备的一例，可以列举出图11所示的个人计算机400以及图12所示的便携式电话500等。其特征在于安装任一上述实施方式中示出的半导体装置作为内部设备。
本发明不受上述实施方式的限制，可以进行各种变形。例如，本发明包括与实施方式中说明的构成实质上相同的构成(例如功能、方法和结果相同的构成或目的和结果相同的构成)。并且，本发明包括将在实施方式中说明的构成的非实质部分替换后的构成。并且，本发明包括与在实施方式中说明的构成发挥相同的作用效果的构成或能够达到相同的目的的构成。并且，本发明包括在实施方式中说明的构成上添加公知技术后的构成。

Claims (18)

1.一种半导体装置，其特征在于，具备：
第一基板，所述第一基板具有形成在第一面上的第一电极以及形成在从所述第一面的反面、即第二面到达所述第一电极的孔中的贯通电极；以及
第二基板，所述第二基板具有连接于所述贯通电极的突起电极；
所述贯通电极在所述第二面侧具有凹部，所述凹部的底部位于所述第一基板的所述第一面和所述第二面之间，
所述突起电极进入所述凹部，
所述凹部的开口宽度a和所述突起电极的顶端宽度b形成a＞b的关系。
2.根据权利要求1所述的半导体装置，其特征在于，所述第一基板的所述凹部的深度c和所述第二基板的所述突起电极的高度d形成c＜d的关系。
3.根据权利要求1所述的半导体装置，其特征在于，所述第一基板的所述凹部的开口从所述底部向所述第二面变宽。
4.根据权利要求1所述的半导体装置，其特征在于，
所述贯通电极由两种以上的材料形成，所述凹部的表面的材料由所述两种以上的材料中熔点最低的材料形成，
所述熔点最低的材料和所述突起电极进行金属间接合。
5.根据权利要求4所述的半导体装置，其特征在于，所述熔点最低的材料为钎料。
6.根据权利要求1所述的半导体装置，其特征在于，形成在所述第二基板上的所述突起电极的顶端宽度b和所述突起电极的底端宽度e形成b＜e的关系。
7.根据权利要求1所述的半导体装置，其特征在于，
所述第一面被钝化膜覆盖，
所述第一电极的一部分从所述钝化膜露出，从所述钝化膜露出的所述第一电极的一部分的表面被蚀刻。
8.一种传感器，其特征在于，所述传感器通过安装有根据权利要求1所述的半导体装置而形成。
9.一种电子设备，其特征在于，所述电子设备具有根据权利要求1所述的半导体装置。
10.一种电子设备，其特征在于，所述电子设备具有根据权利要求8所述的传感器。
11.一种半导体装置，其特征在于，具有：
第一基板，所述第一基板具有形成有第一电极的第一面以及作为所述第一面的反面的第二面；
第二基板，所述第二基板层叠于所述第一基板；
贯通电极，所述贯通电极形成在从所述第一基板的所述第二面到达所述第一电极的孔的内侧；以及
突起电极，所述突起电极从所述第二基板突出，
所述贯通电极在所述第二面侧具有凹部，所述凹部的底部位于所述第一基板的所述第一面和所述第二面之间，
通过所述突起电极进入所述凹部，所述第一基板和所述第二基板层叠在一起，
所述凹部的开口宽度a和所述突起电极的顶端宽度b形成a＞b的关系。
12.根据权利要求11所述的半导体装置，其特征在于，所述第一基板的所述凹部的深度c和所述第二基板的所述突起电极的高度d形成c＜d的关系。
13.根据权利要求11所述的半导体装置，其特征在于，所述第一基板的所述凹部的开口从所述底部向所述第二面变宽。
14.根据权利要求11所述的半导体装置，其特征在于，形成在所述第二基板上的所述突起电极的顶端宽度b和所述突起电极的底端宽度e形成b＜e的关系。
15.根据权利要求11所述的半导体装置，其特征在于，
所述第一面被钝化膜覆盖，
所述第一电极的一部分从所述钝化膜露出，从所述钝化膜露出的所述第一电极的一部分的表面被蚀刻。
16.一种传感器，其特征在于，所述传感器通过安装有根据权利要求11所述的半导体装置而形成。
17.一种电子设备，其特征在于，所述电子设备具有根据权利要求11所述的半导体装置。
18.一种电子设备，其特征在于，所述电子设备具有根据权利要求16所述的传感器。
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