CN102315213A - 多鳍式静态随机存取存储器单元的布局 - Google Patents
多鳍式静态随机存取存储器单元的布局 Download PDFInfo
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Abstract
本发明提供一种多鳍式静态随机存取存储器(SRAM)单元的布局。该SRAM单元包括半导体基底上的多个鳍式有源区,其中鳍式有源区包括一对相邻且具有第一间隔的鳍式有源区以及与相邻鳍式有源区间具有第二间隔的一鳍式有源区,该第二间隔大于该第一间隔;多个鳍式场效应晶体管,其形成于鳍式有源区上,其配置为交叉耦合的第一和第二反相器以存储数据,以及存取数据的至少一端口;第一接触窗,其配置于第一和第二鳍式有源区之间并同时电气接触该第一和第二鳍式有源区;以及一第二接触窗,其配置于并电气接触第三鳍式有源区。本发明可缩减第一鳍式有源区的第一类型接触窗、第二鳍式有源区的第二类型接触窗以及SRAM单元面积,同时改进和保持SRAM单元的功能性和效能。
Description
技术领域
本揭露涉及静态随机存取存储器单元,且特别涉及一种多鳍式静态随机存取存储器单元。
背景技术
在深次微米集成电路技术中,嵌入式静态随机存取存储器(static randomaccess memory,以下简称为SRAM)装置成为高速通信、图像处理和单芯片系统(system-on-chip,简称为SOC)产品中存储单元的热门选择。微处理器和单芯片系统产品中的嵌入式SRAM数量须增加以符合各个新技术世代的性能需求。随着硅技术持续改变尺寸的大小,最小几何尺寸的基体平面晶体管中本质临界电压(Vt)也跟着变化,并造成互补金属氧化物半导体(CMOS)SRAM单元的静态噪声边际(static noise margin,以下简称为SNM)缩减。这种不断变小的晶体管几何尺寸所造成的SNM缩减并非想要的结果。随着电压Vcc改变至较低的电压大小,SNM会更进一步缩减。
为了解决SRAM的问题并且进一步改善单元缩小能力,在一些应用中经常考虑使用鳍式场效应晶体管(FinFET)装置。FinFET同时提供速度和装置稳定度。FinFET具有与顶端表面和相对的侧边结合的沟道(称为鳍式沟道)。借由额外的侧边装置宽度(离子效能)和更好的短沟道控制(次临界漏电)可改善上述问题。在FinFET单元装置中,单一鳍式单元装置的设定会遇到单元比率问题,例如β比(βratio,定义为Ipd/Ipg)或α比(αratio,定义为Ipu/Ipg)。单元稳定度的其中一个重要参数为β比,β比的定义为下拉晶体管驱动电流和沟道栅晶体管驱动电流之间的比值。为了改进SRAM单元的稳定度因此需要高于1的高β比。SRAM单元电压Vcc_min为与写入能力相关的因素。相对应的参数为上拉晶体管驱动电流和沟道栅晶体管驱动电流之间的比值,称为α比。因此,为了增加在特定单元面积内的电流,必须将鳍状物之间的间距最小化。遗憾的是,由于现有微影技术的基本限制(例如间距紧密的鳍状物节点之间的连接与接触须符合接触窗空间规则),FinFET装置内间距的进一步缩小是很难达成的。
因此,需要新的SRAM单元结构和方法以处理有关高阶单元应用和改进具有多个鳍状物的单元的尺寸的这些考虑。
发明内容
为克服上述现有技术的缺陷,本揭露提供一静态随机存取存储器(staticrandom access memory,以下简称为SRAM)单元。该SRAM单元包括多个鳍式有源区,其形成于一半导体基底上,其中所述多个鳍式有源区包括第一鳍式有源区和第二鳍式有源区,其之间具有第一间隔,以及与相邻鳍式有源区间具有第二间隔的第三鳍式有源区,该第二间隔大于该第一间隔;多个鳍式场效应晶体管(FinFET),其形成于所述多个鳍式有源区之上,其中所述多个鳍式场效应晶体管配置为构成交叉耦合的第一反相器和第二反相器以存储数据,以及至少一端口以存取数据;一第一接触窗,其配置于该第一鳍式有源区和该第二鳍式有源区之间,并电气接触该第一和第二鳍式有源区;以及一第二接触窗,其配置于该第三鳍式有源区并电气接触该第三鳍式有源区。
本揭露同时提供一半导体结构的一实施例。该半导体结构包括一第一鳍式有源区和一第二鳍式有源区,其从一半导体基底延伸并且彼此相距一第一距离;一第三鳍式有源区和一第四鳍式有源区,其从该半导体基底延伸并且彼此相距大于该第一距离的一第二距离;一第一外延特征物和一第二外延特征物,其分别形成于该第一鳍式有源区与该第二鳍式有源区之上,其中该第一外延特征物和该第二外延特征物横向结合;一第三外延特征物和一第四外延特征物,其分别形成于该第三鳍式有源区与该第四鳍式有源区之上,其中该第三外延特征物和该第四外延特征物彼此分开;一第一接触窗,其配置于结合的该第一外延特征物和该第二外延特征物之上;以及一第二接触窗,其配置于该第三外延特征物之上,其中该第二接触窗与该第四外延特征物间隔排列并且没有电气连接至该第四鳍式有源区。
本揭露还提供SRAM单元的另一实施例。该SRAM单元包括一第一反相器,其包括一第一上拉晶体管(PU-1)、一第一下拉晶体管(PD-1)和一第二下拉晶体管(PD-2);一第二反相器,其包括一第二上拉晶体管(PU-2)、一第三下拉晶体管(PD-3)和一第四下拉晶体管(PD-4),该第二反相器与该第一反相器交叉耦合以存储数据;一端口,其包括一第一沟道栅晶体管(PG-1)和一第二沟道栅晶体管(PG-2),该端口与该第一反相器和该第二反相器耦合以存取数据,其中每个下拉晶体管和沟道栅晶体管包括一n型鳍式场效应晶体管(nFinFET)且每个上拉晶体管包括一p型鳍式场效应晶体管(pFinFET);一第一鳍式有源区和一第二鳍式有源区,其分别具有一第一硅外延特征物和一第二硅外延特征物,其中该第一硅外延特征物和该第二硅外延特征物结合,且该第一下拉晶体管和该第二下拉晶体管分别形成于该第一鳍式有源区和该第二鳍式有源区之上;以及一硅化物特征物,其形成于结合的该第一硅外延特征物和该第二硅外延特征物之上,并将该第一下拉晶体管的源极区和该第二下拉晶体管的源极区电气连接。
在一例子中,借由以较小间隔实施第一鳍式有源区并以较大间隔实施第二鳍式有源区,可缩减第一鳍式有源区的第一类型接触窗、第二鳍式有源区的第二类型接触窗以及SRAM单元面积,而同时可以改进和保持SRAM单元的功能性和效能。
附图说明
图1到图4为根据本揭露中各实施例所绘制的SRAM装置的一部分的剖面图;
图5到图7为根据本揭露中各实施例所绘制的SRAM装置或其中一部分的俯视图;
图8到图15为根据本揭露中各实施例所绘制的SRAM装置的一部分的剖面图;
图16为根据本揭露中一实施例所绘制的SRAM装置的示意图。
其中,附图标记说明如下:
50、80、100、120、130、146、148、150、152、154、158、160、162~半导体结构;
52、82~半导体基底;
54~绝缘特征物;
56、58、88、90、104、106、108、110、136a-136e、156a-156c、160a-160c~鳍式有源区;
60、92~栅极介电质层;
62、94~栅极电极;
64、66、96、98~区;
84~介电质层;
86~半导体层;
112~层间介电质;
114、116、126、128、140a-140g~接触窗;
122、122a-122d~外延特征物;
124~界面;
132~n阱区;
134~p阱区;
138~栅极;
142a-142f~金属线;
170~SRAM单元;
D1、D2、D3、S1、S2、S3~鳍式有源区间距;
BL、BLB~位线;
PD-1、PD-2~下拉装置;
PG-1、PG-2~沟道栅装置;
PU-1、PU-2~上拉装置;
Vcc、Vss~电源线;
WL~字线。
具体实施方式
本发明的各实施例能借由同时阅读下列详细叙述与相对应的附图而更加理解。须强调的是,附图中各种不同的特征物并未如工业标准作法一样按照比例绘制。事实上,为了清楚说明,附图中各种不同特征物的尺寸会放大或缩小以便于理解。
须了解的是,下列揭露提供很多不同的实施例或范例以实现各实施例的不同特征。组成元件和配置的特定范例是在下列叙述简化本揭露。这些范例当然只是举例,并且不应视为限制。此外,本揭露可能在不同范例中重复使用参考标号和/或符号。此重复是为了简化和明确性,并非意指在所讨论的不同实施例和/或结构之间存在特定关系。
图1为根据本揭露所绘制的半导体结构50的剖面图,该半导体结构50为SRAM单元的一部分。半导体结构50包括半导体基底52。半导体基底52包括硅,或者半导体基底52包括锗、锗化硅或其他合适的半导体材料。半导体基底52包括各绝缘特征物54。绝缘特征物为形成于基底中的浅沟槽绝缘(shallow trench isolation,STI)以分隔各装置。半导体基底也包括各掺杂区例如n阱区和p阱区。半导体结构50包括各鳍式有源区56和58。将鳍式有源区56和58定向为平行。鳍式有源区和浅沟槽绝缘特征物可以在一工艺形成,该工艺包括在半导体基底52中形成沟槽并在沟槽中部分填入介电质材料,或者在沟槽中完全填入介电质材料。接着是抛光工艺,例如使用化学机械抛光(CMP)工艺以除去过多的介电质材料并使表面平坦化。之后,使用选择性蚀刻例如氢氟酸(HF)湿蚀刻,将已形成的浅沟槽绝缘特征物部分移去以形成鳍式有源区。尤其,制造程序包括在半导体基底52中蚀刻沟槽并且以一种或多种介电质材料例如氧化硅、氮化硅、氮氧化硅或上列三者的组合来填入沟槽。已填充的沟槽可具有多层结构,例如以具有氮化硅的热氧化衬层填入沟槽。在本实施例的更进一步中,使用一制造程序来形成浅沟槽绝缘特征物,此制造程序包括例如:成长一垫氧化层;形成一低压化学气相沉积(LPCVD)的氮化物层;使用光致抗蚀剂和掩模图案化浅沟槽绝缘开口、蚀刻基底上的沟槽;选择性成长热氧化沟槽衬以改进沟槽界面;以化学气相沉积氧化物填入沟槽;使用化学机械平坦化(CMP)以蚀刻背部;以及使用氮化物剥离以保留浅沟槽结构。半导体基底52也包括形成于各鳍式有源区的各n阱区和p阱区。
各栅极更进一步形成于鳍式有源区之上。栅极特征物包括栅极介电质层60(例如氧化硅)和配置于该栅极介电质层60之上的栅极电极62(例如掺杂的多晶硅)。在另一实施例中,栅极特征物选择性地或附加地包括其他适合电路效能和集成制造的材料。举例而言,栅极介电质层包括高介电常数的介电质材料层。栅极电极包括金属,例如铝、铜、钨或其他适合的导电材料。在另一实施例中,栅极电极包括一金属其具有适合相关联的FinFET的工作函数。对包括高介电常数的介电质材料和金属的栅极堆叠而言,栅极可借由栅极最后(gate-last)工艺或高介电常数最后(high-k-last)工艺(完整的栅极最后工艺)形成。在本实施例中,为了说明,半导体结构50包括一个或多个FinFET的第一区64以及一个或多个FinFET的第二区66。
图2为半导体结构80的剖面图的另一实施例,该半导体结构80为SRAM单元的一部分。半导体结构80包括半导体基底82。半导体基底82包括硅,或者半导体基底82包括锗、锗化硅或其他合适的半导体材料。半导体结构80包括形成于半导体基底82之上的介电质层84以供绝缘。在一例子中,介电质层84包括氧化硅。半导体结构80包括形成于介电质层84之上的另一半导体层86,例如硅,该半导体层86称为绝缘层上半导体(semiconductor oninsulator,SOI)。绝缘层上半导体结构可借由适合的技术形成,例如氧注入隔离(separation by implanted oxygen,SIMOX)或晶片结合以将介电质层包括在半导体材料内部。
图案化半导体层86以形成鳍式有源区88和90。鳍式有源区88和90配置为并定向为互相平行。鳍式有源区88和90以及浅沟槽绝缘特征物可在一制造程序中形成,该制造程序包括形成图案化掩模层于半导体层上并且通过图案化掩模层的开口蚀刻半导体层。图案化掩模层可为图案化的光致抗蚀剂层或图案化的硬掩模层,例如图案化的氮化硅层。
各栅极更进一步形成于鳍式有源区之上。栅极特征物包括栅极介电质层92(例如氧化硅)和配置于栅极介电质层92之上的栅极电极94(例如掺杂多晶硅)。在一实施例中,栅极介电质层92包括高介电常数的介电质材料层。栅极电极94包括金属,例如铝、铜、钨或其他适合的导电材料。在本实施例中,为了说明,半导体结构80包括一个或多个FinFET的第一区96以及一个或多个FinFET的第二区98。
在一实施例中,形成包括沟道栅和下拉装置的SRAM单元的制造流程具有下列步骤:形成鳍式有源区;形成阱区;形成栅极;外延成长;形成轻掺杂漏极(LDD);形成袋注入(袋形结);形成栅极间隙壁;形成源极/漏极(S/D)掺杂;形成层间介电质(ILD);栅极取代;形成接触窗洞;形成硅化物并且形成接触窗。
图3为根据本揭露所绘制的半导体结构100的剖面图,该半导体结构100具有各FinFET和接触窗。半导体结构100为SRAM单元的一部分。半导体结构100包括半导体基底52和绝缘特征物54,其类似于图1的半导体基底52和绝缘特征物54。半导体结构100包括各鳍式有源区104、106、108和110,其在组成和形成方面类似于图1的鳍式有源区56和58。在鳍式有源区104、106、108和110中,相邻鳍式有源区之间配置不同的间隔(或距离)。在本实施例中,鳍式有源区104和106配置为具有第一间隔D1。鳍式有源区108配置为与相邻鳍式有源区106和110之间具有第二间隔D2。第二间隔D2大于第一间隔D1。第一间隔D1和第二间隔D2分别称为窄间隔和宽间隔。半导体结构100更进一步包括配置于鳍式有源区和绝缘特征物之上的层间介电质(ILD)112。层间介电质112包括一个或多个介电质材料以提供互连结构的绝缘。在一实施例中,层间介电质112包括借由化学气相沉积(CVD)形成的氧化硅。在另一实施例中,层间介电质112包括低介电常数的介电质材料,例如介电常数低于大约3.5。在另一实施例中,层间介电质112包括二氧化硅、氮化硅、氮氧化硅、聚酰亚胺、旋涂式玻璃(spin-on glass,SOG)、氟掺杂硅玻璃(FSG)、碳掺杂硅玻璃、Black Diamond(Applied Materials ofSanta Clara,California)、干凝胶、气凝胶、氟化非晶系碳、对二甲苯、双苯并环丁烯(BCB)、SiLK(DOW Chemical,Midland,Michigan)和/或其他合适的材料。层间介电质112可借由一技术形成,该技术包括旋涂、化学气相沉积、溅镀或其他适合的工艺。
半导体结构100更进一步包括在层间介电质112内形成的各接触窗,其配置为提供电气布线。接触窗为垂直的导电特征物,其用来将源极、漏极和栅极电极电气连接至金属线。接触窗为配线中多层互连的一部分。在本实施例中,各接触窗和其他互连特征物配置为形成SRAM单元。设计第一接触窗114为合适的几何尺寸并且配置为同时电气接触鳍式有源区104和106。在一实施例中,接触窗114配置为同时电气接触鳍式有源区104上的第一FinFET的源极和鳍式有源区106上的第二FinFET的源极。在本实施例中,第一和第二FinFET两者皆是配置为并联的下拉装置:源极连接至电源线Vss,以及漏极互相连接(漏极更如同SRAM单元的一反相器一样耦接至相关联的上拉装置的漏极)。既然此二FinFET的源极设计为适用相同电压(并且此二FinFET的漏极设计为互相耦接),鳍式有源区104和106被设计为具有较小的间隔D1以缩减单元尺寸。半导体结构100也包括第二接触窗116,其设计为并配置为着陆于鳍式有源区108并只电气连接至鳍式有源区108。在一实施例中,第二接触窗116配置为电气接触鳍式有源区108上的第三FinFET的源极。为了避免对准偏移所造成的任何电气故障,相邻的鳍式有源区106和108被设计为具有较大的间隔D2,该较大的间隔D2具有根据制造能力所决定的足够边限。由于制造能力包括微影图案化,相邻鳍式有源区之间间隔的缩减受制造能力所限制。
各接触窗(例如接触窗114和116)的形成包括形成在层间介电质112中的接触窗洞并且以导电材料填入接触窗洞。接触窗洞可借由微影工艺和蚀刻工艺形成,例如电浆干蚀刻。在微影工艺中,图案化的光致抗蚀剂层形成于层间介电质112之上,该图案化的光致抗蚀剂层具有定义接触窗洞区域的各开口。将图案化的光致抗蚀剂层当作蚀刻掩模层以在层间介电质112实施蚀刻工艺来形成接触窗洞。或者,利用图案化的光致抗蚀剂层以及通过图案化的硬掩模层的开口实施于层间介电质112的蚀刻工艺形成硬掩模。接触窗洞的填充包括沉积工艺以在接触窗洞中形成一种或多种导电材料。沉积工艺可包括化学气相沉积、溅镀、电镀或上述三者的组合。接下来可实行化学机械抛光(CMP)工艺以除去过多的导电材料并使表面平坦化。在一实施例中,各接触窗的形成包括利用微影工艺形成图案化的光致抗蚀剂层;蚀刻层间介电质112以形成接触窗洞;在接触窗洞中形成导电材料;以及在层间介电质执行化学机械抛光。
接触窗和其他互连特征物包括介层窗和金属线以形成将FinFET电气配置至功能电路的互连结构,其中该功能电路的例子为SRAM单元或SRAM阵列。在一实施例中,使用钨来形成接触窗洞中的钨插塞。在另一实施例中,填入接触窗洞中的导电材料包括钨、铝、铜、其他合适金属或上述的组合。在另一实施例中,接触窗更进一步包括在以导电材料填入接触窗洞之前于接触窗侧壁上形成的阻隔层。举例来说,氮化钛可借由溅镀在接触窗的侧壁上沉积。
在另一实施例中,硅化物特征物形成于接触窗和鳍式有源区之间以减少接触阻抗。特别是,硅化物材料形成于接触窗洞的底部并且在接触窗洞的范围内直接配置在鳍式有源区上。在一例子中,硅化物特征物借由所属领域称作自动对准硅化(salicide)的工艺来形成。在自动对准硅化技术的一实施例中,金属层首先沉积在半导体结构100上。该金属层直接接触在接触窗洞范围内的鳍式有源区的硅上。接着在半导体结构100执行合适温度的退火程序以使金属层和鳍式有源区的硅进行反应以形成硅化物。退火程序后没有反应的金属可从接触窗内移除。用来形成硅化物的金属材料包括各实施例中的钛、镍、钴、铂、钯、钨、钽或铒。在另一实施例中,形成接触窗的方法包括借由微影工艺来形成图案化的光致抗蚀剂层;蚀刻层间介电质112以形成接触窗洞;在接触窗洞范围内的鳍式有源区上形成硅化物;在接触窗洞内形成导电材料;以及在层间介电质执行化学机械抛光工艺。在另一实施例中,硅化物包括钛(Ti)、钴(Co)、镍(Ni)、钼(Mo)、铂(Pt)或上述的组合。
其它工艺步骤可在接触窗形成之前、之间和/或之后执行。举例而言,多层互连更进一步在各接触窗的形成之后形成。多层互连包括垂直互连,例如传统介层窗加上接触窗和包括金属线的水平互连。各互连特征物可以导电材料包括铜、铝、钨和硅化物执行。在一例子中,使用镶嵌工艺以形成与铜相关的多层互连结构。
在半导体结构100中,SRAM单元包括多个具有不同间隔或间距的鳍式有源区。这些多个鳍式有源区的间距定义为从一鳍式有源区到另一鳍式有源区的量度。此外,半导体结构100包括二种接触窗,第一种接触窗设计为电气接触具有较小间隔的二相邻鳍式有源区,例如第一间隔D1。第二种接触窗设计为只电气接触一鳍式有源区,其与相邻鳍式有源区间具有较大间隔(例如第一间隔D2)。借由实施上述具有不同间隔的多个鳍式有源区以及根据相对应的间隔而与鳍式有源区配置的二种接触窗,SRAM单元更进一步缩减单元面积并且改进单元品质,例如在现有技术所讨论过与提过的各种问题。
图4为根据另一实施例中本揭露所绘制的半导体结构120的剖面图,该半导体结构120具有各种FinFET和接触窗。半导体结构120为SRAM单元的一部分。半导体结构120包括半导体基底52和绝缘特征物54,其类似于图3中半导体结构100的半导体基底52和绝缘特征物54。半导体结构120包括各鳍式有源区104、106、108和110。鳍式有源区104、106、108和110包括从基底52延伸的第一部分和形成于第一部分之上的第二部分,如外延特征物122。在本实施例中,外延特征物122包括分别形成于鳍式有源区104、106、108和110之上的外延特征物122a、122b、122c和122d。界面124形成于外延特征物122和鳍式有源区的第一部分之间。在一实施例中,鳍式有源区的第一部分和外延特征物包括相同的半导体材料,例如硅。在另一实施例中,鳍式有源区的第一部分包括硅而外延特征物包括为了应变效应的不同半导体材料。在此实施例的更进一步中,n阱区中的外延特征物122包括锗化硅(SiGe)以配置为p型FinFET。p阱区中的外延特征物122包括碳化硅(SiC)或硅以配置为n型FinFET。外延特征物122借由一个或多个外延步骤形成。在一实施例中,绝缘特征物54借由浅沟槽绝缘技术形成;接着借由蚀刻工艺嵌入从基底52延伸的鳍式有源区的第一部分;并接着执行外延工艺以形成鳍式有源区的第二部分。在外延特征物122(如鳍式有源区的第二部分)使用不同半导体材料(例如p型FinFET的锗化硅和n型FinFET的碳化硅)的情况下,分别执行二个外延工艺至相对应的鳍式有源区。在本实施例中,外延工艺在多晶硅栅极堆叠的形成之后执行。
在鳍式有源区104、106、108和110其中相邻的鳍式有源区之间配置不同的间隔。在本实施例中,鳍式有源区104和106配置为具有第一间隔D1。鳍式有源区108配置为与相邻鳍式有源区106和110间具有第二间隔D2。第二间隔D2大于第一间隔D1。
当外延特征物122形成于相对应的鳍式有源区上时,横向外延成长将扩大鳍式有源区的尺寸并且如图4所示缩减间隔。对于与相邻鳍式有源区间具有第二间隔D2的鳍式有源区而言,相对应的外延特征物之间具有小于第二间隔D2的第三间隔D3。举例而言,鳍式有源区108和110在相对应的外延特征物122c和122d之间具有第三间距D3。对于具有第一间隔D1的鳍式有源区而言,相对应的外延特征物之间具有窄间隔或甚至横向结合(桥接)。举例而言,外延特征物122a和122b结合以形成连续的着陆特征物。既然外延特征物在多晶硅栅极堆叠的形成之后形成,外延特征物将只形成于源极和漏极区之上而非在鳍式有源区的一部分上,其中多晶硅栅极堆叠在篇幅以外。
半导体装置120包括配置在鳍式有源区和绝缘特征物之上的层间介电质(ILD)112。层间介电质112在组成和形成方面类似于图3中半导体结构100的层间介电质112。
半导体装置120更进一步包括形成于层间介电质112中的各接触窗,其配置为提供电气布线。本实施例包括接触窗126和128。设计接触窗126为合适的几何尺寸并且配置为同时电气接触外延特征物122a和122b。或者,配置接触窗126为着陆于结合的外延特征物122a和122b。在此种情况中,接触窗126可具有比图3中接触窗114还小的尺寸。接触窗128设计为只着陆于外延特征物122c,外延特征物122c与相邻外延特征物(122b和122d)间具有较大的第三间隔D3。类似于图3的接触窗114和116,接触窗126和128设计为在不牺牲SRAM装置品质的前提下缩减SRAM单元尺寸。
各接触窗的形成(例如接触窗126和128)类似于图3中接触窗114和116的形成并且包括在层间介电质112中形成接触窗洞以及用导电材料填入接触窗洞。在另一实施例中,接触窗126和128的形成包括在层间介电质112中形成接触窗洞、在接触窗洞内的基底上形成硅化物以及用导电材料填入接触窗洞。
图1到图4提供SRAM单元的各部分以及SRAM单元中同一部分的各实施例。举例而言,图1和图2提供SRAM单元沿着栅极堆叠的剖面图的二个不同实施例。图3和图4提供SRAM单元沿着源极/漏极区的剖面图的二个不同实施例。
图5到图15为根据本揭露提供SRAM单元的其他实施例。
图5为半导体结构130的俯视图,半导体结构130为SRAM单元的一部分。在本实施例中,半导体结构130包括n阱区132和p阱区134。半导体装置130包括多个鳍式有源区136a到136b。举例而言,鳍式有源区136a和136b配置在p阱区134以形成各n型FinFET(例如下拉装置和/或沟道栅装置),以及鳍式有源区136c、136d和136e配置在n阱区132以形成各p型FinFET(例如上拉装置)。栅极138形成于并跨越多个鳍式有源区136a到136e之上。各接触窗140a到140e形成于一些鳍式有源区和栅极138之上。举例而言,接触窗140a形成于与鳍式有源区136a和136b相关的n型FinFET的漏极上。接触窗140e形成于与鳍式有源区136a和136b相关的n型FinFET的源极上。接触窗140e耦接至互补电源线Vss。在另一例子中,接触窗140b形成于与鳍式有源区136c、136d和136e相关的p型FinFET的漏极上。接触窗140d形成于与鳍式有源区136c、136d和136e相关的p型FinFET的源极上。接触窗140d耦接至电源线Vcc。接触窗140c形成于栅极138之上。半导体结构130同时包括金属线142a、142b和142c。举例而言,金属线142a耦接至接触窗140e和互补电源线Vss。金属线142b耦接至接触窗140d和电源线Vcc。金属线142c耦接至接触窗140a和140b。
图8和图9所示为半导体结构130沿着aa’线的部分剖面图的不同实施例。在图8中,半导体结构146包括半导体基底52;绝缘特征物54;鳍式有源区136c、136d和136e;栅极介电质层60以及栅极电极62。半导体结构146的各特征物类似于图1的半导体结构50中相对应的特征物。在图9所示的另一实施例中,半导体结构148包括半导体基底82;介电质材料层84;鳍式有源区136c、136d和136e;栅极介电质92以及栅极电极94。半导体结构148的各特征物类似于图2的半导体结构80中相对应的特征物。
再参照图5,图10到图15所示为半导体结构130沿着线bb’的(部分)剖面图的不同实施例。在图10中,半导体结构150所示为半导体结构130沿着线bb’的右边部分。半导体结构150包括半导体基底52;绝缘特征物54;鳍式有源区136c、136d和136e;外延特征物122;以及层间介电质112。界面124形成于外延特征物122鳍式有源区之间。半导体结构150的各特征物类似于图4的半导体结构120中相对应的特征物。举例而言,鳍式有源区136c、136d和136e具有宽间隔D2,以及外延特征物122具有小于第二间隔D2的第三间隔D3。在各实施例中,外延特征物包括形成p型FinFET的锗化硅或形成n型FinFET的碳化硅。
在如图11所示的另一实施例中,半导体结构152包括半导体基底52;绝缘特征物54;鳍式有源区136a和136b;外延特征物122;以及层间介电质112。在一实施例中,半导体结构152所示为图5中半导体结构130的左边部分。半导体结构152的各特征物类似于图4的半导体结构120中相对应的特征物。举例而言,鳍式有源区136a和136b类似于图4的鳍式有源区104和106。鳍式有源区136a和136b具有较小的间隔D1。外延特征物122类似于图4的外延特征物122a和122b。相邻的二个外延特征物122结合。在各实施例中,外延特征物可包括形成p型FinFET的锗化硅或形成n型FinFET的碳化硅。
在如图12所示的另一实施例中,半导体结构154包括半导体基底52;绝缘特征物54;鳍式有源区156a,156b和156c;外延特征物122;以及层间介电质112。半导体结构154的各特征物类似于图4的半导体结构120中相对应的特征物。举例而言,鳍式有源区156b和156c类似于图4的鳍式有源区104和106。鳍式有源区156a类似于图4的鳍式有源区108。鳍式有源区156b和156c具有较小的间隔S1。与相邻鳍式有源区156b和156c相关的外延特征物122结合。在鳍式有源区156a上的外延特征物122横向延伸但与相邻的外延特征物122分开一段距离。在一实施例中,硅基底52包括硅而外延特征物122也包括硅。
在如图13所示的另一实施例中,半导体结构158包括半导体基底52;绝缘特征物54;鳍式有源区160a,160b和160c;外延特征物122;以及层间介电质112。半导体结构158的各特征物类似于图4的半导体结构120中相对应的特征物。举例而言,鳍式有源区160a,160b和160c类似于图4的鳍式有源区108和110。鳍式有源区160a,160b和160c具有较大的间隔S2。外延特征物122横向延伸但与相邻的外延特征物122分开一段距离。在一实施例中,硅基底52包括硅而外延特征物122也包括硅。
图14为半导体结构154的剖面图,类似于图12但更进一步包括接触窗126。接触窗126配置于结合的外延特征物122之上并且电气连接至二个相对应的鳍式有源区156b和156c。接触窗126类似于图4的接触窗126。
图15为半导体结构158的剖面图,类似于图13但更进一步包括接触窗128。接触窗128着陆于鳍式有源区160b的外延特征物122之上。接触窗128类似于图4的接触窗128。
图6为作为SRAM单元一部分的半导体结构160的俯视图。在本实施例中,半导体结构160包括多个鳍式有源区136a到136c。在各实施例中,鳍式有源区136a、136b和136c配置于不同FinFET的不同阱区中。举例而言,鳍式有源区136a和136b配置于p阱区以形成各n型FinFET(例如下拉装置和/或沟道栅装置),而鳍式有源区136c配置于n阱区以形成各p型FinFET(例如上拉装置)。栅极138形成于并跨越多个鳍式有源区136a到136c之上。各接触窗140a到140g形成于一些鳍式有源区和栅极138之上。各金属线142a到142f形成于接触窗上方并且设计为与相对应的接触窗耦接以形成功能电路。在本实施例中,功能电路包括一个或多个SRAM单元。在各个例子中,接触窗140a设计为登陆于鳍式有源区136a之上并且耦接至金属线142a。接触窗140b设计为登陆于鳍式有源区136b之上并且耦合至金属线142b,等等如此。接触窗140g设计为登陆于栅极138之上。
除此之外,接触窗140a接触第一FinFET的源极区,而接触窗140d接触第一FinFET的漏极区。接触窗140b接触第二FinFET的源极区,而接触窗140e接触第二FinFET的漏极区。接触窗140c接触第三FinFET的源极区,而接触窗140f接触第三FinFET的漏极区。接触窗140a到140f类似于图4的接触窗128。图10所示为半导体结构160沿着线cc’的部面剖面图,如前所述。
图7为作为SRAM单元一部分的半导体结构162的俯视图。在本实施例中,半导体结构162包括多个鳍式有源区136a和136b。在一实施例中,鳍式有源区136a和136b配置于阱区(n阱或p阱)中。举例而言,鳍式有源区136a和136b配置于p阱区中以形成各n型FinFET(例如下拉装置和/或沟道栅装置)。栅极138形成于并跨越多个鳍式有源区136a和136b之上以形成第一和第二FinFET。各接触窗140a到140c形成于鳍式有源区和栅极138之上。各金属线142a和142b形成于接触窗上方并且设计为与相对应的接触窗耦合以形成功能电路。在一个例子中,接触窗140a配置于二相邻鳍式有源区136a和136b之间。接触窗140a同时接触相邻的鳍式有源区136a和136b。同样地,接触窗140b配置于二相邻鳍式有源区136a和136b之间并且同时接触相邻的鳍式有源区136a和136b。接触窗140a更进一步耦接至金属线142a。接触窗140b更进一步耦接至金属线142b。除此之外,接触窗140a接触第一和第二FinFET的源极区,而接触窗140b接触第一和第二FinFET的漏极区。图11所示为半导体结构162沿着线dd’的部面剖面图,如前所述。
在一实施例中,制造具有沟道栅、下拉和上拉装置的SRAM单元的制造流程有下列步骤:形成鳍式有源区、形成阱区、形成沟道掺杂物、形成栅极、成长外延以形成外延特征物、形成轻掺杂漏极(LDD)、形成栅极间隙壁、形成源极/栅极掺杂、形成层间介电质、栅极取代以形成具有高介电常数材料的栅极堆叠以及金属栅极电极、蚀刻以形成接触窗洞、在源极/漏极区和栅极上形成硅化物、形成接触窗、以及接下来的步骤以形成多层金属线和介层窗。尤其是,外延特征物在栅极形成之后形成并且只形成于源极和漏极之上。鳍式有源区包括在栅极堆叠之下没有外延半导体材料且没有横向扩展的部分。鳍式有源区配置为具有不同间隔。SRAM单元包括二个具有较小间隔D1的相邻鳍式有源区以及与相邻鳍式有源区间具有较大间隔D2的鳍式有源区。此二个具有较小间隔D1的相邻鳍式有源区包括在相对应外延特征物之间更进一步缩减的间隔。在一种情况中,此二外延特征物结合。SRAM单元也包括一第一类型和一第二类型的接触窗。每个此第一类型的接触窗形成于具有较小间隔D1的二鳍式有源区之间并且同时接触二个鳍式有源区。每个此第二类型的接触窗配置于与相邻鳍式有源区间具有较大间隔D2的鳍式有源区之上并且只接触此相对应的鳍式有源区。
图16所示为根据一实施例中本揭露所绘制的SRAM单元170的示意图。SRAM单元170包括鳍式场效应晶体管(FinFET)。SRAM单元170包括用以存储数据的交叉耦合的一第一和一第二反相器。第一反相器包括以p型FinFET构成的第一上拉装置PU-1。第一反相器也包括以n型FinFET构成的第一下拉装置PD-1。第一上拉装置PU-1的漏极和第一下拉装置PD-1的漏极电气连接,形成第一数据节点Node 1。第一上拉装置PU-1的栅极和第一下拉装置PD-1的栅极电气连接。第一上拉装置PU-1的源极电气连接至电源线Vcc。第一下拉装置PD-1的源极电气连接至互补电源线Vss。第二反相器包括以p型FinFET构成的第二上拉装置PU-2。第二反相器也包括以n型FinFET构成的第二下拉装置PD-2。第二上拉装置PU-2的漏极和第二下拉装置PD-2的漏极电气连接,形成第二数据节点Node 2。第二上拉装置PU-2的栅极和第二下拉装置PD-2的栅极电气连接。第二上拉装置PU-2的源极电气连接至电源线Vcc。第二下拉装置PD-2的源极电气连接至互补电源线Vss。除此之外,第一数据节点电气连接至第二上拉装置PU-2和第二下拉装置PD-2的栅极,而第二数据节点电气连接至第一上拉装置PU-1和第一下拉装置PD-1栅极。因此,第一和第二反相器为交叉耦合,如图16所示。
SRAM单元170更进一步包括以n型FinFET构成的第一沟道栅装置PG-1,以及以n型FinFET构成的第二沟道栅装置PG-2。第一沟道栅装置PG-1的源极电气连接至第一数据节点并且第二沟道栅装置PG-2的源极电气连接至第二数据节点,形成数据存取的一端口。除此之外,第一沟道栅装置PG-1的漏极电气连接至位线BL,并且第一沟道栅装置PG-1的栅极电气连接至字线WL。同样地,第二沟道栅装置PG-2的漏极电气连接至反相位线BLB,并且第二沟道栅装置PG2的栅极电气连接至字线WL。
在一实施例中,各n型FinFET和各p型FinFET使用高介电常数/金属栅极技术来形成以使栅极堆叠包括以高介电常数介电质层形成的栅极介电质以及以一种或多种金属形成的栅极电极。SRAM单元170可包括额外的装置,例如额外的下拉装置和沟道栅装置。在一例子中,每个第一和第二反相器包括形成于多个鳍式有源区之上且配置为并联的多个下拉装置。此并联的多个下拉装置配置为漏极连接在一起,源极一起连接至互补电源线Vss,栅极连接在一起。在此种情况下,配置具有较小间隔D1的鳍式有源区,且第一类型的接触窗形成在封闭配置的外延特征物或结合的外延特征物上。
在另一例子中,单元177包括一额外的端口,该额外的端口具有二个或多个沟道栅装置用以存取数据,例如数据读取或写入。那些沟道栅装置配置为并联,并且也可将鳍式有源区和第一类型接触窗的配置和设计以类似下拉装置的并联方式来实施。在另一例子中,若上拉装置可实现与相邻鳍式有源区间具有较大间隔D2的鳍式有源区以及第二类型接触窗。在另一实施例中,接触窗设计为登陆于并接触多个紧密排列的鳍式有源区(例如较小间隔D1)。参照图5举例,接触窗140d接触三个鳍式有源区136c、136d和136e。
在各实施例中,所揭露的SRAM装置克服在现有技术中所提过的问题。在一例子中,借由以较小间隔D1实施第一鳍式有源区并以较大间隔D2实施第二鳍式有源区,可缩减第一鳍式有源区的第一类型接触窗、第二鳍式有源区的第二类型接触窗以及SRAM单元面积,而同时可以改进和保持SRAM单元的功能性和效能。在另一实施例中,外延特征物包括凸起结构,此凸起结构的上表面高于相对应的栅极堆叠的栅极介电质层。在一特定例子中,具有凸起结构的外延特征物为硅外延特征物。在另一实施例中,二个结合的外延特征物为二个硅外延特征物。硅化物形成于结合的二个硅外延特征物之上以使相对应的源极或漏极电气连接。
以上所述为数个实施例的概述特征。本领域普通技术人员应了解他们可以轻而易举地利用本揭露为基础设计或调整其他工艺和结构以实行相同的目的和/或达成此处介绍的实施例的相同优点。本领域普通技术人员也应了解相同的配置不应背离本揭露的精神与范围,在不背离本揭露的精神与范围下他们可做出各种改变、取代和交替。
Claims (10)
1.一种静态随机存取存储器,即SRAM单元,包括:
多个鳍式有源区,其形成于一半导体基底上,其中所述多个鳍式有源区包括第一鳍式有源区、第二鳍式有源区和第三鳍式有源区,其中该第一鳍式有源区和该第二鳍式有源区相邻并且具有一第一间隔,该第三鳍式有源区与相邻的鳍式有源区间具有一第二间隔,该第二间隔大于该第一间隔;
多个鳍式场效应晶体管,即FinFET,其形成于所述多个鳍式有源区之上,其中所述多个鳍式场效应晶体管配置为构成交叉耦合的第一反相器和第二反相器以存储数据,以及存取数据的至少一端口;
一第一接触窗,其配置于该第一鳍式有源区和该第二鳍式有源区之间并电气耦接至该第一鳍式有源区和该第二鳍式有源区;以及
一第二接触窗,其配置于该第三鳍式有源区之上并电气耦接至该第三鳍式有源区。
2.如权利要求1所述的静态随机存取存储器单元,其中该第一鳍式有源区和该第二鳍式有源区还分别包括第一外延特征物和第二外延特征物,该第一外延特征物和该第二外延特征物分别形成于该第一鳍式有源区和该第二鳍式有源区之上。
3.如权利要求1所述的静态随机存取存储器单元,其中:
每一所述多个鳍式有源区包括一外延特征物,其配置于从该半导体基底延伸的该鳍式有源区的另一部分上;
一界面,其位于该外延特征物与该鳍式有源区的另一部分之间;以及
一绝缘特征物,其横向配置于所述多个鳍式有源区之间,该界面位于该绝缘特征物的顶部表面的垂直下方。
4.如权利要求1所述的静态随机存取存储器单元,该第一接触窗还接触另一个鳍式有源区,其相邻该第一鳍式有源区和该第二鳍式有源区并具有与该第一间隔相同的一间隔。
5.如权利要求1所述的静态随机存取存储器单元,其中所述多个鳍式场效应晶体管包括:
一第一上拉装置和一第二上拉装置;
一第一下拉装置,其与该第一上拉装置配置形成该第一反相器;
一第二下拉装置,其与该第二上拉装置配置形成该第二反相器;以及
一第一沟道栅装置和一第二沟道栅装置,其与该第一反相器和该第二反相器配置作为一第一端口。
6.一种半导体结构,包括:
一第一鳍式有源区和一第二鳍式有源区,其从一半导体基底延伸并且彼此相距一第一距离;
一第三鳍式有源区和一第四鳍式有源区,其从该半导体基底延伸并且彼此相距大于该第一距离的一第二距离;
一第一外延特征物和一第二外延特征物,其分别形成于该第一鳍式有源区与该第二鳍式有源区之上,其中该第一外延特征物和该第二外延特征物横向结合;
一第三外延特征物和一第四外延特征物,其分别形成于该第三鳍式有源区与该第四鳍式有源区之上,其中该第三外延特征物和该第四外延特征物彼此分开;
一第一接触窗,其配置于结合的该第一外延特征物和该第二外延特征物之上;以及
一第二接触窗,其配置于该第三外延特征物之上,其中该第二接触窗与该第四外延特征物间隔排列并且没有电气连接至该第四鳍式有源区。
7.如权利要求6所述的半导体结构,还包括:
一绝缘特征物,其横向配置在该第一鳍式有源区和该第二鳍式有源区之间;以及
一界面,其位于该第一外延特征物和该第一鳍式有源区之间,其中该界面位于该绝缘特征物的顶部表面下方。
8.如权利要求6所述的半导体结构,还包括一硅化物特征物,其位于该第三外延特征物与该第三鳍式有源区之间。
9.一种静态随机存取存储器单元,包括:
一第一反相器,其包括一第一上拉晶体管、一第一下拉晶体管和一第二下拉晶体管;
一第二反相器,其包括一第二上拉晶体管、一第三下拉晶体管和一第四下拉晶体管,该第二反相器与该第一反相器交叉耦合以存储数据;
一端口,其包括一第一沟道栅晶体管和一第二沟道栅晶体管,该端口与该第一反相器和该第二反相器耦合以存储数据,其中每个第一下拉晶体管、第二下拉晶体管、第三下拉晶体管、第四下拉晶体管、第一沟道栅和第二沟道栅包括一n型鳍式场效应晶体管以及每个第一上拉晶体管和第二上拉晶体管包括一p型鳍式场效应晶体管;
一第一鳍式有源区和一第二鳍式有源区,其分别具有一第一硅外延特征物和一第二硅外延特征物,其中该第一硅外延特征物和该第二硅外延特征物结合,且该第一下拉晶体管和该第二下拉晶体管分别形成于该第一鳍式有源区和该第二鳍式有源区之上;以及
一硅化物特征物,其形成于结合的该第一硅外延特征物和该第二硅外延特征物之上,并将该第一下拉晶体管的源极区和该第二下拉晶体管的源极区电气连接。
10.如权利要求9所述的静态随机存取存储器单元,其中该第一硅外延特征物和该第二硅外延特征物包括一凸起结构,该凸起结构的顶部表面高于该第一下拉晶体管和该第二下拉晶体管的栅极介电质。
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US8796759B2 (en) | 2010-07-15 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin-like field effect transistor (FinFET) device and method of manufacturing same |
US9130058B2 (en) | 2010-07-26 | 2015-09-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Forming crown active regions for FinFETs |
US8367498B2 (en) | 2010-10-18 | 2013-02-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin-like field effect transistor (FinFET) device and method of manufacturing same |
US9472550B2 (en) | 2010-11-23 | 2016-10-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Adjusted fin width in integrated circuitry |
US8633076B2 (en) | 2010-11-23 | 2014-01-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for adjusting fin width in integrated circuitry |
US8649209B1 (en) * | 2011-03-25 | 2014-02-11 | Altera Corporation | Memory element circuitry with reduced oxide definition width |
TWI514614B (zh) * | 2011-08-30 | 2015-12-21 | Lextar Electronics Corp | 固態發光半導體結構及其磊晶層成長方法 |
JP2013058688A (ja) * | 2011-09-09 | 2013-03-28 | Toshiba Corp | 半導体装置の製造方法 |
US8796124B2 (en) | 2011-10-25 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Doping method in 3D semiconductor device |
US8693235B2 (en) | 2011-12-06 | 2014-04-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for finFET SRAM arrays in integrated circuits |
US8582352B2 (en) * | 2011-12-06 | 2013-11-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for FinFET SRAM cells |
KR101876793B1 (ko) * | 2012-02-27 | 2018-07-11 | 삼성전자주식회사 | 전계효과 트랜지스터 및 그 제조 방법 |
US9105744B2 (en) | 2012-03-01 | 2015-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices having inactive fin field effect transistor (FinFET) structures and manufacturing and design methods thereof |
US10515956B2 (en) | 2012-03-01 | 2019-12-24 | Taiwan Semiconductor Manufacturing Company | Semiconductor devices having Fin Field Effect Transistor (FinFET) structures and manufacturing and design methods thereof |
US9368388B2 (en) * | 2012-04-13 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus for FinFETs |
US8969974B2 (en) | 2012-06-14 | 2015-03-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for FinFET device |
US9024387B2 (en) * | 2012-06-25 | 2015-05-05 | International Business Machines Corporation | FinFET with body contact |
US9018713B2 (en) | 2012-06-25 | 2015-04-28 | International Business Machines Corporation | Plural differential pair employing FinFET structure |
US9142400B1 (en) | 2012-07-17 | 2015-09-22 | Stc.Unm | Method of making a heteroepitaxial layer on a seed area |
KR20140040543A (ko) * | 2012-09-26 | 2014-04-03 | 삼성전자주식회사 | 핀 구조의 전계효과 트랜지스터, 이를 포함하는 메모리 장치 및 그 반도체 장치 |
US8822320B2 (en) * | 2012-11-20 | 2014-09-02 | International Business Machines Corporation | Dense finFET SRAM |
US9397217B2 (en) * | 2012-12-28 | 2016-07-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact structure of non-planar semiconductor device |
US9859429B2 (en) * | 2013-01-14 | 2018-01-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device and method of fabricating same |
US8779546B1 (en) * | 2013-03-07 | 2014-07-15 | Sony Corporation | Semiconductor memory system with bit line and method of manufacture thereof |
EP2969433B1 (en) * | 2013-03-12 | 2018-11-28 | Robert Bosch GmbH | Power tool comprising a workpiece material detector |
US9892922B1 (en) * | 2013-07-05 | 2018-02-13 | Altera Corporation | Methods for fabricating integrated circuits with triple gate oxide devices |
US9023697B2 (en) * | 2013-08-08 | 2015-05-05 | International Business Machines Corporation | 3D transistor channel mobility enhancement |
US9059002B2 (en) * | 2013-08-27 | 2015-06-16 | International Business Machines Corporation | Non-merged epitaxially grown MOSFET devices |
KR102224525B1 (ko) | 2014-02-03 | 2021-03-08 | 삼성전자주식회사 | 레이아웃 디자인 시스템, 이를 이용하여 제조한 반도체 장치 및 그 반도체 장치의 제조 방법 |
US9548303B2 (en) | 2014-03-13 | 2017-01-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET devices with unique fin shape and the fabrication thereof |
CN106030812B (zh) | 2014-03-27 | 2019-09-24 | 英特尔公司 | 锗锡沟道晶体管 |
US9698240B2 (en) * | 2014-03-31 | 2017-07-04 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device and formation thereof |
US9443769B2 (en) | 2014-04-21 | 2016-09-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wrap-around contact |
US9391173B2 (en) | 2014-04-22 | 2016-07-12 | International Business Machines Corporation | FinFET device with vertical silicide on recessed source/drain epitaxy regions |
US10177133B2 (en) | 2014-05-16 | 2019-01-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device including source/drain contact having height below gate stack |
US9564530B2 (en) | 2014-06-23 | 2017-02-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit structure and method with solid phase diffusion |
US9608116B2 (en) * | 2014-06-27 | 2017-03-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | FINFETs with wrap-around silicide and method forming the same |
US9966471B2 (en) | 2014-06-27 | 2018-05-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked Gate-All-Around FinFET and method forming the same |
KR102192350B1 (ko) | 2014-08-05 | 2020-12-18 | 삼성전자주식회사 | 반도체 소자의 미세 패턴 형성 방법 및 이를 이용한 반도체 소자의 제조방법 |
US9324619B2 (en) * | 2014-08-25 | 2016-04-26 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
US10026661B2 (en) | 2014-09-18 | 2018-07-17 | Samsung Electronics Co., Ltd. | Semiconductor device for testing large number of devices and composing method and test method thereof |
US9767248B2 (en) | 2014-09-18 | 2017-09-19 | Samsung Electronics, Co., Ltd. | Semiconductor having cross coupled structure and layout verification method thereof |
US9704862B2 (en) | 2014-09-18 | 2017-07-11 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods for manufacturing the same |
US9811626B2 (en) | 2014-09-18 | 2017-11-07 | Samsung Electronics Co., Ltd. | Method of designing layout of semiconductor device |
US10095825B2 (en) | 2014-09-18 | 2018-10-09 | Samsung Electronics Co., Ltd. | Computer based system for verifying layout of semiconductor device and layout verify method thereof |
US9589955B2 (en) | 2014-10-01 | 2017-03-07 | Samsung Electronics Co., Ltd. | System on chip |
KR102288869B1 (ko) | 2014-10-01 | 2021-08-10 | 삼성전자주식회사 | 시스템 온 칩 |
US9437484B2 (en) | 2014-10-17 | 2016-09-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Etch stop layer in integrated circuits |
US9418896B2 (en) | 2014-11-12 | 2016-08-16 | Samsung Electronics Co., Ltd. | Semiconductor device and fabricating method thereof |
US9466494B2 (en) | 2014-11-18 | 2016-10-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Selective growth for high-aspect ration metal fill |
US9508858B2 (en) | 2014-11-18 | 2016-11-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contacts for highly scaled transistors |
US9412817B2 (en) | 2014-12-19 | 2016-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Silicide regions in vertical gate all around (VGAA) devices and methods of forming same |
US9613850B2 (en) | 2014-12-19 | 2017-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lithographic technique for feature cut by line-end shrink |
US9859286B2 (en) * | 2014-12-23 | 2018-01-02 | International Business Machines Corporation | Low-drive current FinFET structure for improving circuit density of ratioed logic in SRAM devices |
US9876114B2 (en) | 2014-12-30 | 2018-01-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for 3D FinFET metal gate |
US9673112B2 (en) | 2015-02-13 | 2017-06-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of semiconductor fabrication with height control through active region profile |
US9859115B2 (en) | 2015-02-13 | 2018-01-02 | National Taiwan University | Semiconductor devices comprising 2D-materials and methods of manufacture thereof |
US9502502B2 (en) | 2015-03-16 | 2016-11-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of manufacture thereof |
US9911727B2 (en) | 2015-03-16 | 2018-03-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strapping structure of memory circuit |
KR102307467B1 (ko) * | 2015-03-20 | 2021-09-29 | 삼성전자주식회사 | 액티브 핀을 포함하는 반도체 장치 |
KR102352153B1 (ko) | 2015-03-25 | 2022-01-17 | 삼성전자주식회사 | 집적회로 장치 및 이의 제조 방법 |
US9698048B2 (en) | 2015-03-27 | 2017-07-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating semiconductor device |
KR102432268B1 (ko) | 2015-04-14 | 2022-08-12 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법. |
KR102170701B1 (ko) | 2015-04-15 | 2020-10-27 | 삼성전자주식회사 | 반도체 장치 제조 방법 |
US9673145B2 (en) * | 2015-05-07 | 2017-06-06 | United Microelectronics Corp. | Semiconductor integrated circuit layout structure |
US9653346B2 (en) | 2015-05-07 | 2017-05-16 | United Microelectronics Corp. | Integrated FinFET structure having a contact plug pitch larger than fin and first metal pitch |
US9761683B2 (en) | 2015-05-15 | 2017-09-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US9576796B2 (en) | 2015-05-15 | 2017-02-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of manufacture thereof |
US9741829B2 (en) | 2015-05-15 | 2017-08-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US10062779B2 (en) | 2015-05-22 | 2018-08-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US9685368B2 (en) | 2015-06-26 | 2017-06-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure having an etch stop layer over conductive lines |
US10403744B2 (en) | 2015-06-29 | 2019-09-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices comprising 2D-materials and methods of manufacture thereof |
US11424399B2 (en) | 2015-07-07 | 2022-08-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated thermoelectric devices in Fin FET technology |
US9418886B1 (en) | 2015-07-24 | 2016-08-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming conductive features |
US9536980B1 (en) | 2015-07-28 | 2017-01-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gate spacers and methods of forming same |
US9698100B2 (en) | 2015-08-19 | 2017-07-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for interconnection |
US9564363B1 (en) | 2015-08-19 | 2017-02-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming butted contact |
US9831090B2 (en) | 2015-08-19 | 2017-11-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and structure for semiconductor device having gate spacer protection layer |
US9721887B2 (en) | 2015-08-19 | 2017-08-01 | Taiwan Semiconductor Manufacturing Company, Ltd | Method of forming metal interconnection |
US9728402B2 (en) | 2015-08-21 | 2017-08-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Flowable films and methods of forming flowable films |
US9786602B2 (en) | 2015-08-21 | 2017-10-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnection structure and methods of fabrication the same |
US9490136B1 (en) | 2015-08-31 | 2016-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming trench cut |
US9613856B1 (en) | 2015-09-18 | 2017-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming metal interconnection |
US9972529B2 (en) | 2015-09-28 | 2018-05-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming metal interconnection |
US10163797B2 (en) | 2015-10-09 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Forming interlayer dielectric material by spin-on metal oxide deposition |
US9735052B2 (en) | 2015-10-12 | 2017-08-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal lines for interconnect structure and method of manufacturing same |
US9711533B2 (en) | 2015-10-16 | 2017-07-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET devices having different source/drain proximities for input/output devices and non-input/output devices and the method of fabrication thereof |
US9659864B2 (en) | 2015-10-20 | 2017-05-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for forming self-aligned via with selectively deposited etching stop layer |
KR102323943B1 (ko) | 2015-10-21 | 2021-11-08 | 삼성전자주식회사 | 반도체 장치 제조 방법 |
US9647116B1 (en) | 2015-10-28 | 2017-05-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for fabricating self-aligned contact in a semiconductor device |
US9818690B2 (en) | 2015-10-30 | 2017-11-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned interconnection structure and method |
US9627531B1 (en) | 2015-10-30 | 2017-04-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Field-effect transistor with dual vertical gates |
US9520482B1 (en) | 2015-11-13 | 2016-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of cutting metal gate |
US9633999B1 (en) | 2015-11-16 | 2017-04-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and structure for semiconductor mid-end-of-line (MEOL) process |
US10164051B2 (en) | 2015-11-16 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of cutting metal gate |
US9899387B2 (en) | 2015-11-16 | 2018-02-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-gate device and method of fabrication thereof |
US9773879B2 (en) | 2015-11-30 | 2017-09-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and a method for fabricating the same |
US10340348B2 (en) | 2015-11-30 | 2019-07-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing finFETs with self-align contacts |
US10163719B2 (en) | 2015-12-15 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming self-alignment contact |
US9873943B2 (en) | 2015-12-15 | 2018-01-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Apparatus and method for spatial atomic layer deposition |
US9728501B2 (en) | 2015-12-21 | 2017-08-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming trenches |
DE102016116026B4 (de) | 2015-12-29 | 2024-02-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Halbleitervorrichtung und Herstellungsverfahren |
US9887128B2 (en) | 2015-12-29 | 2018-02-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and structure for interconnection |
US10163704B2 (en) | 2015-12-29 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and a method for fabricating the same |
US9614086B1 (en) | 2015-12-30 | 2017-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conformal source and drain contacts for multi-gate field effect transistors |
US9899269B2 (en) | 2015-12-30 | 2018-02-20 | Taiwan Semiconductor Manufacturing Company, Ltd | Multi-gate device and method of fabrication thereof |
US11088030B2 (en) | 2015-12-30 | 2021-08-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and a method for fabricating the same |
US10115796B2 (en) | 2016-01-07 | 2018-10-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of pulling-back sidewall metal layer |
US10811262B2 (en) | 2016-01-14 | 2020-10-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device having a uniform and thin silicide layer on an epitaxial source/ drain structure and manufacturing method thereof |
US9881872B2 (en) | 2016-01-15 | 2018-01-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for fabricating a local interconnect in a semiconductor device |
US10727094B2 (en) | 2016-01-29 | 2020-07-28 | Taiwan Semiconductor Manufacturing Co., Ltd | Thermal reflector device for semiconductor fabrication tool |
US10163912B2 (en) | 2016-01-29 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for semiconductor device fabrication with improved source drain proximity |
US10283605B2 (en) | 2016-01-29 | 2019-05-07 | Taiwan Semiconductor Manufacturing Co., Ltd | Self-aligned metal gate etch back process and device |
US9812451B2 (en) | 2016-02-03 | 2017-11-07 | Taiwan Semiconductor Manufacturing Company, Ltd | Field effect transistor contact with reduced contact resistance |
US10535558B2 (en) | 2016-02-09 | 2020-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming trenches |
US9543161B1 (en) | 2016-02-10 | 2017-01-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of planarizating film |
US9947756B2 (en) | 2016-02-18 | 2018-04-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and manufacturing method thereof |
TWI726869B (zh) * | 2016-02-24 | 2021-05-11 | 聯華電子股份有限公司 | 靜態隨機存取記憶體的佈局結構及其製作方法 |
US9754822B1 (en) | 2016-03-02 | 2017-09-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure and method |
US9755019B1 (en) | 2016-03-03 | 2017-09-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US9570556B1 (en) | 2016-03-03 | 2017-02-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US10056407B2 (en) | 2016-03-04 | 2018-08-21 | Taiwan Semiconductor Manufacturing Co., Ltd | Semiconductor device and a method for fabricating the same |
US10109627B2 (en) | 2016-03-08 | 2018-10-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Enlarging spacer thickness by forming a dielectric layer over a recessed interlayer dielectric |
US9711402B1 (en) | 2016-03-08 | 2017-07-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming contact metal |
US9911611B2 (en) | 2016-03-17 | 2018-03-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming openings in a material layer |
DE102016114724B4 (de) | 2016-03-25 | 2021-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Verfahren zum Ausbilden von Gräben mit unterschiedlichen Tiefen und Vorrichtung |
US9779984B1 (en) | 2016-03-25 | 2017-10-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming trenches with different depths |
US9548366B1 (en) | 2016-04-04 | 2017-01-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self aligned contact scheme |
US9847477B2 (en) | 2016-04-12 | 2017-12-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a bottom electrode of a magnetoresistive random access memory cell |
US9805951B1 (en) | 2016-04-15 | 2017-10-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of integration process for metal CMP |
US9893062B2 (en) | 2016-04-28 | 2018-02-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and a method for fabricating the same |
US10475847B2 (en) | 2016-04-28 | 2019-11-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device having stress-neutralized film stack and method of fabricating same |
US9899266B2 (en) | 2016-05-02 | 2018-02-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET structures and methods of forming the same |
US11127629B2 (en) | 2016-05-17 | 2021-09-21 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and fabricating method thereof |
US10276662B2 (en) | 2016-05-31 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming contact trench |
US9917085B2 (en) | 2016-05-31 | 2018-03-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal gate isolation structure and method forming same |
US9941386B2 (en) | 2016-06-01 | 2018-04-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure with fin structure and method for forming the same |
US10109467B2 (en) | 2016-06-01 | 2018-10-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Advanced exhaust system |
US9627258B1 (en) | 2016-06-15 | 2017-04-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming a contact |
US10164032B2 (en) | 2016-06-17 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned contact and manufacturing method thereof |
US10515822B2 (en) | 2016-06-20 | 2019-12-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for preventing bottom layer wrinkling in a semiconductor device |
US10008414B2 (en) | 2016-06-28 | 2018-06-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | System and method for widening Fin widths for small pitch FinFET devices |
US10685873B2 (en) | 2016-06-29 | 2020-06-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Etch stop layer for semiconductor devices |
US9768064B1 (en) | 2016-07-14 | 2017-09-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Formation method of semiconductor device structure |
US9640540B1 (en) | 2016-07-19 | 2017-05-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and method for an SRAM circuit |
US10121873B2 (en) | 2016-07-29 | 2018-11-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal gate and contact plug design and method forming same |
US9721805B1 (en) | 2016-07-29 | 2017-08-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Formation method of semiconductor device structure |
US10199500B2 (en) | 2016-08-02 | 2019-02-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-layer film device and method |
US9929271B2 (en) | 2016-08-03 | 2018-03-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
US9991205B2 (en) | 2016-08-03 | 2018-06-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
US10522536B2 (en) | 2016-08-03 | 2019-12-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method of semiconductor device with gate stacks |
US10043886B2 (en) | 2016-08-03 | 2018-08-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal gate formation through etch back process |
US10510850B2 (en) | 2016-08-03 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
US10164111B2 (en) | 2016-08-03 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and methods of manufacture |
US9997524B2 (en) | 2016-08-24 | 2018-06-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor memory device and manufacturing method thereof |
US10269926B2 (en) | 2016-08-24 | 2019-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Purging deposition tools to reduce oxygen and moisture in wafers |
US9865697B1 (en) | 2016-08-25 | 2018-01-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure and method for forming the same |
US10580901B2 (en) * | 2016-09-02 | 2020-03-03 | International Business Machines Corporation | Stacked series connected VFETs for high voltage applications |
US9812358B1 (en) | 2016-09-14 | 2017-11-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET structures and methods of forming the same |
US9865589B1 (en) | 2016-10-31 | 2018-01-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | System and method of fabricating ESD FinFET with improved metal landing in the drain |
US10043665B2 (en) | 2016-11-28 | 2018-08-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Formation method of semiconductor device structure with semiconductor nanowire |
US10049930B2 (en) | 2016-11-28 | 2018-08-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory device and operation method thereof |
US9881834B1 (en) | 2016-11-29 | 2018-01-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact openings and methods forming same |
US9985134B1 (en) | 2016-11-29 | 2018-05-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs and methods of forming FinFETs |
US10290546B2 (en) | 2016-11-29 | 2019-05-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Threshold voltage adjustment for a gate-all-around semiconductor structure |
CN108122976B (zh) * | 2016-11-29 | 2020-11-03 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法、以及sram |
US10510598B2 (en) | 2016-11-29 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned spacers and method forming same |
US10886268B2 (en) * | 2016-11-29 | 2021-01-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing a semiconductor device with separated merged source/drain structure |
US9837539B1 (en) | 2016-11-29 | 2017-12-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device and method of forming |
US10008416B2 (en) | 2016-11-30 | 2018-06-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Forming a protective layer to prevent formation of leakage paths |
US10707316B2 (en) | 2016-12-09 | 2020-07-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method of semiconductor device structure with gate structure |
EP3335821B1 (en) | 2016-12-14 | 2020-10-07 | Sandvik Intellectual Property AB | Internal milling cutter |
US9865595B1 (en) | 2016-12-14 | 2018-01-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET device with epitaxial structures that wrap around the fins and the method of fabricating the same |
US10157781B2 (en) | 2016-12-14 | 2018-12-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming semiconductor structure using polishing process |
US9972571B1 (en) | 2016-12-15 | 2018-05-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Logic cell structure and method |
US10049936B2 (en) | 2016-12-15 | 2018-08-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device having merged epitaxial features with Arc-like bottom surface and method of making the same |
US10651171B2 (en) | 2016-12-15 | 2020-05-12 | Taiwan Semiconductor Manufacturing Co. Ltd. | Integrated circuit with a gate structure and method making the same |
US10079289B2 (en) | 2016-12-22 | 2018-09-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metal gate structure and methods thereof |
US10164106B2 (en) | 2016-12-29 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and a method for fabricating the same |
US9985023B1 (en) | 2017-02-21 | 2018-05-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method of semiconductor device structure |
US9859364B1 (en) | 2017-03-03 | 2018-01-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US10153198B2 (en) | 2017-04-07 | 2018-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low-resistance contact plugs and method forming same |
US10056390B1 (en) | 2017-04-20 | 2018-08-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET SRAM having discontinuous PMOS fin lines |
US10522643B2 (en) | 2017-04-26 | 2019-12-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Device and method for tuning threshold voltage by implementing different work function metals in different segments of a gate |
US10522417B2 (en) | 2017-04-27 | 2019-12-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET device with different liners for PFET and NFET and method of fabricating thereof |
US10411020B2 (en) * | 2017-08-31 | 2019-09-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Using three or more masks to define contact-line-blocking components in FinFET SRAM fabrication |
US10276720B2 (en) * | 2017-08-31 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming fin field effect transistor (FINFET) device structure |
US10453753B2 (en) | 2017-08-31 | 2019-10-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Using a metal-containing layer as an etching stop layer and to pattern source/drain regions of a FinFET |
US10276697B1 (en) | 2017-10-27 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Negative capacitance FET with improved reliability performance |
US10522557B2 (en) | 2017-10-30 | 2019-12-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Surface topography by forming spacer-like components |
US10366915B2 (en) | 2017-11-15 | 2019-07-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET devices with embedded air gaps and the fabrication thereof |
US10510894B2 (en) | 2017-11-30 | 2019-12-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Isolation structure having different distances to adjacent FinFET devices |
US10756114B2 (en) | 2017-12-28 | 2020-08-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor circuit with metal structure and manufacturing method |
CN109979881B (zh) * | 2017-12-28 | 2023-07-18 | 中芯国际集成电路制造(北京)有限公司 | 静态随机存取存储器的结构及其形成方法 |
US10854615B2 (en) | 2018-03-30 | 2020-12-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET having non-merging epitaxially grown source/drains |
US10629706B2 (en) | 2018-05-10 | 2020-04-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin and gate dimensions for optimizing gate formation |
US11302535B2 (en) | 2018-06-27 | 2022-04-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Performing annealing process to improve fin quality of a FinFET semiconductor |
US10665506B2 (en) | 2018-06-27 | 2020-05-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with reduced via bridging risk |
US10790352B2 (en) | 2018-06-28 | 2020-09-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | High density capacitor implemented using FinFET |
US10388771B1 (en) | 2018-06-28 | 2019-08-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and device for forming cut-metal-gate feature |
US10886226B2 (en) | 2018-07-31 | 2021-01-05 | Taiwan Semiconductor Manufacturing Co, Ltd. | Conductive contact having staircase barrier layers |
US11121129B2 (en) * | 2018-07-31 | 2021-09-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device |
US10998241B2 (en) | 2018-09-19 | 2021-05-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Selective dual silicide formation using a maskless fabrication process flow |
US11210447B2 (en) | 2018-09-26 | 2021-12-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Reconfiguring layout and sizing for transistor components to simultaneously optimize logic devices and non-logic devices |
US11069793B2 (en) | 2018-09-28 | 2021-07-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Reducing parasitic capacitance for gate-all-around device by forming extra inner spacers |
US11139203B2 (en) | 2018-10-22 | 2021-10-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Using mask layers to facilitate the formation of self-aligned contacts and vias |
US10971605B2 (en) | 2018-10-22 | 2021-04-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dummy dielectric fin design for parasitic capacitance reduction |
KR20200116646A (ko) * | 2019-04-02 | 2020-10-13 | 삼성전자주식회사 | 표준 셀을 포함하는 집적 회로 및 반도체 장치 |
US11508822B2 (en) | 2019-09-25 | 2022-11-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Source/drain via having reduced resistance |
US11764220B2 (en) | 2020-04-27 | 2023-09-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing a semiconductor device by patterning a serpentine cut pattern |
US11769821B2 (en) | 2020-05-15 | 2023-09-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device having a corner spacer |
US11996453B2 (en) | 2021-08-27 | 2024-05-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Introducing fluorine to gate after work function metal deposition |
CN117858496B (zh) * | 2024-03-07 | 2024-06-07 | 合肥晶合集成电路股份有限公司 | 静态随机存取存储器单元的制备方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1655364A (zh) * | 2003-12-30 | 2005-08-17 | 因芬尼昂技术股份公司 | 晶体管结构、存储单元及其阵列、及存储器制造方法 |
KR20050107698A (ko) * | 2004-05-10 | 2005-11-15 | 삼성전자주식회사 | 핀펫구조를 갖는 플래시 메모리 소자 및 그 제조방법 |
US20070235785A1 (en) * | 2006-04-06 | 2007-10-11 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
CN101183664A (zh) * | 2006-11-14 | 2008-05-21 | 国际商业机器公司 | 半导体结构及制造多个鳍片场效应晶体管的方法 |
Family Cites Families (88)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5289432A (en) | 1991-04-24 | 1994-02-22 | International Business Machines Corporation | Dual-port static random access memory cell |
US5828597A (en) | 1997-04-02 | 1998-10-27 | Texas Instruments Incorporated | Low voltage, low power static random access memory cell |
US6084820A (en) | 1999-01-06 | 2000-07-04 | Virage Logic Corporation | Dual port memory device with vertical shielding |
JP3226886B2 (ja) | 1999-01-29 | 2001-11-05 | エヌイーシーマイクロシステム株式会社 | 半導体記憶装置とその制御方法 |
US7358121B2 (en) | 2002-08-23 | 2008-04-15 | Intel Corporation | Tri-gate devices and methods of fabrication |
US6706571B1 (en) | 2002-10-22 | 2004-03-16 | Advanced Micro Devices, Inc. | Method for forming multiple structures in a semiconductor device |
US7378710B2 (en) * | 2002-12-19 | 2008-05-27 | International Business Machines Corporation | FinFET SRAM cell using inverted FinFET thin film transistors |
US7023056B2 (en) | 2003-11-26 | 2006-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory cell structure |
US7002258B2 (en) | 2003-12-03 | 2006-02-21 | Arm Physical Ip, Inc. | Dual port memory core cell architecture with matched bit line capacitances |
JP2005175415A (ja) | 2003-12-05 | 2005-06-30 | Taiwan Semiconductor Manufacturing Co Ltd | 集積回路デバイスとその製造方法 |
US6924561B1 (en) * | 2003-12-08 | 2005-08-02 | Advanced Micro Devices, Inc. | SRAM formation using shadow implantation |
KR100513405B1 (ko) | 2003-12-16 | 2005-09-09 | 삼성전자주식회사 | 핀 트랜지스터의 형성 방법 |
US7098491B2 (en) | 2003-12-30 | 2006-08-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protection circuit located under fuse window |
US7187036B2 (en) | 2004-03-31 | 2007-03-06 | Taiwan Semiconductor Manufacturing Company | Connection structure for SOI devices |
US6914338B1 (en) | 2004-04-06 | 2005-07-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory cell having conductive sill |
US7115920B2 (en) * | 2004-04-12 | 2006-10-03 | International Business Machines Corporation | FinFET transistor and circuit |
US7092309B2 (en) | 2004-04-30 | 2006-08-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Standby mode SRAM design for power reduction |
US7300837B2 (en) * | 2004-04-30 | 2007-11-27 | Taiwan Semiconductor Manufacturing Co., Ltd | FinFET transistor device on SOI and method of fabrication |
US20050247981A1 (en) | 2004-05-10 | 2005-11-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory device having shielded access lines |
US20050253287A1 (en) | 2004-05-11 | 2005-11-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dual-port SRAM cell structure |
US7257017B2 (en) | 2004-05-28 | 2007-08-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | SRAM cell for soft-error rate reduction and cell stability improvement |
US7112857B2 (en) | 2004-07-06 | 2006-09-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Devices with different electrical gate dielectric thicknesses but with substantially similar physical configurations |
US7176125B2 (en) | 2004-07-23 | 2007-02-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a static random access memory with a buried local interconnect |
US7365432B2 (en) | 2004-08-23 | 2008-04-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory cell structure |
US7026689B2 (en) | 2004-08-27 | 2006-04-11 | Taiwan Semiconductor Manufacturing Company | Metal gate structure for MOS devices |
US7286896B2 (en) | 2004-09-13 | 2007-10-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-function teach pendant for a semiconductor manufacturing environment |
US7244640B2 (en) | 2004-10-19 | 2007-07-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for fabricating a body contact in a Finfet structure and a device including the same |
US7250657B2 (en) | 2005-03-11 | 2007-07-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Layout structure for memory arrays with SOI devices |
US8405216B2 (en) | 2005-06-29 | 2013-03-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure for integrated circuits |
US7279375B2 (en) * | 2005-06-30 | 2007-10-09 | Intel Corporation | Block contact architectures for nanoscale channel transistors |
US7807523B2 (en) | 2005-07-01 | 2010-10-05 | Synopsys, Inc. | Sequential selective epitaxial growth |
US8466490B2 (en) | 2005-07-01 | 2013-06-18 | Synopsys, Inc. | Enhanced segmented channel MOS transistor with multi layer regions |
US7190050B2 (en) | 2005-07-01 | 2007-03-13 | Synopsys, Inc. | Integrated circuit on corrugated substrate |
US7265008B2 (en) | 2005-07-01 | 2007-09-04 | Synopsys, Inc. | Method of IC production using corrugated substrate |
US7605449B2 (en) | 2005-07-01 | 2009-10-20 | Synopsys, Inc. | Enhanced segmented channel MOS transistor with high-permittivity dielectric isolation material |
US7247887B2 (en) | 2005-07-01 | 2007-07-24 | Synopsys, Inc. | Segmented channel MOS transistor |
US7508031B2 (en) | 2005-07-01 | 2009-03-24 | Synopsys, Inc. | Enhanced segmented channel MOS transistor with narrowed base regions |
US7405994B2 (en) | 2005-07-29 | 2008-07-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dual port cell structure |
US7485934B2 (en) | 2005-10-25 | 2009-02-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated semiconductor structure for SRAM cells |
US7675124B2 (en) | 2006-02-24 | 2010-03-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory array structure with strapping cells |
US7723806B2 (en) | 2006-03-28 | 2010-05-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory cells and semiconductor memory device using the same |
US7586147B2 (en) | 2006-04-17 | 2009-09-08 | Taiwan Semiconductor Manufacturing Co. Ltd. | Butted source contact and well strap |
US7269056B1 (en) | 2006-04-27 | 2007-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Power grid design for split-word line style memory cell |
US7403413B2 (en) | 2006-06-28 | 2008-07-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multiple port resistive memory cell |
US7577040B2 (en) | 2006-07-18 | 2009-08-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dual port memory device with reduced coupling effect |
US7864561B2 (en) | 2006-07-28 | 2011-01-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Cell structure with buried capacitor for soft error rate improvement |
US7679947B2 (en) | 2006-08-02 | 2010-03-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor devices with source and bulk coupled to separate voltage supplies |
US7505354B2 (en) | 2006-08-10 | 2009-03-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Word line voltage control circuit for memory devices |
US7514757B2 (en) | 2006-08-31 | 2009-04-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory formation with reduced metallization layers |
US7468902B2 (en) | 2006-09-27 | 2008-12-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | SRAM device with a low operation voltage |
US7502273B2 (en) | 2006-09-27 | 2009-03-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Two-port SRAM with a high speed sensing scheme |
US7592675B2 (en) | 2006-10-02 | 2009-09-22 | Taiwan Semiconductor Manufacutring Company, Ltd. | Partial FinFET memory cell |
US7525868B2 (en) | 2006-11-29 | 2009-04-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multiple-port SRAM device |
US7692230B2 (en) | 2006-12-06 | 2010-04-06 | Taiwan Semiconductor Manufacturing Co. Ltd. | MRAM cell structure |
US7660149B2 (en) | 2006-12-07 | 2010-02-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | SRAM cell with separate read and write ports |
US7738282B2 (en) | 2007-02-15 | 2010-06-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cell structure of dual port SRAM |
US7529117B2 (en) | 2007-03-07 | 2009-05-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Design solutions for integrated circuits with triple gate oxides |
US8421130B2 (en) | 2007-04-04 | 2013-04-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for manufacturing SRAM devices with reduced threshold voltage deviation |
US7898037B2 (en) | 2007-04-18 | 2011-03-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact scheme for MOSFETs |
JP4461154B2 (ja) * | 2007-05-15 | 2010-05-12 | 株式会社東芝 | 半導体装置 |
US7939862B2 (en) | 2007-05-30 | 2011-05-10 | Synopsys, Inc. | Stress-enhanced performance of a FinFet using surface/channel orientations and strained capping layers |
US8883597B2 (en) | 2007-07-31 | 2014-11-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabrication of a FinFET element |
US8188537B2 (en) * | 2008-01-29 | 2012-05-29 | Unisantis Electronics Singapore Pte Ltd. | Semiconductor device and production method therefor |
US8283231B2 (en) | 2008-06-11 | 2012-10-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | finFET drive strength modification |
US7910453B2 (en) | 2008-07-14 | 2011-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Storage nitride encapsulation for non-planar sonos NAND flash charge retention |
US8153493B2 (en) | 2008-08-28 | 2012-04-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET process compatible native transistor |
US7829951B2 (en) * | 2008-11-06 | 2010-11-09 | Qualcomm Incorporated | Method of fabricating a fin field effect transistor (FinFET) device |
US8361871B2 (en) * | 2008-12-24 | 2013-01-29 | Intel Corporation | Trigate static random-access memory with independent source and drain engineering, and devices made therefrom |
US8737107B2 (en) | 2009-01-15 | 2014-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory circuits and routing of conductive layers thereof |
US7862962B2 (en) | 2009-01-20 | 2011-01-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit layout design |
US7989355B2 (en) | 2009-02-12 | 2011-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of pitch halving |
US8390033B2 (en) | 2009-02-23 | 2013-03-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal structure for memory device |
US8144540B2 (en) | 2009-04-14 | 2012-03-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Two-port 8T SRAM design |
US8053299B2 (en) | 2009-04-17 | 2011-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabrication of a FinFET element |
US8472227B2 (en) | 2010-01-27 | 2013-06-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuits and methods for forming the same |
US8189368B2 (en) | 2009-07-31 | 2012-05-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Cell structure for dual port SRAM |
US8009463B2 (en) | 2009-07-31 | 2011-08-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Cell structure for dual port SRAM |
US8399935B2 (en) | 2009-09-18 | 2013-03-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Embedded SRAM memory for low power applications |
US8120939B2 (en) | 2009-09-24 | 2012-02-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | ROM cell having an isolation transistor formed between first and second pass transistors and connected between a differential bitline pair |
US8174868B2 (en) | 2009-09-30 | 2012-05-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Embedded SRAM structure and chip |
US8258572B2 (en) | 2009-12-07 | 2012-09-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | SRAM structure with FinFETs having multiple fins |
US8218354B2 (en) | 2009-12-30 | 2012-07-10 | Taiwan Semicondcutor Manufacturing Co., Ltd. | SRAM word-line coupling noise restriction |
US8263451B2 (en) * | 2010-02-26 | 2012-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Epitaxy profile engineering for FinFETs |
US8399931B2 (en) | 2010-06-30 | 2013-03-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Layout for multiple-fin SRAM cell |
US8942030B2 (en) | 2010-06-25 | 2015-01-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for SRAM cell circuit |
US8675397B2 (en) | 2010-06-25 | 2014-03-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cell structure for dual-port SRAM |
US8212295B2 (en) | 2010-06-30 | 2012-07-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | ROM cell circuit for FinFET devices |
US8315084B2 (en) | 2010-03-10 | 2012-11-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fully balanced dual-port memory cell |
-
2010
- 2010-06-30 US US12/827,690 patent/US8399931B2/en active Active
-
2011
- 2011-04-02 CN CN2011100859632A patent/CN102315213B/zh active Active
-
2013
- 2013-03-12 US US13/797,190 patent/US8653630B2/en not_active Ceased
-
2016
- 2016-02-11 US US15/041,843 patent/USRE47409E1/en active Active
-
2019
- 2019-05-24 US US16/422,627 patent/USRE49203E1/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1655364A (zh) * | 2003-12-30 | 2005-08-17 | 因芬尼昂技术股份公司 | 晶体管结构、存储单元及其阵列、及存储器制造方法 |
KR20050107698A (ko) * | 2004-05-10 | 2005-11-15 | 삼성전자주식회사 | 핀펫구조를 갖는 플래시 메모리 소자 및 그 제조방법 |
US20070235785A1 (en) * | 2006-04-06 | 2007-10-11 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
CN101183664A (zh) * | 2006-11-14 | 2008-05-21 | 国际商业机器公司 | 半导体结构及制造多个鳍片场效应晶体管的方法 |
Cited By (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103208496A (zh) * | 2012-01-12 | 2013-07-17 | 台湾积体电路制造股份有限公司 | Sram单元和阵列 |
CN103208496B (zh) * | 2012-01-12 | 2016-03-09 | 台湾积体电路制造股份有限公司 | Sram单元和阵列 |
CN103854696B (zh) * | 2012-11-30 | 2016-12-28 | 台湾积体电路制造股份有限公司 | 含FinFET的SRAM单元 |
CN103854696A (zh) * | 2012-11-30 | 2014-06-11 | 台湾积体电路制造股份有限公司 | 含FinFET的SRAM单元 |
CN103915325A (zh) * | 2012-12-28 | 2014-07-09 | 格罗方德半导体公司 | 使用沟道自对准硅化物布线层的方法 |
CN103915325B (zh) * | 2012-12-28 | 2017-09-29 | 格罗方德半导体公司 | 使用沟道自对准硅化物布线层的方法 |
CN104576643A (zh) * | 2013-10-14 | 2015-04-29 | 格罗方德半导体公司 | 具有改进的沟道迁移率的三维晶体管 |
CN104576643B (zh) * | 2013-10-14 | 2022-04-01 | 格芯(美国)集成电路科技有限公司 | 具有改进的沟道迁移率的三维晶体管 |
US10340380B2 (en) | 2013-10-14 | 2019-07-02 | Globalfoundries Inc. | Three-dimensional transistor with improved channel mobility |
CN105355652A (zh) * | 2014-08-20 | 2016-02-24 | 台湾积体电路制造股份有限公司 | 金属栅极结构及其制造方法 |
US10056299B2 (en) | 2014-08-20 | 2018-08-21 | Taiwan Semiconductor Manufacturing Company Ltd. | Metal gate structure and manufacturing method thereof |
CN106206732A (zh) * | 2015-01-20 | 2016-12-07 | 台湾积体电路制造股份有限公司 | 半导体器件及其制造方法 |
CN106206732B (zh) * | 2015-01-20 | 2019-07-16 | 台湾积体电路制造股份有限公司 | 半导体器件及其制造方法 |
CN105938832A (zh) * | 2015-03-03 | 2016-09-14 | 三星电子株式会社 | 包括鳍形的集成电路器件 |
CN106067464B (zh) * | 2015-04-21 | 2020-05-12 | 三星电子株式会社 | 具有接触塞的半导体装置及其形成方法 |
CN109841587A (zh) * | 2015-04-21 | 2019-06-04 | 三星电子株式会社 | 具有接触塞的半导体装置 |
CN109841587B (zh) * | 2015-04-21 | 2020-02-28 | 三星电子株式会社 | 具有接触塞的半导体装置 |
CN106067464A (zh) * | 2015-04-21 | 2016-11-02 | 三星电子株式会社 | 具有接触塞的半导体装置及其形成方法 |
CN113192951A (zh) * | 2015-07-30 | 2021-07-30 | 三星电子株式会社 | 集成电路和集成电路组 |
CN113192951B (zh) * | 2015-07-30 | 2024-01-05 | 三星电子株式会社 | 集成电路和集成电路组 |
USRE49780E1 (en) | 2015-07-30 | 2024-01-02 | Samsung Electronics Co., Ltd. | Methods of designing a layout of a semiconductor device including field effect transistor and methods of manufacturing a semiconductor device using the same |
CN108281419B (zh) * | 2016-12-28 | 2021-06-01 | 台湾积体电路制造股份有限公司 | 无传输门的电路单元以及包括该单元的集成电路布局 |
CN108281419A (zh) * | 2016-12-28 | 2018-07-13 | 台湾积体电路制造股份有限公司 | 无传输门的电路单元以及包括该单元的集成电路布局 |
CN109216455A (zh) * | 2017-06-29 | 2019-01-15 | 台湾积体电路制造股份有限公司 | 半导体器件及其形成方法 |
US10867871B2 (en) | 2017-08-30 | 2020-12-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect structure for fin-like field effect transistor |
CN109427791A (zh) * | 2017-08-30 | 2019-03-05 | 三星电子株式会社 | 半导体器件 |
US11367663B2 (en) | 2017-08-30 | 2022-06-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect structure for fin-like field effect transistor |
CN109427791B (zh) * | 2017-08-30 | 2023-07-04 | 三星电子株式会社 | 半导体器件 |
CN109427743A (zh) * | 2017-08-30 | 2019-03-05 | 台湾积体电路制造股份有限公司 | 用于鳍式场效应晶体管的互连结构及其形成方法 |
CN110970395B (zh) * | 2018-09-28 | 2022-01-07 | 台湾积体电路制造股份有限公司 | 导电特征形成 |
CN110970395A (zh) * | 2018-09-28 | 2020-04-07 | 台湾积体电路制造股份有限公司 | 导电特征形成 |
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USRE49203E1 (en) | 2022-09-06 |
US20130200395A1 (en) | 2013-08-08 |
US8399931B2 (en) | 2013-03-19 |
CN102315213B (zh) | 2013-07-10 |
US8653630B2 (en) | 2014-02-18 |
USRE47409E1 (en) | 2019-05-28 |
US20120001197A1 (en) | 2012-01-05 |
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