JP5091932B2 - 非プレーナ型トランジスタを用いた半導体装置および製造方法 - Google Patents
非プレーナ型トランジスタを用いた半導体装置および製造方法 Download PDFInfo
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- JP5091932B2 JP5091932B2 JP2009217868A JP2009217868A JP5091932B2 JP 5091932 B2 JP5091932 B2 JP 5091932B2 JP 2009217868 A JP2009217868 A JP 2009217868A JP 2009217868 A JP2009217868 A JP 2009217868A JP 5091932 B2 JP5091932 B2 JP 5091932B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
Description
Claims (5)
- 半導体基板上の1つ以上のフィンを備える2つの非プレーナ型パスゲート・トランジスタと、
前記半導体基板上の1つ以上のフィンを備える2つの非プレーナ型プルアップ・トランジスタと、
前記半導体基板上の1つ以上のフィンを備える2つの非プレーナ型プルダウン・トランジスタと、
前記非プレーナ型プルアップ・トランジスタのフィンと前記非プレーナ型プルダウン・トランジスタとの間に幅を広げて形成されたアシスト・フィンによって、前記非プレーナ型プルアップ・トランジスタのフィンの一部と前記非プレーナ型プルダウン・トランジスタのフィンの一部とを電気的に接続する、前記半導体基板上の2つのアシスト・バーと、
を備えるスタティック・ランダム・アクセス・メモリ・セル。 - 前記アシスト・バーが、前記半導体基板の表面に実質的に平行で且つ前記プルダウン・トランジスタのフィンおよび前記プルアップ・トランジスタのフィンに実質的に平行な方向において前記半導体基板の表面に実質的に垂直に形成されている、請求項1のスタティック・ランダム・アクセス・メモリ・セル。
- 前記非プレーナ型プルダウン・トランジスタのフィンがn型FinMOSFETであり、前記非プレーナ型プルアップ・トランジスタのフィンがp型FinMOSFETであり、
前記プルダウン・トランジスタおよび前記パスゲート・トランジスタに含まれているフィンが2種類コンタクト・ホールのみを有し、一方のコンタクト・ホールはビット線をn型拡散層に電気的に接続し、他方のコンタクト・ホールはn型拡散層を接地ラインに電気的に接続する、
請求項1のスタティック・ランダム・アクセス・メモリ・セル。 - 2つの非プレーナ型パスゲート・トランジスタ、2つの非プレーナ型プルアップ・トランジスタ、および2つの非プレーナ型プルダウン・トランジスタを備えるスタティック・ランダム・アクセス・メモリ・セルのセル面積を減少させる方法であって、
前記非プレーナ型プルアップ・トランジスタのフィンの一部と前記非プレーナ型プルダウン・トランジスタのフィンの一部とをアシスト・バーによって電気的に接続することを備え、
前記非プレーナ型プルアップ・トランジスタのフィンの一部と前記非プレーナ型プルダウン・トランジスタのフィンの一部とをアシスト・バーによって電気的に接続することは、
前記非プレーナ型プルアップ・トランジスタのフィンと前記非プレーナ型プルダウン・トランジスタとの間にアシスト・フィンを形成し、
前記非プレーナ型プルアップ・トランジスタのフィンの一部が前記非プレーナ型プルダウン・トランジスタのフィンの一部にアシスト・バーによって電気的に接続されるように、アシスト・フィンの幅を広げてアシスト・バーを形成する、
ことを備える方法。 - アシスト・バーが、パスゲート・トランジスタ、プルダウン・トランジスタ、およびプルアップ・トランジスタのそれぞれの拡散層を電気的に接続する、請求項4の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/399,197 | 2009-03-06 | ||
US12/399,197 US8116121B2 (en) | 2009-03-06 | 2009-03-06 | Semiconductor device and manufacturing methods with using non-planar type of transistors |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010212653A JP2010212653A (ja) | 2010-09-24 |
JP5091932B2 true JP5091932B2 (ja) | 2012-12-05 |
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JP2009217868A Active JP5091932B2 (ja) | 2009-03-06 | 2009-09-18 | 非プレーナ型トランジスタを用いた半導体装置および製造方法 |
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US (2) | US8116121B2 (ja) |
JP (1) | JP5091932B2 (ja) |
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2009
- 2009-03-06 US US12/399,197 patent/US8116121B2/en active Active
- 2009-09-18 JP JP2009217868A patent/JP5091932B2/ja active Active
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2012
- 2012-01-06 US US13/344,656 patent/US20120108016A1/en not_active Abandoned
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US8116121B2 (en) | 2012-02-14 |
US20120108016A1 (en) | 2012-05-03 |
JP2010212653A (ja) | 2010-09-24 |
US20100224943A1 (en) | 2010-09-09 |
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