USRE47409E1 - Layout for multiple-fin SRAM cell - Google Patents
Layout for multiple-fin SRAM cell Download PDFInfo
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- USRE47409E1 USRE47409E1 US15/041,843 US201615041843A USRE47409E US RE47409 E1 USRE47409 E1 US RE47409E1 US 201615041843 A US201615041843 A US 201615041843A US RE47409 E USRE47409 E US RE47409E
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
- H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H01L27/11—
Definitions
- an embedded static random access memory (SRAM) device has become a popular storage unit of high speed communication, image processing and system-on-chip (SOC) products.
- SRAM static random access memory
- the amount of embedded SRAM in micro-processors and SOCs increases to meet the performance requirement in each new technology generation.
- Vt intrinsic threshold voltage
- CMOS complimentary metal-oxide-semiconductor
- SNM SRAM cell static noise margin
- the FinFET provides both speed and device stability.
- the FinFET has a channel (referred to as a fin channel) associated with a top surface and opposite sidewalls. Benefits can be provided from the additional sidewall device width (Ion performance) as well as better short channel control (sub-threshold leakage).
- the setting of single fin cell device faces cell ratio problems like beta ratio (Ipd/Ipg) or alpha ratio (Ipu/Ipg).
- beta ratio is defined as the ratio between pull-down transistor drive current and pass-gate transistor drive current.
- a high beta ratio greater than 1 is desired in order to improve the stability of the SRAM cell.
- SRAM cell voltage Vcc_min is a factor related to the write capability.
- the corresponding parameter is the ratio between pull-up transistor drive current and pass-gate transistor drive current, referred to as “alpha ratio.”
- the present disclosure provides a static random access memory (SRAM) cell.
- the SRAM cell includes a plurality of fin active regions formed on a semiconductor substrate, wherein the plurality of fin active regions include a pair adjacent fin active regions having a first spacing and a fin active region having a second spacing from adjacent fin active regions, the second spacing being greater than the first spacing; a plurality of fin field-effect transistors (FinFETs) formed on the plurality of fin active regions, wherein the plurality of FinFETs are configured to a first and second inverters cross-coupled for data storage and at least one port for data access; a first contact disposed between the first and second the fin active regions, electrically contacting both of the first and second the fin active regions; and a second contact disposed on and electrically contacting the third fin active region.
- FinFETs fin field-effect transistors
- the present disclosure also provides one embodiment of a semiconductor structure.
- the semiconductor structure includes a first and second fin active regions extended from a semiconductor substrate and spaced away from each other with a first distance; a third and fourth fin active regions extended from the semiconductor substrate and spaced away from each other with a second distance greater than the first distance; a first and second epitaxy features formed on the first and second fin active regions, respectively, wherein the first and second epitaxy features are laterally merged together; a third and fourth epitaxy features formed on the third and fourth fin active regions, respectively, wherein the third and fourth epitaxy features are separated from each other; a first contact disposed on the first and second epitaxy features merged together; and a second contact disposed on the third epitaxy feature, wherein the second contact is spaced away from the fourth epitaxy feature and is not electrically connected to the fourth fin active region.
- the present disclosure provides yet another embodiment of a static random access memory (SRAM) cell.
- the SRAM cell includes a first inverter including a first pull-up transistor (PU- 1 ) and a first and second pull-down transistors (PD- 1 and PD- 2 ); a second inverter including a second pull-up transistor (PU- 2 ) and a third and fourth pull-down transistors (PD- 3 and PD- 4 ), the second inverter being cross-coupled with the first inverter for data storage; a port including a first pass-gate transistor (PG- 1 ) and a second pass-gate transistor (PG- 2 ), the port being coupled with the first and second inverters for data access, wherein each of PD- 1 , PD- 2 , PD- 3 , PD- 4 , PG- 1 and PG- 2 includes a n-type fin field-effect transistor (nFinFET) and each of PU- 1 and PU- 2 includes a p-type fin
- FIGS. 1 to 4 are sectional views of a portion of a SRAM device constructed according to various aspects of the present disclosure in various embodiments.
- FIGS. 5 to 7 are top views of a SRAM device or a portion thereof constructed according to various aspects of the present disclosure in various embodiments.
- FIGS. 8 to 15 are sectional views of a portion of a SRAM device constructed according to various aspects of the present disclosure in various embodiments.
- FIG. 16 is a schematic view of a static random access memory (SRAM) device constructed according to various aspects of the present disclosure in one embodiment.
- SRAM static random access memory
- FIG. 1 is a sectional view of a semiconductor structure 50 as a portion of a SRAM cell constructed according to various aspects of the present disclosure.
- the semiconductor structure 50 includes a semiconductor substrate 52 .
- the semiconductor substrate 52 includes silicon. Alternatively, the substrate includes germanium, silicon germanium or other proper semiconductor materials.
- the semiconductor substrate 52 includes various isolation features 54 .
- One isolation feature is a shallow trench isolation (STI) formed in the substrate to separate various devices.
- the semiconductor substrate also includes various doped regions such as n-well and p-wells.
- the semiconductor structure 50 includes various fin active regions 56 and 58 . The fin active regions 56 and 58 are oriented in parallel.
- the fin active regions and the STI features can be formed in a processing sequence including forming trenches in the semiconductor substrate 52 and partially filling the trenches with a dielectric material. Alternatively, the trenches are completely filled with the dielectric material. Then a polishing process, such as chemical mechanical polishing (CMP) process is applied to remove the excessive dielectric material and planarize the surface. Thereafter, the formed STI features are partially removed to form the fin active regions using a selective etch such as hydrochloride (HF) wet etch.
- the processing sequence includes etching trenches in the semiconductor substrate 52 and filling the trenches by one or more dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride or combinations thereof.
- the filled trench may have a multi-layer structure such as a thermal oxide liner layer with silicon nitride filling the trench.
- the STI features are created using a process sequence such as: growing a pad oxide, forming a low pressure chemical vapor deposition (LPCVD) nitride layer, patterning an STI opening using photoresist and masking, etching a trench in the substrate, optionally growing a thermal oxide trench liner to improve the trench interface, filling the trench with CVD oxide, using chemical mechanical planarization (CMP) to etch back, and using nitride stripping to leave the STI structure.
- the semiconductor substrate 52 also includes various n-wells and p-wells formed in various fin active regions.
- a gate feature includes a gate dielectric layer 60 (such as silicon oxide) and a gate electrode 62 (such as doped polysilicon) disposed on the gate dielectric layer 60 .
- the gate feature alternatively or additionally includes other proper materials for circuit performance and manufacturing integration.
- the gate dielectric layer includes high-k dielectric material layer.
- the gate electrode includes metal, such as aluminum, copper, tungsten or other proper conductive material.
- the gate electrode includes a metal having proper work function to the associated FinFET.
- the gate can be formed by a gate-last process or a high-k-last process (a complete gate-last process).
- the semiconductor structure 50 includes a first region 64 for one or more FinFETs and a second region 66 for one or more FinFETs.
- FIG. 2 is another embodiment of a sectional view of the semiconductor structure 80 as a portion of a SRAM cell.
- the semiconductor structure 80 includes a semiconductor substrate 82 .
- the semiconductor substrate 82 includes silicon.
- the semiconductor substrate 82 includes germanium, silicon germanium or other proper semiconductor materials.
- the semiconductor structure 80 includes a dielectric layer 84 formed on the semiconductor substrate 82 for isolation.
- the dielectric layer 84 includes silicon oxide.
- the semiconductor structure 80 includes another semiconductor layer 86 , such as silicon, formed on the dielectric layer 84 , referred to as semiconductor on insulator (SOI).
- SOI semiconductor on insulator
- the SOI structure can be formed by a proper technology, such as separation by implanted oxygen (SIMOX) or wafer bonding to include the dielectric layer inside semiconductor material.
- SIMOX separation by implanted oxygen
- the semiconductor layer 86 is patterned to form fin active regions 88 and 90 .
- the fin active regions 88 and 90 are configured and oriented in parallel.
- the fin active regions 88 & 90 and the STI features can be formed in a processing sequence including forming a patterned mask layer on the semiconductor layer and etching the semiconductor layer through the openings of the patterned mask layer.
- the patterned mask layer can be a patterned photoresist layer or a patterned hard mask layer, such as a patterned silicon nitride layer.
- a gate feature includes a gate dielectric layer 92 (such as silicon oxide) and a gate electrode 94 (such as doped polysilicon) disposed on the gate dielectric layer 92 .
- the gate dielectric layer 92 includes high-k dielectric material layer.
- the gate electrode 94 includes metal, such as aluminum, copper, tungsten, or other proper conductive material.
- the semiconductor structure 80 includes a first region 96 for one or more FinFETs and a second region 98 for one or more FinFETs.
- the processing flow to form a SRAM cell including the pass-gate and pull-down devices, have the following steps: formation of fin active regions; well formation; gate formation; epitaxy growth; light doped drain (LDD) formation; pocket implant (pocket junction) formation; gate spacer formation; source/drain (S/D) dopant formation; interlayer dielectric (ILD) formation; gate replacement; forming contact holes; silicide formation and forming contacts.
- LDD light doped drain
- pocket junction pocket implant
- ILD interlayer dielectric
- the fin active regions 104 and 106 are configured to have a first spacing “D 1 .”
- the fin active region 108 is configured to have a second spacing “D 2 ” from adjacent fin active regions 106 and 110 .
- the second spacing D 2 is greater than the first spacing D 1 .
- the first spacing D 1 and the second spacing D 2 are referred to as narrow spacing and wide spacing, respectively.
- the semiconductor structure 100 further includes an interlayer dielectric (ILD) 112 disposed on the fin active regions and the isolation features.
- the ILD 112 includes one or more dielectric materials for providing isolation to interconnections.
- the ILD 112 includes silicon oxide formed by chemical vapor deposition (CVD).
- the ILD 112 includes a dielectric material of a low dielectric constant, such as a dielectric constant less than about 3.5.
- the ILD 112 includes silicon dioxide, silicon nitride, silicon oxynitride, polyimide, spin-on glass (SOG), fluoride-doped silicate glass (FSG), carbon doped silicon oxide, Black Diamond® (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB (bis-benzocyclobutenes), SiLK (Dow Chemical, Midland, Mich.), polyimide, and/or other suitable materials.
- the ILD 112 may be formed by a technique including spin-on, CVD, sputtering, or other suitable processes.
- the formation of various contacts includes forming contact holes in the ILD 112 and filling the contact hole with a conductive material.
- the contact holes can be formed by a lithography process and an etch process, such as plasma dry etch.
- a patterned photoresist layer is formed on the ILD 112 with various openings defining regions for the contact holes.
- the etch process is applied to the ILD 112 to form the contact holes using the patterned photoresist layer as an etch mask layer.
- a hard mask is formed using the patterned photoresist layer and the etch process is applied to the ILD 112 through the openings of the patterned hard mask layer.
- the contacts and other interconnect features include vias and metal lines to form an interconnect to electrically configure the FinFETs to functional circuits, such as a SARM cell or SRAM array.
- tungsten is used to form tungsten plug in the contact holes.
- the conductive material filled in the contact holes includes tungsten, aluminum, copper, other proper metals, or combinations thereof.
- the contacts further include a barrier layer formed on the sidewalls of the contact holes before filling the contact holes with conductive material. For example, a titanium nitride may be deposited on the sidewalls of the contact holes by sputtering.
- the metal material used to form silicide includes titanium, nickel, cobalt, platinum, palladium tungsten, tantalum or erbium in various embodiment.
- the method of forming contacts includes forming a patterned photoresist layer by a lithography process; etching the ILD 112 to form contact holes; forming silicide on fin active regions within the contact holes; forming a conductive material in the contact holes; and performing a CMP process to the ILD.
- the silicide includes titanium (Ti), cobalt (Co), nickel (Ni), molybdenum (Mo), platinum (Pt), or combinations thereof.
- the multilayer interconnection is further formed after the formation of the various contacts.
- the multilayer interconnection includes vertical interconnects, such as conventional vias in addition to the contacts and horizontal interconnect including metal lines.
- the various interconnection features may implement various conductive materials including copper, aluminum, tungsten and silicide.
- a damascene process is used to form copper related multilayer interconnection structure.
- a SRAM cell includes multiple fin active regions with varying spacing or pitch.
- the pitch of multiple fin active regions is defined as a dimension from one fin active region to an adjacent fin active region.
- the semiconductor structure 100 includes two types of contacts, the first type of contacts is designed to electrically contact two adjacent fin active regions having a smaller spacing, such as the first spacing D 1 .
- the second type of contacts is designed to electrically contact only one fin active region having a larger spacing (such as D 2 ) from the adjacent fin active regions.
- FIG. 4 is a sectional view of a semiconductor structure 120 having various FinFETs and contacts constructed according to various aspects of the present disclosure in another embodiment.
- the semiconductor structure 120 is a portion of a SRAM cell.
- the semiconductor structure 120 includes a semiconductor substrate 52 and isolation features 54 similar to the those of the semiconductor structure 100 in FIG. 3 .
- the semiconductor structure 120 includes various fin active regions 104 , 106 , 108 and 110 .
- the fin active regions 104 , 106 , 108 and 110 include a first portion extended from the semiconductor substrate 52 and a second portion formed on the first portion as epitaxy features 122 .
- the epitaxy features 122 include 122 a, 122 b, 122 c and 122 d formed on the fin active regions 104 , 106 , 108 and 110 , respectively.
- An interface 124 is formed between the epitaxy features 122 and first portion of the fin active regions.
- the first portion of the fin active regions and the epitaxy features include a same semiconductor material, such as silicon.
- the first portion of the fin active region include silicon and the epitaxy features include different semiconductor material(s) for strained effect.
- the epitaxy features 122 in a n-well include silicon germanium (SiGe) configured for p-type FinFETs.
- the epitaxy features 122 in a p-well include silicon carbide (SiC) or silicon configured for n-type FinFETs.
- the epitaxy features 122 are formed by one or more epitaxy steps.
- the isolation features 54 are formed by the STI technique; then the first portion of the fin active region extended from the semiconductor substrate 52 is recessed by an etching process; and then an epitaxy process is performed to form the second portion of the fin active regions.
- the epitaxy features 122 (as the second portion of the fin active regions) use various semiconductor materials (such as silicon germanium for p-type FinFETs and silicon carbide for n-type FinFETs), two epitaxy processes are implemented to respective fin active regions.
- the epitaxy process is implemented after the formation polysilicon gate stacks.
- the fin active regions 104 , 106 , 108 and 110 are configured with different spacing between adjacent fin active regions.
- the fin active regions 104 and 106 are configured to have a first spacing D 1 .
- the fin active region 108 is configured to have a second spacing D 2 from adjacent fin active regions 106 and 110 .
- the second spacing D 2 is greater than the first spacing D 1 .
- the respective epitaxy features 122 When the epitaxy features 122 are formed on the respective fin active regions, lateral epitaxy growth will enlarge the dimension of the fin active regions and narrow the spacing as illustrated in FIG. 4 .
- the respective epitaxy features For the fin active regions with the second spacing D 2 to the adjacent fin active regions, the respective epitaxy features have a spacing D 3 less than D 2 .
- the fin active regions 108 and 110 have the spacing D 3 between the respective epitaxy features 122 c and 122 d.
- the respective epitaxy features For the fin active regions with the first spacing D 2 , the respective epitaxy features have a narrow spacing or are even laterally merged (bridged) together.
- the epitaxy features 122 a and 122 b are merged together to form a continuous landing feature. Since the epitaxy features are formed after the formation of the polysilicon gate stacks, the epitaxy features will only be formed on the source and drain regions but not on a portion of the fin active regions wherein the polysili
- the semiconductor structure 120 includes an interlayer dielectric (ILD) 112 disposed on the fin active regions and the isolation features.
- ILD 112 is similar to that of the semiconductor structure 100 in FIG. 3 in terms of composition and formation.
- the semiconductor structure 120 further includes various contacts formed in the ILD 112 and configured to provide electrical routing.
- the present embodiment includes contacts 126 and 128 .
- the contact 126 is designed with a proper geometry and is disposed to electrically contact both epitaxy features 122 a and 122 b.
- the contact 126 is configured to land on the merged epitaxy features 122 a and 122 b. In this case, the contact 126 may have a less dimension than the contact 114 of FIG. 3 .
- the contact 128 is designed to land only on the epitaxy feature 122 c that has a larger spacing D 3 from the adjacent epitaxy features ( 122 b and 122 d). Similar to the contacts 114 and 116 of FIG. 3 , contacts 126 and 128 are designed to reduce the SRAM cell size without sacrificing the quality of the SRAM device.
- the formation of various contacts is similar to the formation of the contacts 114 and 116 of FIG. 3 and includes forming contact holes in the ILD 112 and filling the contact hole with a conductive material.
- the formation of the contacts 126 and 128 includes forming contact holes in the ILD 112 , forming silicide on the substrate within the contact holes and filling the contact hole with a conductive material.
- FIGS. 1 to 4 provide various portions of a SRAM cell and various embodiments of a same portion of the SRAM cell.
- FIGS. 1 and 2 provide sectional views of the SRAM cell along a gate stack in two different embodiment.
- FIGS. 3 and 4 provide sectional views of the SRAM cell along a source/drain region in two different embodiment.
- FIGS. 5 to 15 provide other embodiments of a SRAM cell according to various aspects of the present disclosure.
- FIG. 5 is a top view of a semiconductor structure 130 as a portion of a SRAM cell.
- the semiconductor structure 130 includes a n-well region 132 and a p-well region 134 .
- the semiconductor structure 130 includes multiple fin active regions 136 a through 136 e.
- the fin active regions 136 a and 136 b are disposed in the p-well region 134 for forming various n-type FinFETs (such as pull-down devices and/or pass-gate devices), and the fin active regions 136 c, 136 d and 136 e are disposed in the n-well region 132 for forming various p-type FinFETs (such as pull-up devices).
- a gate 138 is formed over the multiple fin active regions 136 a through 136 e.
- Various contacts 140 a through 140 e are formed on some fin active regions and the gate 138 .
- the contact 140 a is formed on drains of the n-type FinFETs associated the fin active regions 136 a and 136 b.
- the contact 140 e is formed on sources of the n-type FinFETs associated the fin active regions 136 a and 136 b.
- the contact 140 e is coupled to the complimentary power line Vss.
- the contact 140 b is formed on drains of the p-type FinFETs associated the fin active regions 136 c, 136 d and 136 e.
- the contact 140 d is formed on sources of the p-type FinFETs associated the fin active regions 136 c, 136 d and 136 e.
- the contact 140 d is coupled to the power line Vcc.
- the contact 140 c is formed on the gate 138 .
- the semiconductor structure 130 also includes metal lines 142 a, 142 b and 142 c.
- the metal line 142 a is coupled to the contact 140 e and the complimentary power line Vss.
- the metal line 142 b is coupled to the contact 140 d and the power line Vcc.
- the metal line 142 c is coupled to the contact 140 a and 140 a.
- a semiconductor structure 146 includes a semiconductor structure 52 ; isolation features 54 ; the fin active regions 136 c, 136 d and 136 e; gate dielectric 60 and the gate electrode 62 .
- Various features in the semiconductor structure 146 are similar to the corresponding features in the semiconductor structure 50 of FIG. 1 .
- a semiconductor structure 148 includes a semiconductor structure 82 ; a dielectric material layer 84 ; the fin active regions 136 c, 136 d and 136 e; gate dielectric 92 and the gate electrode 94 .
- Various features in the semiconductor structure 148 are similar to the corresponding features in the semiconductor structure 80 of FIG. 2 .
- a semiconductor structure 150 illustrates a right portion of the semiconductor structure 130 along the line bb′.
- the semiconductor structure 150 includes the semiconductor structure 52 ; the isolation features 54 ; the fin active regions 136 c, 136 d and 136 e; epitaxy features 122 ; and interlayer dielectric (ILD) 112 .
- An interface 124 is formed between the epitaxy features 122 and the fin active regions.
- Various features in the semiconductor structure 150 are similar to the corresponding features in the semiconductor structure 120 of FIG. 4 .
- the fin active regions 136 c, 136 d and 136 e have a large spacing D 2 and the epitaxy features 122 have a spacing D 3 less than D 2 .
- the epitaxy features may include silicon germanium for p-type FinFETs or silicon carbide for n-type FinFETs.
- a semiconductor structure 152 includes the semiconductor structure 52 ; the isolation features 54 ; the fin active regions 136 a and 136 b; epitaxy features 122 ; and the ILD 112 .
- the semiconductor structure 152 illustrates a left portion of the semiconductor structure 130 in FIG. 5 .
- Various features in the semiconductor structure 150 are similar to the corresponding features in the semiconductor structure 120 of FIG. 4 .
- the fin active regions 136 a and 136 b are similar to the fin active regions 104 and 106 of FIG. 4 .
- the fin active regions 136 a and 136 b have a smaller spacing D 1 .
- the epitaxy features 122 are similar to the epitaxy features 122 a and 122 b of FIG. 4 .
- the two adjacent epitaxy features 122 are merged together.
- the epitaxy features may include silicon germanium for p-type FinFETs or silicon carbide for n-type FinFETs.
- a semiconductor structure 154 includes the semiconductor structure 52 ; the isolation features 54 ; the fin active regions 156 a, 156 b and 156 c; epitaxy features 122 ; and the ILD 112 .
- Various features in the semiconductor structure 154 are similar to the corresponding features in the semiconductor structure 120 of FIG. 4 .
- the fin active regions 156 b and 156 c are similar to the fin active regions 104 and 106 of FIG. 4 .
- the fin active region 156 a is similar to the fin active region 108 of FIG. 4 .
- the fin active regions 156 b and 156 c have a smaller spacing S 1 .
- the epitaxy features 122 associated with the adjacent fin active regions 156 b and 156 c are merged together.
- the epitaxy feature 122 on the fin active region 156 a laterally expands but is separated from the adjacent epitaxy feature 122 with a distance.
- the silicon substrate 52 include silicon and the epitaxy features 122 include silicon as well.
- a semiconductor structure 158 includes the semiconductor structure 52 ; the isolation features 54 ; the fin active regions 160 a, 160 b and 160 c; epitaxy features 122 ; and the ILD 112 .
- Various features in the semiconductor structure 158 are similar to the corresponding features in the semiconductor structure 120 of FIG. 4 .
- the fin active regions 160 a, 160 b and 160 c are similar to the fin active regions 108 and 110 of FIG. 4 .
- the fin active regions 160 a, 160 b and 160 c have a larger spacing S 2 .
- the epitaxy features 122 laterally expand but are separated from the adjacent epitaxy feature 122 .
- the silicon substrate 52 include silicon and the epitaxy features 122 include silicon as well.
- FIG. 14 is a sectional view of the semiconductor structure 154 , similar to the FIG. 12 but further including a contact 126 .
- the contact 126 is disposed on the merged epitaxy features 122 and electrically connected to the two corresponding fin active regions 156 a and 156 b.
- the contact 126 is similar to the contact 126 of FIG. 4
- FIG. 15 is a sectional view of the semiconductor structure 158 , similar to the FIG. 13 but further including a contact feature 128 .
- the contact feature 128 lands on the epitaxy feature 122 of the fin active regions 160 b.
- the contact 128 is similar to the contact 128 of FIG. 4 .
- FIG. 6 is a top view of a semiconductor structure 160 as a portion of a SRAM cell.
- the semiconductor structure 160 includes multiple fin active regions 136 a through 136 c.
- the fin active regions 136 a, 136 b and 136 c are disposed in different well regions for different FinFETs.
- the fin active regions 136 a and 136 b are disposed in a p-well region for forming various n-type FinFETs (such as pull-down devices and/or pass-gate devices), and the fin active region 136 c is disposed in a n-well region for forming various p-type FinFETs (such as pull-up devices).
- a gate 138 is formed over the multiple fin active regions 136 a through 136 c.
- Various contacts 140 a through 140 g are formed on some fin active regions and the gate 138 .
- Various metal lines 142 a through 142 f are formed over the contacts and designed to couple with the respective contacts to form a functional circuit.
- the functional circuit includes one or more SRAM cells.
- the contact 140 a is designed to land on the fin active region 136 a and is coupled to the metal line 142 a.
- the contact 140 b is designed to land on the fin active region 136 b and is coupled to the metal line 142 b, and so on.
- the contact 140 g is designed to land on the gate 138 .
- the contact 140 a contacts a source region of a first FinFET and the contact 140 d contacts a drain region of the first FinFET.
- the contact 140 b contacts a source region of a second FinFET and the contact 140 e contacts a drain region of the second FinFET.
- the contact 140 c contacts a source region of a third FinFET and the contact 140 f contacts a drain region of the third FinFET.
- the contacts 140 a through 140 f are similar to the contact 128 of FIG. 4 .
- a sectional view of the semiconductor structure 160 along the line cc′ is shown, in portion, in FIG. 10 , which is described previously.
- FIG. 7 is a top view of a semiconductor structure 162 as a portion of a SRAM cell.
- the semiconductor structure 162 includes multiple fin active regions 136 a and 136 b.
- the fin active regions 136 a and 136 b are disposed in a well region (a n-well or a p-well).
- the fin active regions 136 a and 136 b are disposed in a p-well region for forming various n-type FinFETs (such as pull-down devices and/or pass-gate devices).
- a gate 138 is formed over the multiple fin active regions 136 a and 136 b to form the first and second FinFETs.
- Various contacts 140 a through 140 c are formed on the fin active regions and the gate 138 .
- Various metal lines 142 a and 142 b are formed over the contacts and designed to couple with the respective contacts to form a functional circuit.
- the contact 140 a is disposed between the two adjacent fin active regions 136 a and 136 b.
- the contact 140 a contacts both the adjacent fin active regions 136 a and 136 b.
- the contact 140 b is disposed between the two adjacent fin active regions 136 a and 136 b, and contacts both the adjacent fin active regions 136 a and 136 b.
- the contact 140 a is further coupled to the metal line 142 a.
- the contact 140 b is further coupled to the metal line 142 b.
- the contact 140 a contacts source regions of the first and second FinFETs and the contact 140 b contacts drain regions of the first and second FinFETs.
- a sectional view of the semiconductor structure 162 along the line dd′ is shown, in portion, in FIG. 11 , which is described previously.
- the processing flow to form a SRAM cell including the pass-gate, pull-down and pull-up devices, have the following steps: formation of fin active regions, well formation, channel dopant formation, gate formation, epitaxy growth to form epitaxy features, light doped drain (LDD) formation, gate spacer formation, source/drain (S/D) dopant formation, ILD deposition, gate replacement to form gate stacks having high-k dielectric material and metal gate electrode, etching to form contact holes, formation of silicide on source/drain regions and gates, forming contacts, and subsequent steps to form multilayer metal lines and vias.
- the epitaxy features are formed after the gate formation and are only formed on the source and drain regions.
- the fin active regions include portions underlying the gate stacks are free of the epitaxy semiconductor materials and are not enlarged laterally.
- the fin active regions are configured with different spacing.
- a SRAM cell includes two adjacent fin active regions having a small spacing D 1 and a fin active region having a larger spacing D 2 from the adjacent active regions.
- the two fin active regions with the smaller spacing D 1 include a further reduced spacing between the corresponding epitaxy features. In one case, the two epitaxy features are merged together.
- the SRAM cell also includes a first and second type of contacts.
- the first type of contacts each is formed between the two fin active regions with the smaller spacing D 1 and contacts the both two fin active regions.
- the second type of contacts each is disposed on a fin active region having the larger spacing D 2 from the adjacent fin active regions and contacts only the corresponding fin active region.
- FIG. 16 is a schematic view of a SRAM cell 170 constructed according to various aspects of the present disclosure in one embodiment.
- the SRAM cell 170 includes fin field-effect transistors (FinFETs).
- the SRAM cell 170 includes a first and second inverters that are cross-coupled as a data storage.
- the first inverter includes a first pull-up device formed with a p-type fin field-effect transistor (pFinFET), referred to as PU- 1 .
- the first inverter includes a first pull-down device formed with an n-type fin field-effect transistor (nFinFET), referred to as PD- 1 .
- pFinFET p-type fin field-effect transistor
- PD- 1 n-type fin field-effect transistor
- the drains of the PU- 1 and PD- 1 are electrically connected together, forming a first data node (“Node 1 ”).
- the gates of PU- 1 and PD- 1 are electrically connected together.
- the source of PU- 1 is electrically connected to a power line Vcc.
- the source of PD- 1 is electrically connected to a complimentary power line Vss.
- the second inverter includes a second pull-up device formed with a pFinFET, referred to as PU- 2 .
- the second inverter also includes a second pull-down device formed with an nFinFET, referred to as PD- 2 .
- the drains of the PU- 2 and PD- 2 are electrically connected together, forming a second data node (“Node- 2 ).
- the gates of PU- 2 and PD- 2 are electrically connected together.
- the source of PU- 2 is electrically connected to the power line Vcc.
- the source of PD- 2 is electrically connected to the complimentary power line Vss.
- the first data node is electrically connected to the gates of PU- 2 and PD- 2
- the second data node is electrically connected to the gates of PU- 1 and PD- 1 . Therefore, the first and second inverters are cross-coupled as illustrated in FIG. 16 .
- the SRAM cell 170 further includes a first pass-gate device formed with an n-type fin field-effect transistor (nFinFET), referred to as PG- 1 , and a second pass-gate device formed with an n-type fin field-effect transistor (nFinFET), referred to as PG- 2 .
- the source of the first pass-gate PG- 1 is electrically connected to the first data node and the source of the first pass-gate PG- 2 is electrically connected to the second data node, forming a port for data access.
- the drain of PG- 1 is electrically connected to a bit line (“BL”), and the gate of PG- 1 is electrically connected to a word line (“WL”).
- the drain of PG- 2 is electrically connected to a bit line bar (“BLB”), and the gate of PG- 2 is electrically connected to the word line WL.
- the various nFinFETs and pFinFETs are formed using high-k/metal gate technology so the gate stacks includes a high-k dielectric material layer for gate dielectric and one or more metals for gate electrode.
- the SRAM cell 170 may include additional devices, such as additional pull-down devices and pass-gate devices.
- each of the first and second inverters includes multiple pull-down devices formed on multiple fin active regions and configured in parallel. The multiple pull-down devices in parallel are configured such that the drains are connected together, the sources are connected together to the complimentary power line Vss, the gates are connected together.
- the fin active regions with the smaller spacing D 1 are implemented and the first type of contacts are formed on the closed disposed or merged epitaxy features.
- the cell 170 include an additional port having two or more pass-gate devices for additional data access, such as data reading or writing. Those pass-gate devices are configured in parallel and can also implement the configuration and design of the fin active regions and the first type of contacts similar to those for the pull-down devices in parallel.
- a pull-up device may implement the fin active region having the larger spacing D 2 from the adjacent fin active regions and the second type of contacts.
- a contact is designed to land on and contact multiple fin active regions tightly packed (e.g., with the smaller spacing D 1 ).
- the contact 140 d contacts three fin active regions 136 c, 136 d and 136 e.
- an epitaxy feature includes a raised structure having a top surface higher than the gate dielectric layer of the corresponding gate stack.
- the epitaxy feature with the raised structure is a silicon epitaxy feature.
- the two merged epitaxy features are two silicon epitaxy features. A silicide is formed on the two merged silicon epitaxy features so that the corresponding sources or drains are electrically connected together.
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Also Published As
Publication number | Publication date |
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CN102315213B (en) | 2013-07-10 |
US20130200395A1 (en) | 2013-08-08 |
US8399931B2 (en) | 2013-03-19 |
US8653630B2 (en) | 2014-02-18 |
CN102315213A (en) | 2012-01-11 |
USRE49203E1 (en) | 2022-09-06 |
US20120001197A1 (en) | 2012-01-05 |
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