TW427027B - Manufacturing method for MOS transistor - Google Patents

Abstract

The present invention provides a manufacturing method for MOS transistor on the silicon substrate surface of a semiconductor chip. The inventive method is firstly forming a silicon oxide on the silicon substrate surface; and, forming a polysilicon layer and a smaller silicon nitride on the surface of silicon oxide; then, forming a silicon oxide spacer around the polysilicon layer and silicon nitride; and, removing the silicon nitride on the inner side of the spacer; forming the source and the drain of MOS transistor on the silicon substrate on the outer side of the spacer; then, uniformly forming a conductive layer on the surface of semiconductor chip and filling the gap inside the spacer; then, employing the CMP to remove the top area of the spacer so that the conductive layer inside and outside the spacer can be separated by the spacer and forming the gate of the MOS transistor and the landing pad of the source and the drain respectively.

Description

Λ27027 5. Description of the invention (1) The present invention provides a method for manufacturing a MOS transistor, especially a method for simultaneously manufacturing a gate electrode of a MOS transistor and a source pad and a sink pad of a mS transistor.

The memory cell of dynamic random access memory (DRAM) is mainly composed of a metal oxide semiconductor (MOS) transistor, a capacitor, and an electrode contact. ). The M0S transistor is used as a switching transistor in the memory unit to control the transfer of charge. The capacitor is used to store the charge to memorize or output data. The electrode contact is a contact plug. (contact plug), which is used to smoothly connect the j (0s transistor) and the capacitor to form a memory unit. Please refer to FIG. 1 and FIG. 2 'FIG. 1 and FIG. Schematic diagram of the method. The MOS transistor 25 is fabricated on a silicon substrate 12 of a semiconductor wafer 10. As shown in the first figure, when a juqs transistor 25 is made, a hard oxygen layer 14 is formed on the dream substrate 12, Then, a gate electrode is formed on a predetermined area on the surface of the oxygen-containing layer 14, and then an ion implantation process is used to form a doped region 20 on the silicon substrate 12 on both sides of the gate electrode 16. 'Used as lightly doped drain (LDD) of MOS transistor 25 as shown in Figure 2' Next, a portion of the gate electrode 6 is formed by nitriding.

Page 4 * ΛΡ7 02Τ 5. Description of the invention (2) The spacer 22 made of silicon nitride. Then, the ion implantation process is performed again to form a thicker #hetero region on the silicon substrate 12 on the outer edge of the sidewall 22, which is used as the source or drain 24 of the M0S transistor 25 to complete the M0S transistor 25. Making. However, as the design of semiconductor devices is gradually shrinking, it is becoming more difficult to make electrode contacts in DRAMs using processes such as etching and deposition. Therefore, in the current semiconductor manufacturing process, a landing pad and another contact plug are usually formed at the bottom of the electrode contact to reduce the overall process difficulty of the electrode contact, thereby ensuring the electrical quality of the entire DRAM. Please refer to FIGS. 3 to 7. FIGS. 3 to 27 are schematic diagrams of a process for manufacturing the transfer pad 38 on the semiconductor wafer 10 shown in FIG. 2. When the transistor 25 is fabricated, it can start to make a transfer pad 38 above the source or drain 24. As shown in FIG. 3, a dielectric layer 26 made of silicon oxide is formed on the surface of the semiconductor wafer 10, and then a lithography process is used to form a dielectric layer 26 on the surface of the dielectric layer 26. The first photoresist layer 28 passes to the holes 30 on the surface of the dielectric layer 26. Then, as shown in Fig. 4, an anisotropic etching process is performed to remove the dielectric layer 26 below the hole 30 downward to form a contact hole 32. Subsequently, a photoresist removal process is performed to completely remove the first photoresist layer M on the surface of the semiconductor wafer 10. As shown in Figure 5, a conductive layer is uniformly formed on the surface of the semiconductor wafer 10.

Page 5 427027 V. Description of the invention (3) *-layer 34 and filling the contact hole 32 ^ Then as shown in FIG. 6, a second photoresist layer is formed on a predetermined area of the surface of the conductive layer 34 36, used to determine the position of the transfer pad 38. As shown in FIG. 7, the conductive layer 34 not covered by the second photoresist layer is removed, and then the second photoresist layer 36 is removed to complete the fabrication. The upper end of the conductive layer 34 protrudes from the dielectric layer 26. Copier is used as an adapter pad 38 for electrical connection to the storage node of a capacitor made later, and the pillar = part of the conductive layer 34 is used as a contact plug 37 Is used to electrically connect to the drain or source 24 on the 12 ^ side of the silicon substrate. However, it is known that when the transfer pad 38 is manufactured, the M0S transistor 25 is completed before the surface of the semiconductor wafer 10, and then the transfer is continued. The manufacturing process of the pad 38. Therefore, we must strictly control the yellow light process so as to form holes 30 in the first photoresist layer to accurately locate the position of the contact plug 37 so as to avoid the etching process of the dielectric layer 26. Due to the poor selection of tb by silicon nitride for silicon oxide etching, the surface of the adjacent gate 16 and its side wall 22 are mistakenly caused, causing the distance between the contact plug and the gate 16 to be too close, resulting in electricity. Electrical coupling effect, which affects the electric power of 1 > 1 ^ 14 Characteristic table: Secondly, it is convenient to form a conductive layer uniformly on the surface of the semiconductor wafer 10, so as to file your contact holes 32, and then a yellow light process must be performed again to locate the correct position of the transfer 塾 38. Therefore, the entire MAM process Will become quite complicated and difficult to control. Therefore, the main object of the present invention is to provide a MOS transistor.

Page 6 427027 V. Description of the invention (4) Manufacturing method 'It can not only manufacture gate and source of MOS transistor at the same time

And pads, and it can simplify the entire semiconductor manufacturing process and improve the electrical performance of the product. D Simple illustration of the diagram. Figures 1 and 2 are schematic diagrams of conventional methods for making MOS transistors. FIG. 3 to FIG. 7 are schematic diagrams of a process for fabricating a transfer pad on the semiconductor wafer shown in FIG. 2. Figures 8 to 17 are schematic diagrams of a method for making a MOS transistor according to the present invention. Symbols shown in the figure 40 semiconductor wafer 42 silicon substrate 44 silicon oxide layer 46 polycrystalline silicon layer 48 first dielectric layer 50 lightly doped drain 52 second dielectric layer 53 sidewalls 54 source and drain 56 conductive layer 58 Please refer to FIGS. 8 to 17 for the transition of the metal silicide layer 60. FIGS. 8 to 17 are schematic diagrams of a method for fabricating a MOS transistor according to the present invention. The invention provides a method for simultaneously fabricating a gate 47 of a MOS transistor and a switch 60 on a silicon substrate 42 of a semi-conductor wafer 40. Among them, the JIOS transistor is used as a switching transistor in a memory unit of dynamic random access memory.

A21021 V. Description of the invention (5) The upper end is used to connect the storage node or bit line of the storage capacitor (capacitor) of the memory cell. As shown in FIG. 8, the method of the present invention first forms a silicon oxide layer 44 on the surface of the silicon substrate 42, and then forms a poly-si 1 icon layer 46 on a predetermined area on the surface of the silicon oxide layer 44. . As shown in FIG. 9, a layer of nitrogen silicon compound is formed as a first dielectric layer 48 on a specific area of the surface of the polycrystalline silicon layer 46. Then, an ion implantation process is performed on the silicon substrates on both sides of the polycrystalline silicon layer 46. Two lightly doped regions 50 ′ are formed on 42 for lightly doped MOS transistors; and lightly doped drain (DDD) is shown in FIG. 10. As shown in FIG. 11 ', a silicon oxide layer is then uniformly formed on the surface of the silicon oxide layer 44, the polycrystalline silicon layer 46, and the first dielectric layer 48 as the second dielectric layer 52. As shown in FIG. 11 ', a silver etching process is performed to completely remove the second dielectric layer 52 above the surface of the first dielectric layer 48, and leave the polysilicon layer 46 and the first dielectric layer. A second dielectric layer 52 around the layer 48 forms a sidewall 53. As shown in FIG. 13 ', an etch process is then used to completely remove the first dielectric layer 48 above the polycrystalline silicon layer 46 and inside the sidewalls 53. Subsequently, as shown in FIG. 14 ', the ion implantation process is performed again to form a two-doped region 54 on the surface of the silicon substrate 42 on the outer edge of the side wall 53 to be used as a source and a drain 54 of the MOS transistor.

427 0 2 7 V. Description of the invention (6) As shown in Fig. 15, the next step is to facilitate the formation of an amorphous silicon layer, a polycrystalline silicon layer or an epitaxial silicon layer on the surface of the semiconductor wafer 10 uniformly ( ep it axy) layer and fills the space inside the side wall member 53 and is used as the conductive layer 56. Then, chemical mechanical polishing (CMP) is used to perform a planarization process on the surface of the conductive layer 56 to remove the conductive layer 56 on the top portion of the sidewall 53, so that the sidewall 5 3 is inside and outside. The conductive layers 56 can be isolated from each other by the screen effect of the side walls 53. Among them, the polycrystalline silicon layer 46 on the inner side of the side wall member 53 and the conductive layer 56 above it are used to compound the gate electrode 57 formed as a MOS transistor. Subsequently, an ion implantation process is performed, so that the conductive layer 56 is doped with HA group Boron (B) ions or va group arsenic (As) ions to reduce the resistance value of the conductive layer 56. As shown in FIG. 16, a self-aligned silicide (salicide) process is performed to form a metal silicide layer 58 on the surface of the conductive layer 56, thereby reducing the conductive layer 56. Sheet resistance on the surface. The Salicide process is to deposit a metal tungsten layer (not shown) on the surface of the semiconductor wafer 40, and then place the semiconductor wafer 40 in a high temperature environment to force the metal tungsten layer to react with the silicon conductive layer 56 to form. Tungsten silicon (WSiX), that is, the metal silicide layer 58 ^ The unreacted metal tungsten layer is then removed to complete the Salicide process.

F · 4 27 0 27 V. Description of the invention (7) As shown in FIG. 17, a yellow light and etching system are used to remove the conductive layer 56 and the metal silicide layer 58 in a specific area on the surface of the silicon substrate 42 ′. In order to isolate the MOS transistor phase from other elements on the surface of the silicon substrate 42 to avoid short circuits, although in the embodiment disclosed in the present invention described above, a nitrogen silicon compound is used as the first dielectric layer 48, and then silicon oxide is selected. As the second dielectric layer 52, but in practical applications, as long as the materials of the first dielectric layer and the second dielectric layer 52 are different, and can form a good etching selection ratio, The choice does not affect the applicability of the invention. For example, in the method of this month, silicon oxide can be used as the first dielectric layer, and then a nitrogen silicon compound can be used as the second dielectric layer 52 to form side lines to complete the entire MOS transistor process. In addition, since the present invention uses the polycrystalline silicon layer 46 and the conductive layer 56 inside the side wall 53 as the gate 47 of the MOS transistor, and then uses the side wall 53 as an isolation insulator to use the side wall 53 and The metal debris layer 58 is used as the transfer pad 6. . So this = need to carry out two | light system to define the correct position of the entire transition 塾 60 to make the gate 47 and the transition pad 60 of the M0S transistor at the same time, so that the entire semiconductor manufacturing process becomes It is relatively simple and easy to control, and it can better maintain the product quality of the semiconductor wafer 40. Compared with the conventional method of making M0S transistors and switching chirps, the present invention

Page 10 42702?

Claims (1)

42702? 6. Application scope of patent 1. A method for fabricating a metal oxide semiconductor (MOS) transistor on the surface of a semiconductor wafer. The surface of the semiconductor wafer includes a silicon substrate. The method includes the following steps: forming a dream oxygen layer on the surface of the dream substrate; forming a poly-silicon layer and a first dielectric layer on a predetermined region of the silicon oxide layer surface; the first dielectric The layer system is located on a specific area of the surface of the polycrystalline silicon layer; a second dielectric layer is uniformly formed on the surface of the silicon oxide layer, the polycrystalline silicon layer, and the first dielectric layer; and an etching back process is performed to Completely removing the second dielectric layer above the first dielectric layer, and forming a spacer on the polycrystalline silicon layer and the second dielectric layer surrounding the first dielectric layer; performing an etch (etch ) Process to completely remove the first dielectric layer on the inner side of the sidewall; performing an ion implantation process to form a two-doped region on a silicon substrate on the outer edge of the sidewall; Forming the source and drain of the M0S transistor; uniformly forming a conductive layer on the surface of the semiconductor wafer, and filling the space inside the side wall with the conductive layer; and performing a A planarization process planarizes the surface of the conductive layer and removes the top part of the sidewall at the same time. The conductive layers inside and outside the sidewall will be isolated from each other due to the sidewall, and will be located inside the sidewall. The polycrystalline silicon layer and the conductive layer above it are used as the Page 12 4 2 7 0 2 71 6. Scope of patent application Gate of M0S transistor. 2. As described in the manufacturing method of the patent claim 1, wherein the MOS transistor system is formed in a predetermined area on the surface of the silicon substrate, and the manufacturing method further includes the following steps after the planarization process is completed: The conductive layer at the edge of the predetermined region on the surface of the silicon substrate allows the MOS transistor to be isolated from other elements on the surface of the silicon substrate, and at the same time isolates the conductive layers located above the source and the drain from each other and located at the source. The electrode and the conductive layer above the electrode are used as the source and drain pads (1 andingpad), respectively. 3. The manufacturing method according to the scope of patent application 'wherein the MOS transistor system is a switching transistor (pass) in a memory unit (n! Emory ceU) of a dynamic random access memory (DRAM). transistor), and the upper end of the transfer pad is used to connect to the lower storage electrode (storage electrode) of the capacitor in the memory unit or a bit line of the DRAM. 4. The manufacturing method as claimed in claim 1, wherein before forming the second dielectric layer, an ion implantation process is further included to form a two-doped region on the stone substrate on both sides of the periphery of the polycrystalline silicon layer. It is a lightly doped drain (LDD) of the transistor. 5. The manufacturing method according to the scope of the patent application, wherein the planarization process is Page 13 427027 6. The scope of the patent application is a chemical mechanical polishing (CMP). 6. For the manufacturing method of the scope of patent application 1, the first dielectric layer is made of silicon oxide. SiO2), and the second dielectric layer is composed of silicon nitride (SiN). 7. The manufacturing method as claimed in claim 1, wherein the first dielectric layer is composed of silicon nitride and the second dielectric layer is composed of silicon oxide. 8. The manufacturing method as claimed in claim 1, wherein the conductive layer is composed of a poly-si 1 icon layer or an epitaxy layer. 9. The manufacturing method as claimed in claim 8, wherein the conductive layer contains a dopant of group IIIA or VA to reduce the resistance value of the conductive layer. 10. For example, the manufacturing method of patent scope 9 wherein the dopant of the melon a group is boron (Boron, B) ions, and the dopant of the VA group is arsenic, As. 11. The manufacturing method for applying for patent scope 10, wherein the surface of the conductive layer is further provided with a metal silicide layer 'for reducing the sheet resistance of the conductive layer- Page 14 6. Scope of patent application 1Z. For the manufacturing method of scope of patent application 11, the metal silicide layer is Tungsten Silicon (WSix). Page 15