CN101785097B - 电子零件 - Google Patents

电子零件 Download PDF

Info

Publication number
CN101785097B
CN101785097B CN2009801002317A CN200980100231A CN101785097B CN 101785097 B CN101785097 B CN 101785097B CN 2009801002317 A CN2009801002317 A CN 2009801002317A CN 200980100231 A CN200980100231 A CN 200980100231A CN 101785097 B CN101785097 B CN 101785097B
Authority
CN
China
Prior art keywords
conductivity
electronic component
grounding electrode
substrate
pressure section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN2009801002317A
Other languages
English (en)
Other versions
CN101785097A (zh
Inventor
大野和幸
田中祥雄
中岛清
鞍谷直人
前川智史
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MMI Semiconductor Co Ltd
Original Assignee
Omron Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Corp filed Critical Omron Corp
Publication of CN101785097A publication Critical patent/CN101785097A/zh
Application granted granted Critical
Publication of CN101785097B publication Critical patent/CN101785097B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/10Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48235Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a via metallisation of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015Shape
    • H01L2924/1016Shape being a cuboid
    • H01L2924/10162Shape being a cuboid with a square active surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/143Digital devices
    • H01L2924/1433Application-specific integrated circuit [ASIC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/162Disposition
    • H01L2924/16251Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/163Connection portion, e.g. seal
    • H01L2924/16315Shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/163Connection portion, e.g. seal
    • H01L2924/1632Disposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09818Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/099Coating over pads, e.g. solder resist partly over pads
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227Other objects, e.g. metallic pieces
    • H05K2201/10371Shields or metal cases
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

一种电子零件,通过基板(52)和导电性罩(54)构成用于收纳安装在基板(52)上表面的半导体元件的封装。在基板(52)的上表面外周部环状地形成接地电极(57)。由抗焊料剂(67)将接地电极(57)的内周部上表面覆盖。在导电性罩(54)的外周下端面形成有大致水平弯曲的凸缘(70)。将导电性罩(54)配置在基板(52)的上表面并且使凸缘(70)的下表面与抗焊料剂(67)的上表面抵接。另外,在抗焊料剂(67)的外周侧,在形成于凸缘(70)的下表面与接地电极(57)之间的空间填充导电性接合部件(73)而使导电性罩(54)与基板(52)接合。

Description

电子零件
技术领域
本发明涉及电子零件。具体地,涉及在封装内收纳有传感器芯片和电路等半导体元件的电子零件。
背景技术
作为在高频用封装中收纳有半导体元件的电子零件,例如具有专利文献1公开的部件。图1及图2是专利文献1公开的电子零件11的分解立体图及剖面图。该电子零件11利用金属罩14将在基板12上表面安装的半导体元件13的上方覆盖。安装在基板12上表面的半导体元件13通过接合线15而与焊盘16连接,焊盘16通过通孔22与背面的引出电极18连接。在基板12的上表面外周部以包围电路区域的方式设有环状的接地电极19,接地电极19通过通孔17而与基板12背面的接地图案20连接。金属罩14通过导电性树脂粘接剂21与接地电极19连接,机械地固定在接地电极19上的同时与接地电极19电连接。通过将连接金属罩14用的接地电极19设置在基板12的上表面,抑制引出电极18与金属罩14之间的电容C引起的对电路功能的影响。
但是,在专利文献1这样构造的电子零件11中,具有导电性树脂粘接剂21向内侧流出、由于导电性树脂粘接剂21而使半导体元件13短路的情况。即,在将金属罩14固定在基板12上时,沿接地电极19涂敷从注射器排出的导电性树脂粘接剂21,将导电性树脂粘接剂21夹入到接地电极19与金属罩14的外周部下表面之间,将金属罩14重合在基板12之上,进而压靠金属罩14。因此,在将金属罩14压靠在接地电极19上时,将导电性树脂粘接剂21从接地电极19与金属罩14之间挤出,向内侧流出的导电性树脂粘接剂21可能与信号输入输出用和供电用的焊盘16接触。由于导电性树脂粘接剂21与接地电极19接触而成为地电位,故而与焊盘16接触时使电路短路,成为要解决的课题。
为了避免上述不良情况,以往,使设有半导体元件13和焊盘16的区域与接地电极19的距离有足够的余量。但是,若将该距离增大,则电子零件11的设置面积(footprint)增大,电子零件11的尺寸增大。相反,若将电子零件11的尺寸减小,则容易产生由导电性树脂粘接剂21导致的短路。因此,电子零件11的小型化和短路防止处于折衷(trade-off)的关系。
在专利文献1这样构造的电子零件11中,由于导电性树脂粘接剂21的厚度偏差而使电子零件11的高度也容易产生偏差。即,在利用导电性树脂粘接剂21粘接金属罩14时,若较强地按压金属罩,则如上所述地导电性树脂粘接剂21会向内侧流出而产生短路,故而在粘接金属罩14时不能够充分按压金属罩14,因此,导电性树脂粘接剂21的厚度产生偏差。电子零件11的高度由基板12的厚度、金属罩14的高度和导电性树脂粘接剂21的厚度的合值来决定,故而若导电性树脂粘接剂21的厚度偏差则电子零件11的高度不固定。若导电性树脂粘接剂21的厚度大,则妨碍电子零件11的低高度化。相反,若厚度过小,则由树脂量不足和气泡的产生而导致粘接强度降低。
图3是表示专利文献2公开的电子零件31的剖面图。在该电子零件31中,在设于基板32上表面的岛部33安装有高频用半导体元件34,岛部33经由通孔35与背面的引出电极36连接。另外,半导体元件34的电极通过接合线37与基板32之上的焊盘38连接,焊盘38经由通孔39与背面的引出电极40连接。在基板32的上表面外周部,通过由划片切削而设有槽部41,在该槽部41之上重合有树脂罩42时,在槽部41与树脂罩42之间形成有树脂滞留部43。由此,在由粘接树脂44将树脂罩42的下表面和槽部41粘接时,多余的粘接树脂44被保持在树脂滞留部43,防止其向内部的半导体元件34侧流出。
但是,在这样构造的电子零件31中,必须由划片对基板32进行机械加工来制作槽部41,导致制造成本上升。另外,由于在制作基板32之后设置槽部41,故而难以在作为粘接部的槽部41设置导电图案,不利于金属罩和基板的导电图案(接地电极)的伴随导电的接合。另外,由于槽部41的机械加工偏差而导致电子零件31的高度偏差也增大。
专利文献1:(日本)特开2002-134639号公报
专利文献2:(日本)特开2002-110833号公报
发明内容
本发明是鉴于上述技术课题而作出的,其目的在于提供一种电子零件,通过利用导电性粘合部件将导电性罩接合在设于基板的接地电极上而构成半导体元件的封装,其中,通过低成本的方式能够防止导电性粘接树脂向内部流出,并且能够进一步减小高度偏差。
本发明的电子零件,在基板的上表面安装半导体元件,在所述基板上表面的包围所述半导体元件的区域形成接地电极,以将所述半导体元件覆盖的方式在所述基板之上重合导电性罩并通过导电性接合部件使所述导电性罩的下表面整个一周与所述接地电极接合在一起,其特征在于,所述导电性罩在下表面的一部分具有压抵部,在所述压抵部的外周侧,通过所述导电性接合部件将所述导电性罩的下表面和所述接地电极接合在一起。另外,由抗焊料剂和丝网图案等覆盖部件将所述接地电极的一部分覆盖,并且在被该覆盖部件覆盖的区域的外周侧,使所述接地电极的一部分从所述覆盖部件露出,将所述压抵部设置在所述覆盖部件的上表面。
在本发明的电子零件中,由于通过由基板和导电性罩构成的封装将安装在基板上表面的半导体元件覆盖而使导电性罩与接地电极导通,故而能够遮蔽内部的半导体元件不受外部的高频干扰的影响。另外,在导电性罩的下表面一部分设置压抵部,在该压抵部的外周侧通过导电性粘接部件使导电性罩的下表面和接地电极接合,故而导电性罩的下表面与接地电极之间的导电性接合部件由导电性罩的压抵部挡住,防止其流入到压抵部的内侧,或者即使导电性接合部件超过压抵部而浸入到内侧,也能够将其流入量抑制成少量。由此,能够防止导电性粘接部件浸入接地电极的内侧而使内部的电路短路。另外,由于能够将导电性罩相对于基板充分压靠,故而电子零件的高度大致由基板的厚度和导电性罩的高度之和来决定,能够降低电子零件的高度偏差。
根据该方面,与在接地电极的上表面配置压抵部的情况相比,能够将导电性罩下表面与接地电极之间的导电性接合部件的厚度增加与覆盖部件的厚度相当的量,能够使导电性罩更加可靠且牢固地与接地电极接合。
本发明的电子零件的另一方面,在所述导电性罩下表面的所述压抵部的外周侧,使所述导电性罩的下表面比所述压抵部更向上方凹陷。根据该方面,能够将导电性罩下表面与接地电极之间的导电性接合部件的厚度增加与导电性罩下表面凹陷的量相当的量,能够使导电性罩更加可靠且牢固地与接地电极接合。
本发明的电子零件的又一方面,所述导电性罩的下表面与所述接地电极之间的间隙随着朝向所述压抵部的外周侧而逐渐增大。根据该方面,能够将导电性罩下表面与接地电极之间的导电性粘合部件的厚度增大与导电性罩下表面与接地电极之间的间隙逐渐变大的量相当的量,能够使导电性罩更加可靠且牢固地与接地电极接合。
另外,在上述方面中,可以将所述压抵部配置在所述接地电极的上表面。在所述方面中,由于导电性罩的下表面凹陷、或导电性罩下表面与接地电极之间的间隙逐渐增大,故而即使在将压抵部配置在接地电极的上表面的情况下,也能够在导电性罩下表面与接地电极之间得到用于保持导电性接合部件的空间。
另外,本发明用于解决上述课题的方式,具有将以上的结构要素适当组合的特征,本发明通过将上述结构要素组合而可进行各种变更。
附图说明
图1是专利文献1公开的电子零件的分解立体图;
图2是专利文献1公开的电子零件的剖面图;
图3是专利文献2公开的电子零件的剖面图;
图4是表示本发明第一实施方式的电子零件的构造的剖面图;
图5是图4的X部放大图;
图6是表示电子零件的基板的俯视图;
图7是从电子零件的基板除去抗焊料剂后的状态的俯视图;
图8是电子零件的基板的仰视图;
图9(a)~(c)是用于说明导电性粘接树脂的涂敷方法的剖面图;
图10是表示第一实施方式的变形例的电子零件的一部分的剖面图;
图11是表示本发明第二实施方式的电子零件的结构的剖面图;
图12是图11的Y部放大图;
图13是表示第二实施方式的电子零件的不同组装状态的局部剖面图;
图14是表示第二实施方式的变形例的电子零件的一部分的剖面图;
图15是表示本发明第三实施方式的电子零件的结构的剖面图;
图16是表示本发明第四实施方式的电子零件的结构的剖面图;
图17是表示第四实施方式的变形例的电子零件的一部分的剖面图;
图18是表示本发明第五实施方式的电子零件的结构的剖面图;
图19是表示本发明第六实施方式的电子零件的结构的剖面图;
图20是表示第六实施方式的电子零件的基板的俯视图;
图21是表示从第六实施方式的基板除去抗焊料剂后的状态的俯视图;
图22是表示本发明第七实施方式的电子零件的构造的局部剖面图。
附图标记说明
51:电子零件
52:基板
53:半导体元件
54:导电性罩
55:岛部
57:接地电极
59:引出电极
67:抗焊料剂
68:装片树脂(ダイボンド樹脂)
69:接合线
70:凸缘
71:凹部
72:压抵部
73:导电性接合部件
81:电子零件
82:镀敷层
具体实施方式
以下,参照附图说明本发明的优选实施方式。
(第一实施方式)
图4是表示本发明第一实施方式的电子零件的结构的剖面图,图5是图4的X部放大图。另外,图6是基板的俯视图,图7是除去抗焊料剂(覆盖部件)后的状态的基板的俯视图,图8是基板的仰视图。这里所示的电子零件51在基板52的上表面安装半导体元件53,在由基板52和导电性罩54构成的封装(法拉第罩)中收纳有半导体元件53。
基板52由印刷基板构成,如图7所示,在基板52的上表面,通过对粘贴在绝缘板52a上表面的Cu等金属薄膜进行构图而形成有岛部55、焊盘56、接地电极57。接地电极57在基板52的外周部以包围岛部55和焊盘56的方式形成,焊盘56配置在岛部55附近。另外,在接地电极57内的区域中、没有岛部55和焊盘56的区域形成有表面侧接地图案58。这些岛部55、焊盘56、接地电极57、表面侧接地图案58通过槽61、62、63而相互分开。
如图6所示,岛部55的除去外周部的区域被用于保护金属薄膜表面的抗焊料剂67覆盖。表面侧接地图案58的表面也被抗焊料剂67覆盖。另外,在从接地电极57的内周部到绝缘板52a露出的部分的区域也形成有抗焊料剂67。例如,相对于宽度0.25mm的接地电极57,通过抗焊料剂67将接地电极57内周部的宽度0.10mm范围覆盖。这些抗焊料剂67通过网版印刷熔化状态的抗焊料剂而以均匀的厚度涂敷在基板52的表面,然后通过加热而使其固化。另外,在本实施方式中,作为覆盖部件而使用抗焊料剂,但除此之外,也可以使用丝网图案等。
另外,如图8所示,在基板52的下表面,通过对粘贴在绝缘板52a下表面的Cu等金属薄膜进行构图而形成有引出电极59和背面侧接地图案60。该引出电极59和背面侧接地图案60通过槽64而相互分开。这些引出电极59和背面侧接地图案60是用于将电子零件50钎焊安装在基板(例如携带电话用的母板)上的图案。
如图4所示,在绝缘板52a上以贯通表面背面的方式设有通孔,焊盘56通过通孔65而与引出电极59电连接,岛部55以及接地电极57通过通孔66与背面侧接地图案60连接。另外,表面侧接地图案58可以同样地通过通孔而与背面侧接地图案60连接,或者表面侧接地图案58可以从地面电气地浮起,或者也可以不设置表面侧接地图案58。不过,由于通过使表面背面的金属薄膜的面积大致相等而能够防止基板52的翘曲,故而设有表面侧接地图案58为好。
半导体元件53是各种传感检测用的传感器芯片、LSI、ASIC等元件,通过装片树脂(ダイボンド樹脂)68而粘接固定在岛部55以及其上表面的抗焊料剂67之上。作为装片树脂68,使用硅酮、环氧等粘接树脂,装片树脂68将来自外部环境的多余力阻断。半导体元件53的端子和焊盘56通过接合线69而连接,由此,半导体元件53的端子与下表面的引出电极59导通。另外,在基板52的上表面可以安装有多个半导体元件,也可以安装其他电子零件。另外,金属薄膜的图案根据安装的半导体元件和电子零件等的形式而适当自由设计。
导电性罩54由电阻率小的金属材料形成罩状,在下表面形成有用于收纳半导体元件53等的空间。在导电性罩54的下端部整个一周形成有大致水平延伸的凸缘70。在凸缘70下表面的前端侧,遍及整个一周而设有凹部71,在凸缘70的下表面、在凹部71的深处(导电性罩54的内部侧),遍及整个一周而形成有凸部状的压抵部72。
该导电性罩54通过对金属板进行压力加工而制成,凹部71也在压力加工时同时形成。由此,与通过切削加工形成凹部71的情况相比,能够低成本且尺寸偏差小地形成凹部71。
导电性罩54覆盖半导体元件53等而载置在基板52之上,凸缘70下表面的压抵部72遍及整个一周而与接地电极57上的抗焊料剂67抵接。在凸缘70的凹部71与接地电极57及抗焊料剂67之间的空间填充导电性接合部件73,导电性罩54通过导电性接合部件73与接地电极57接合固定,通过导电性接合部件73的导电性而与接地电极57电连接并且与下表面的背面侧接地图案60同电位(地电位)。作为导电性接合部件73,使用导电性环氧树脂(例如含有银填充剂的环氧树脂)和焊料等材料。
根据这样的电子零件51,通过接地的导电性罩54和具有接地的背面侧接地图案60的基板52而构成法拉第罩(ファラデ一ケ一ジ),故而能够阻断来自外部的高频干扰,能够降低半导体元件53受到外部干扰的影响。另外,封装可以根据收纳的半导体元件53的种类而构成密封结构,也可以不是密封结构。例如,在需要耐湿性、耐药品性的情况下,封装具有气密性为好。或者,在只要将来自外部的灰尘、光等阻断即可的情况下,只要由封装将半导体元件53等覆盖即可,气密性不是必要因素。或者,在作为半导体元件53而安装有音响传感器等的情况下,可以在导电性罩54的顶部等开设用于使音响振动通过的孔。
在导电性接合部件73形成通过空隙等将封装的外侧和内侧相连的孔。但是,若如本实施方式这样地使导电性罩54和基板52直接接触,并且在其外周侧形成牢固的接合部件滞留部(倒角),则能够阻断导电性罩54与基板52的接合部分的通气。由此,在封装要求气密性的情况下,能够提高其气密性。
另外,在该电子零件51中,如图5所示,凸缘70下表面的压抵部72与抗焊料剂67抵接而使压抵部72及抗焊料剂67在导电性接合部件73的内侧构成壁,故而在接合导电性罩54时,能够防止熔化状态的导电性接合部件73向内部流入,并且能够防止流入到内部的导电性接合部件73与焊盘56等电路部分接触而引起短路。另外,填充导电性接合部件73的空间的厚度为抗焊料剂67的厚度与凹部71的高度之和,故而可获得导电性接合部件73的厚度,能够以足够量的导电性接合部件73进行接合并且可防止气泡的产生,可将导电性罩54牢固地接合在基板52上。另外,凸缘70的压抵部72直接与抗焊料剂67的上表面抵接,故而电子零件51的高度与导电性接合部件73的厚度无关而由基板52的厚度和导电性罩54的高度来决定,并且,抗焊料剂67的厚度可利用网版印刷时的丝网厚度而获取精度,故而可降低电子零件51的高度尺寸偏差,并且可得到电子零件51的高度精度。
使接地电极57的一部分从抗焊料剂67露出是为了通过导电性接合部件73而使接地电极57和导电性罩54电导通。另外,由于导电性接合部件73相对于抗焊料剂67的润湿角小,故而若利用抗焊料剂67覆盖至接地电极57的外侧端,则导电性接合部件73会向导电性接合部件73的外周侧流出。导电性接合部件73与抗焊料剂67相比,相对于接地电极57(无机材料)的润湿角大,故而如本实施方式这样地使接地电极57的外周侧从抗焊料剂67露出的话,导电性接合部件73不易向接地电极57的外周侧漏出。
图9是用于说明使导电性罩54与基板52接合而组装电子零件51的顺序的剖面图。图9(a)局部所示的压模74(转印针)对应于接地电极57的形状而形成环状乃至筒状。导电性接合部件73如图9(a)所示地涂敷在压模74的下表面之后,将压模74靠压在接地电极57未被抗焊料剂67覆盖的区域,由此而转印在该区域。接着,在使凸缘70与接地电极57位置对齐的状态下将导电性罩54重合在基板52上,如图9(b)所示地由凹部71按压导电性接合部件73,如图9(c)所示地使压抵部72与抗焊料剂67的上表面抵接。此时,导电性接合部件73被凸缘70按压而向凹部71与接地电极57之间的空间扩展,但是该空间的内侧端被由压抵部72和抗焊料剂67形成的壁堵住,故而导电性接合部件73向导电性罩54的内侧流入。
另外,导电性接合部件73可以通过注射器等而沿接地电极57涂敷。
(第一实施方式的变形例)
图10是表示第一实施方式的变形例的电子零件的一部分的剖面图。在该变形例中,将覆盖引出电极59的抗焊料剂67除去,使凸缘70的压抵部72与引出电极59的表面抵接。在该实施方式中,填充在凸缘70与引出电极59之间的导电性接合部件73的厚度与凹部71的高度相同,比第一实施方式的情况稍薄。另外,填充在凸缘70与引出电极59之间的导电性接合部件73使位于其内侧的压抵部72成为壁,故而不会使导电性接合部件73向导电性罩54的内侧流入。
另外,在第一实施方式中,可以由镀Au等的镀敷层将引出电极59从抗焊料剂67露出的面覆盖。在变形例中,也可以由镀Au等的镀敷层将引出电极59的表面覆盖。
(第二实施方式)
图11是表示本发明第二实施方式的电子零件的结构的剖面图。图12是图11的Y部放大图。第二实施方式的电子零件81与第一实施方式的电子零件51的不同之处在于:在第二实施方式的电子零件81中,在导电性罩54的凸缘70不设置凹部71,压抵部72平坦。
在第二实施方式的电子零件81中,凸缘70下表面的弯曲部附近成为压抵部72,使该压抵部72与抗焊料剂67的上表面抵接,通过被夹入在凸缘70与接地电极57之间的导电性接合部件73将导电性罩54与接地电极57接合并且电连接。
由此,在该结构中,导电性接合部件73的厚度与抗焊料剂67大致相同(约20μm左右),比第一实施方式的情况稍薄。但是,此时在抗焊料剂67的内侧,抗焊料剂67的端面成为壁而防止抗焊料剂67向导电性罩54的内部流入,故而不会由流入到内部的导电性接合部件73引起短路。另外,此时,凸缘70与抗焊料剂67抵接,电子零件81的高度与导电性接合部件73的厚度无关而由基板52的厚度和导电性罩54的高度来决定,故而能够降低电子零件81的高度偏差。
另外,根据导电性罩54的接合方式,在凸缘70的一部分或整个一周,如图13所示地导电性接合部件73由于毛细管现象等而会浸入到压抵部1与抗焊料剂67之间。此时,严格意义上,压抵部72不与抗焊料剂67抵接。但是,由于导电性接合部件73涂敷在压抵部72的外侧且压抵部72被足够强地压靠在抗焊料剂67上,故而即使导电性接合部件73浸入到压抵部72与抗焊料剂67之间,其膜厚也非常薄,导电性接合部件73由表面张力而被保持在压抵部72与抗焊料剂67之间,故而几乎不会有由于导电性接合部件73向内侧流入而使半导体元件53等短路的可能性。另外,由于即使导电性接合部件73浸入到压抵部72与抗焊料剂67之间、导电性接合部件73也不会引起短路,故而能够将导电性罩54足够强地压靠在基板52上,能够将浸入的导电性接合部件73的膜厚充分减薄。因此,实质上,可以说压抵部72与抗焊料剂67抵接,此时也能够减小电子零件51的高度偏差(关于上述方面,与第一实施方式等其他实施方式同样)、
(第二实施方式的变形例)
图14是表示第二实施方式的变形例的电子零件的一部分的剖面图。在该变形例中,通过由镀Au等不锈性金属构成的镀敷层82将接地电极57的表面中从抗焊料剂67露出的区域覆盖,保护接地电极57。
(第三实施方式)
图15是表示本发明第三实施方式的电子零件的构造的剖面图。在该电子零件中,使凸缘70的前端(外周端缘)向斜上方倾斜或弯曲(点划线是将凸缘70的下表面延长的线段),使凸缘70基部的压抵部72与抗焊料剂67的上表面抵接。由此,能够使凸缘70下表面与接地电极57之上的镀敷层82之间的空间的厚度比抗焊料剂67的厚度大。结果,能够增大导电性接合部件73的厚度,可提高导电性罩54的接合强度。
在该实施方式中,可以不设置覆盖接地电极57的抗焊料剂67。由于凸缘70倾斜或弯曲,故而即使凸缘70基部的压抵部72直接与接地电极57抵接,在凸缘70的外周部与接地电极57之间也产生空间(间隙),能够在该空间中填充导电性接合部件73而使导电性罩54接合在基板52上。
(第四实施方式)
图16是表示本发明第四实施方式的电子零件的结构的剖面图。在该实施方式中,使用在凸缘70形成有凹部71和压抵部72的导电性罩54。并且,使导电性罩54的压抵部72在接地电极57的内侧与绝缘板52a的表面抵接。在抵接部分的外周侧,通过覆盖接地电极57而涂敷的导电性接合部件73,将凹部71的内面和基板52接合。
(第四实施方式的变形例)
图17是表示第四实施方式的变形例的电子零件的一部分的剖面图。在该变形例中,在接地电极57的内周侧从接地电极57离开而在绝缘板52a的上表面形成有抗焊料剂67。该抗焊料剂67与接地电极57平行而形成环状。并且,使凸缘70基部的压抵部72与抗焊料剂67的上表面抵接,在抗焊料剂67的外周侧,通过覆盖接地电极57而涂敷的导电性接合部件73,将压抵部72和基板52接合。
(第五实施方式)
图18是表示本发明第五实施方式的电子零件的结构的剖面图。在该实施方式的电子零件91中,使用树脂(例如液晶聚合物)形成罩状的树脂模制件的罩主体92的整个表面(外面及内面)被导电膜93(例如一层或多层镀敷膜)覆盖而构成导电性罩54。
另外,虽未作图示,导电膜93可以遍及罩主体92的整个面而设置在罩主体92的内部。此时,只要使导电膜93的一部分在凸缘70的下表面露出而与接地电极57导通即可。
(第六实施方式)
图19是表示本发明第六实施方式的电子零件的结构的剖面图。图20是表示安装有半导体元件53的基板52的俯视图,图21是表示形成抗焊料剂67之前的基板52的俯视图。用于该实施方式的电子零件101的基板52,如图21所示,将岛部55和表面侧接地图案58以及接地电极57一体形成。即,不设置第一实施方式的槽61、63。结果,仅焊盘56由槽62分开。伴随于此,抗焊料剂67也如图20所示地,在接地电极57的除了外周部(涂敷导电性接合部件73的区域)和焊盘56之外的整个金属薄膜区域形成。
(第七实施方式)
图22是表示本发明第七实施方式的电子零件的结构的局部剖面图。在该实施方式中,使导电性罩54的下端部朝向外周侧稍弯折或弯曲而设有弯曲部102,将弯曲部102的前端部下表面作为压抵部72。在该实施方式中不存在水平的凸缘70,在压抵部72的外周侧不存在足够长的区域,但在该实施方式中,如图22所示,能够在压抵部72的外周侧的弯曲部102前端面与接地电极57之间保持导电性接合部件73而将导电性罩54与接地电极57接合。

Claims (4)

1.一种电子零件,在基板的上表面安装半导体元件,在所述基板上表面的包围所述半导体元件的区域形成接地电极,以将所述半导体元件覆盖的方式在所述基板之上重合导电性罩并通过导电性接合部件使所述导电性罩的下表面整个一周与所述接地电极接合在一起,其特征在于,
所述导电性罩在下表面的一部分具有压抵部,在所述压抵部的外周侧,通过所述导电性接合部件将所述导电性罩的下表面和所述接地电极接合在一起,
由覆盖部件将所述接地电极的一部分覆盖,并且在被所述覆盖部件覆盖的区域的外周侧,使所述接地电极的一部分从所述覆盖部件露出,在所述覆盖部件的上表面配置有所述压抵部。
2.如权利要求1所述的电子零件,其特征在于,在所述导电性罩下表面的所述压抵部的外周侧,使所述导电性罩的下表面比所述压抵部更向上方凹陷。
3.如权利要求1所述的电子零件,其特征在于,所述导电性罩的下表面与所述接地电极之间的间隙随着朝向所述压抵部的外周侧而逐渐增大。
4.如权利要求2或3所述的电子零件,其特征在于,在所述接地电极的上表面配置有所述压抵部。
CN2009801002317A 2008-07-01 2009-02-16 电子零件 Active CN101785097B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP172109/08 2008-07-01
JP2008172109A JP5277755B2 (ja) 2008-07-01 2008-07-01 電子部品
PCT/JP2009/000608 WO2010001503A1 (ja) 2008-07-01 2009-02-16 電子部品

Publications (2)

Publication Number Publication Date
CN101785097A CN101785097A (zh) 2010-07-21
CN101785097B true CN101785097B (zh) 2011-11-30

Family

ID=41465613

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2009801002317A Active CN101785097B (zh) 2008-07-01 2009-02-16 电子零件

Country Status (6)

Country Link
US (1) US8314485B2 (zh)
EP (1) EP2187435B1 (zh)
JP (1) JP5277755B2 (zh)
KR (1) KR101101562B1 (zh)
CN (1) CN101785097B (zh)
WO (1) WO2010001503A1 (zh)

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011074550A1 (ja) 2009-12-15 2011-06-23 三菱化学株式会社 有機電界発光素子の製造方法、有機電界発光素子、表示装置及び照明装置
CN102185580A (zh) * 2010-01-18 2011-09-14 精工爱普生株式会社 电子装置、基板的制造方法以及电子装置的制造方法
JP5253437B2 (ja) * 2010-02-26 2013-07-31 日本電波工業株式会社 表面実装用の水晶振動子
JP2011187518A (ja) * 2010-03-05 2011-09-22 Nippon Telegr & Teleph Corp <Ntt> 半導体装置およびその製造方法
JP5463173B2 (ja) * 2010-03-12 2014-04-09 日立オートモティブシステムズ株式会社 角速度検出装置
JP2011233703A (ja) * 2010-04-27 2011-11-17 Daishinku Corp 電子部品パッケージ、及び電子部品パッケージの製造方法
JP5368377B2 (ja) * 2010-06-02 2013-12-18 三菱電機株式会社 電子部品パッケージおよびその製造方法
KR101179399B1 (ko) * 2010-10-04 2012-09-04 삼성전기주식회사 크로스토크를 저감하기 위한 인쇄회로기판
WO2012074775A1 (en) 2010-11-19 2012-06-07 Analog Devices, Inc. Packaged integrated device with electrically conductive lid
US20120263978A1 (en) * 2011-04-14 2012-10-18 Chung-Hsiung Wang Energy storage device and method of manufacturing the same
ITTO20110876A1 (it) * 2011-09-30 2013-03-31 Stmicroelectronics Malta Ltd Metodo di saldatura di un cappuccio ad uno strato di supporto
JP5915265B2 (ja) * 2012-03-02 2016-05-11 日本電気株式会社 電子部品及び電子部品の製造方法
WO2013172443A1 (ja) * 2012-05-18 2013-11-21 株式会社村田製作所 電子部品及びその製造方法
JP2014072346A (ja) * 2012-09-28 2014-04-21 Nec Corp 中空封止構造及び中空封止構造の製造方法
JP6036303B2 (ja) * 2013-01-07 2016-11-30 セイコーエプソン株式会社 パッケージ、光学モジュール、及び電子機器
US20140238726A1 (en) * 2013-02-28 2014-08-28 Cooper Technologies Company External moisture barrier package for circuit board electrical component
JP2015056606A (ja) * 2013-09-13 2015-03-23 株式会社東芝 半導体装置
US9736925B2 (en) * 2014-01-31 2017-08-15 Stmicroelectronics S.R.L. Packaged semiconductor device having a shielding against electromagnetic interference and manufacturing process thereof
US20150255365A1 (en) * 2014-03-05 2015-09-10 Nvidia Corporation Microelectronic package plate with edge recesses for improved alignment
JP6314731B2 (ja) 2014-08-01 2018-04-25 株式会社ソシオネクスト 半導体装置及び半導体装置の製造方法
JP6179681B2 (ja) * 2015-01-08 2017-08-16 株式会社村田製作所 圧電振動部品の製造方法
WO2016144039A1 (en) 2015-03-06 2016-09-15 Samsung Electronics Co., Ltd. Circuit element package, manufacturing method thereof, and manufacturing apparatus thereof
US10916520B2 (en) 2015-06-10 2021-02-09 Mitsubishi Electric Corporation Semiconductor device, and method of manufacturing the same
US9870967B2 (en) * 2016-03-10 2018-01-16 Analog Devices, Inc. Plurality of seals for integrated device package
US10477737B2 (en) 2016-05-04 2019-11-12 Samsung Electronics Co., Ltd. Manufacturing method of a hollow shielding structure for circuit elements
KR102481868B1 (ko) * 2016-05-04 2022-12-28 삼성전자주식회사 이종의 회로 소자군용 중공 차폐구조 및 그 제조방법
DE102016214277A1 (de) * 2016-08-02 2018-02-08 Continental Automotive Gmbh Leiterplatte und Sensor
US10477687B2 (en) 2016-08-04 2019-11-12 Samsung Electronics Co., Ltd. Manufacturing method for EMI shielding structure
CN106455463A (zh) * 2016-09-30 2017-02-22 奇酷互联网络科技(深圳)有限公司 一种屏蔽装置、屏蔽装置制造方法及电子设备
KR102572559B1 (ko) * 2017-01-25 2023-09-01 삼성전자주식회사 전자파 차폐구조
JP6974787B2 (ja) 2016-12-12 2021-12-01 株式会社村田製作所 圧電振動子、モジュール部品及びそれらの製造方法
JP6817858B2 (ja) * 2017-03-17 2021-01-20 日本電波工業株式会社 表面実装型デバイス及びその製造方法
US11425851B2 (en) * 2017-03-31 2022-08-23 Fuji Corporation Electronic component mounting machine and mounting method
WO2019013608A1 (ko) * 2017-07-14 2019-01-17 주식회사 아모센스 기능성 컨택터
US10594020B2 (en) 2017-07-19 2020-03-17 Samsung Electronics Co., Ltd. Electronic device having antenna element and method for manufacturing the same
KR102373931B1 (ko) 2017-09-08 2022-03-14 삼성전자주식회사 전자파 차폐구조
WO2019093218A1 (ja) * 2017-11-07 2019-05-16 アルプスアルパイン株式会社 圧力センサ
JP7029297B2 (ja) * 2018-01-16 2022-03-03 ローム株式会社 電子素子モジュール
CN108493176B (zh) * 2018-03-27 2020-07-10 浙江中正智能科技有限公司 一种指纹识别芯片装置及其制造方法
CN110349931B (zh) * 2018-04-08 2021-04-09 华为技术有限公司 封装结构、电子装置及封装方法
JP7155659B2 (ja) * 2018-06-25 2022-10-19 日本電気硝子株式会社 気密パッケージ及び気密パッケージの製造方法
JP2020014064A (ja) * 2018-07-13 2020-01-23 日本電波工業株式会社 圧電デバイス
JP2020036179A (ja) * 2018-08-30 2020-03-05 日本電波工業株式会社 圧電デバイス
FR3090264B1 (fr) * 2018-12-13 2022-01-07 St Microelectronics Grenoble 2 Procédé de montage de composant
DE112019007104T5 (de) * 2019-03-28 2021-12-09 Mitsubishi Electric Corporation Abschirmgehäuse
US20220342140A1 (en) * 2019-09-30 2022-10-27 Kyocera Corporation Optical waveguide package and light-emitting device
US11365118B1 (en) * 2020-12-03 2022-06-21 Knowles Electronics, Llc Acoustic transducer assembly
US20230145639A1 (en) * 2021-11-05 2023-05-11 Qorvo Us, Inc. System in a package (sip) with air cavity

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3743427B2 (ja) * 2003-02-07 2006-02-08 株式会社デンソー 電磁波シールド型半導体装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62149155A (ja) * 1985-09-02 1987-07-03 Hitachi Ltd 封止電子装置
JPH03203354A (ja) * 1989-12-29 1991-09-05 Nec Corp ガラスシール形半導体装置用パッケージ
JP3834426B2 (ja) * 1997-09-02 2006-10-18 沖電気工業株式会社 半導体装置
GB2365007B (en) * 2000-07-21 2002-06-26 Murata Manufacturing Co Insulative ceramic compact
JP2002110833A (ja) 2000-10-04 2002-04-12 Sanyo Electric Co Ltd 半導体装置およびその製造方法
JP2002134639A (ja) * 2000-10-25 2002-05-10 Murata Mfg Co Ltd 高周波電子部品用パッケージおよびそれを用いた高周波電子部品
JP2004064013A (ja) * 2002-07-31 2004-02-26 Kinseki Ltd 電子部品用パッケ−ジのキャップ封止方法
JP2006059872A (ja) * 2004-08-17 2006-03-02 Murata Mfg Co Ltd 高周波用電子部品および送受信装置
US7656047B2 (en) * 2005-01-05 2010-02-02 Advanced Semiconductor Engineering, Inc. Semiconductor device package and manufacturing method
US7358106B2 (en) * 2005-03-03 2008-04-15 Stellar Micro Devices Hermetic MEMS package and method of manufacture
JP2006253953A (ja) * 2005-03-09 2006-09-21 Fujitsu Ltd 通信用高周波モジュールおよびその製造方法
US8143095B2 (en) * 2005-03-22 2012-03-27 Tessera, Inc. Sequential fabrication of vertical conductive interconnects in capped chips
US20070232107A1 (en) * 2006-04-03 2007-10-04 Denso Corporation Cap attachment structure, semiconductor sensor device and method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3743427B2 (ja) * 2003-02-07 2006-02-08 株式会社デンソー 電磁波シールド型半導体装置

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
JP特开2002-134639A 2002.05.10
JP特开2004-64013A 2004.02.26

Also Published As

Publication number Publication date
KR101101562B1 (ko) 2012-01-02
EP2187435A1 (en) 2010-05-19
US8314485B2 (en) 2012-11-20
KR20100031547A (ko) 2010-03-22
JP5277755B2 (ja) 2013-08-28
EP2187435B1 (en) 2017-04-12
US20100200983A1 (en) 2010-08-12
CN101785097A (zh) 2010-07-21
EP2187435A4 (en) 2013-11-13
WO2010001503A1 (ja) 2010-01-07
JP2010016030A (ja) 2010-01-21

Similar Documents

Publication Publication Date Title
CN101785097B (zh) 电子零件
CN101728340B (zh) 半导体装置及其制造方法
US6748807B2 (en) Inertia detecting transducer
US8274797B2 (en) Electronic component
WO2022188524A1 (zh) 封装模组、封装工艺及电子设备
KR101166654B1 (ko) 반도체 장치
TW201408149A (zh) 電路板組件及相機模組
KR101135858B1 (ko) 전자 부품
JP2012089898A (ja) 半田ボール及び半導体パッケージ
US11146893B2 (en) Sensor system, sensor arrangement, and assembly method using solder for sealing
CN206877989U (zh) 电子器件
JP2009206286A (ja) プリント基板及びこれを用いた携帯電子機器
JP4852349B2 (ja) 半導体装置および半導体装置の製造方法
CN208538144U (zh) 指纹模组防水结构、防水指纹模组以及指纹识别移动终端
JP4319771B2 (ja) 赤外線データ通信モジュール
CN218123385U (zh) 封装产品及电子设备
CN214243807U (zh) 一种传感器电气组件
JP5804762B2 (ja) 圧電デバイス
JP5072124B2 (ja) 回路基板および電子機器
KR100512783B1 (ko) 사출성형된 영상감지기 및 그의 제조방법
JP5981825B2 (ja) 配線基板
KR20170089483A (ko) 밀봉 패키지 및 그 제조 방법
JP2011007532A (ja) センサ装置
KR20010058572A (ko) 반도체패키지 및 그 실장 방법
JPH02296354A (ja) 半導体装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CP03 Change of name, title or address
CP03 Change of name, title or address

Address after: Tokyo, Japan

Patentee after: MMI Semiconductor Co.,Ltd.

Address before: Shiga

Patentee before: Shiga Semiconductor Co.,Ltd.

TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20220907

Address after: Shiga

Patentee after: Shiga Semiconductor Co.,Ltd.

Address before: Kyoto Japan

Patentee before: Omron Corp.