CN206877989U - 电子器件 - Google Patents

电子器件 Download PDF

Info

Publication number
CN206877989U
CN206877989U CN201720588097.1U CN201720588097U CN206877989U CN 206877989 U CN206877989 U CN 206877989U CN 201720588097 U CN201720588097 U CN 201720588097U CN 206877989 U CN206877989 U CN 206877989U
Authority
CN
China
Prior art keywords
electrical connection
additional
electric connection
connection line
carrier substrates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201720588097.1U
Other languages
English (en)
Inventor
D·奥彻雷
A·哈吉
F·奎尔恰
J·洛佩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Grenoble 2 SAS
Original Assignee
STMicroelectronics Grenoble 2 SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Grenoble 2 SAS filed Critical STMicroelectronics Grenoble 2 SAS
Application granted granted Critical
Publication of CN206877989U publication Critical patent/CN206877989U/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6611—Wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the wire connector during or after the bonding process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/858—Bonding techniques
    • H01L2224/85801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Manufacturing & Machinery (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

电连接线连接电子芯片的电连接焊盘与载体衬底的电连接焊盘，该电子芯片安装至该载体衬底。液体介电材料沉积在该电连接线上并且然后硬化以形成围绕该电连接线的局部介电涂层。液体导电材料沉积在该局部介电涂层上并且然后硬化以形成围绕该局部介电涂层的局部导电屏蔽。

Description

电子器件
技术领域
实施例涉及电子器件领域并且更具体地涉及包括安装在载体衬底上的电子芯片以及将芯片连接至载体衬底的电连接线的那些电子器件，这些载体衬底包括电连接网络或引线框。
背景技术
在电连接线尤其是以高频率传送信号的情况下，这些信号可以通过围绕电磁场而被衰减或被破坏和/或发射可能破坏周围环境的电磁场。
目前，为了应对这种问题，提出了向电子器件添加潜在地连接至地的金属屏蔽板。尽管如此，定位这类金属屏蔽板并将其电连接至地，加上制造包封块或将包封盖放置就位造成了问题并且成本很高。此外，由于所获得的屏蔽是非特定的并且位于距电连接线一定距离，因此，所获得的电磁保护水平仍然是不够的。
实用新型内容
根据一个实施例，提出了一种电子器件，该电子器件包括：载体衬底；电子芯片，该电子芯片安装在该载体衬底上；至少一条电连接线，该至少一条电连接线连接该载体衬底的电连接焊盘和该电子芯片的电连接焊盘；局部介电涂层，该局部介电涂层由介电材料制成、至少部分地围绕该电连接线并且至少部分地覆盖这些电连接焊盘；以及局部导电屏蔽，该局部导电屏蔽由导电材料制成、至少部分地覆盖该局部介电涂层。
由介电材料制成的该局部介电涂层可以完全围绕该电连接线并且可以完全覆盖这些焊盘和这些结，并且该局部导电屏蔽可以完全覆盖该局部介电涂层。
该器件可以附加地包括至少一条附加电连接线，该至少一条附加电连接线连接该载体衬底的电连接焊盘和该电子芯片的电连接焊盘，该局部导电屏蔽与此附加电连接线和/或与这些电连接焊盘中的至少一个电连接焊盘相接触。
附图说明
现在将以附图所展示的非限制性示例的方式描述电子器件和制造模式，在附图中：
图1表示制造过程中的电子器件在一个制造步骤中的横截面视图；
图2表示图1的电子器件的俯视图；
图3表示制造过程中的电子器件在随后的制造步骤中的横截面视图；
图4表示图3的电子器件的俯视图；
图5表示制造过程中的电子器件在随后的制造步骤中的横截面视图，示出了所获得的电子器件；以及
图6表示图5的电子器件的俯视图。
具体实施方式
如在图1和图2中所展示的，电子器件1包括载体衬底2以及包括有集成电路的电子芯片3，该电子芯片的背面4借助于粘合层(未示出)固定至载体衬底2的正面5。
载体衬底2由介电材料制成并且包括用于连接至一个或多个金属层的集成电连接网络6，该集成电连接网络包括正面5的正面暴露的电连接焊盘7和8，这些正面暴露的电连接焊盘横向地位于与电子芯片3的侧面9相距一定距离处并且彼此靠近。
电子芯片3包括与其背面4相反的此电子芯片3的正面12的正面暴露的电连接焊盘10和11，这些正面暴露的电连接焊盘位于与电子芯片3的侧面9相距一定距离处，离载体衬底2的正面焊盘7和8不远。
现在将描述出于在载体衬底2和电子芯片3的焊盘7与10以及可选地焊盘8与11之间分别形成电连接的目的的步骤。
在图1和图2所展示的步骤中，一方面，裸露的电连接线(也称为键合接线)13被放置就位在暴露的电连接焊盘7与10之间，并且电结14和15借助于焊接分别形成在电连接线13的两端与焊盘7和10之间，并且另一方面，附加电连接线16被放置就位在附加的暴露的电连接焊盘8与11之间，并且电结借助于焊接分别形成在电连接线16的端部与焊盘8和11之间。电连接线13和16是邻近的但是彼此有一定距离。
可以使用专门的接线键合机来实施将电连接线13和16放置就位的这个操作。
在图3和图4所展示的随后的步骤中，将确定量的粘合液体介电材料局部分配在电连接线13的顶部上，使得此介电材料完全围绕电连接线13并且完全覆盖焊盘7和10以及结14和15。在硬化之后，此介电材料形成局部介电涂层17。
此操作可以例如使用专门的工具来实施，该专门的工具包括能够将液体介电材料的至少一滴校准的液体介电材料递送到电连接线13的顶部上的分注注射器18，此液体介电材料具体地借助于润湿效应或者毛细效应最终流动用于围绕电连接线12并且用于覆盖焊盘7和10以及结14和15。
接下来，液体介电材料凭借其在室温下固有的硬化品质或者通过在热源或光辐射源效应下硬化而硬化以形成介电涂层17。例如，介电材料可以是适合的环氧树脂。
在图5和图6所展示的随后步骤中，将确定量的导电粘合液体材料局部分配在介电涂层17的顶部上以及潜在地在电连接线16的顶部上，从而使得此导电材料完全围绕介电涂层17并且与电连接线16和/或焊盘8和11相接触，此导电材料潜在地溢流到载体衬底2的以及电子芯片3的正面5和12上。在硬化之后，此导电材料形成局部导电屏蔽19，该局部导电屏蔽尽可能地靠近电连接线13并且连接至电连接线16以及至焊盘8和11。
此操作可以例如使用专门的控制工具来实施，该专门的控制工具包括能够递送液体导电材料的至少一滴校准的液体导电材料的分注注射器20，此液体导电材料具体地借助于润湿效应或者毛细效应流动。
接下来，液体导电材料凭借其在室温下固有的硬化品质或者通过在热源或光辐射源效应下硬化而硬化以形成局部导电屏蔽19。例如，导电材料可以是填充有金属颗粒的环氧树脂。
因此，获得成品电子器件1。
电连接线13旨在传送载体衬底2和电子芯片3的焊盘7与10之间的电信号。导电屏蔽19为这些电信号提供电磁保护。
由电连接线16连接的焊盘8和11形成电子器件1的电气电路的接地焊盘。因此，连接至焊盘8和11以及至电连接线16的导电屏蔽19连接至电子器件1的电气电路的地。
根据一个变体实施例，局部介电涂层17将有可能覆盖焊盘7和10中的仅一个焊盘以及电连接线13的相邻部分，并且局部导电屏蔽19将有可能在此减少的局部导电屏蔽19不与电连接线13相接触的情况下部分地覆盖此减少的局部介电涂层17。
根据一个变体实施例，将有可能真的省略电连接线16。
当然，电子器件1可以包括连接载体衬底2的以及电子芯片3的其他焊盘7和10的其他电连接线13，以及连接载体衬底2的以及电子芯片3的其他焊盘8和11的其他电连接线16，该载体衬底和该电子芯片还配备有局部介电涂层17和局部导电屏蔽19，这些电连接线的对应制造步骤将会是相同的。
根据一个变体实施例，一个局部导电屏蔽19将有可能由多个邻近电连接线13共享并且局部地覆盖载体衬底的正面5和/或电子芯片3的正面12，使得此延伸的局部导电屏蔽19将会形成对电子器件1的电子电路中的一部分的电磁保护。这类延伸的局部导电屏蔽19可以例如借助于金属材料(例如，铜或铝)的物理气相淀积(PCV)来形成。在此情况下，将有可能提供单条接地电连接线16。仍在此情况下并且作为变体，延伸的局部导电屏蔽19可以通过提供载体衬底2的未被介电涂层17覆盖的至少一个电连接焊盘8而连接至地。
根据一个变体实施例，载体衬底2可以包括金属框，该金属框包括电子芯片3将会安装在其上的平台，电连接线13和16将电子芯片3连接至此框的外围引线。

Claims (5)

1.一种电子器件，其特征在于，包括：
载体衬底；
电子芯片，所述电子芯片安装在所述载体衬底上；
至少一条电连接线，所述至少一条电连接线连接所述载体衬底的电连接焊盘和所述电子芯片的电连接焊盘；
局部介电涂层，所述局部介电涂层由介电材料制成、至少部分地围绕所述电连接线并且至少部分地覆盖所述电连接焊盘；以及
局部导电屏蔽，所述局部导电屏蔽由导电材料制成、至少部分地覆盖所述局部介电涂层。
2.根据权利要求1所述的电子器件，其特征在于，所述局部介电涂层完全围绕所述电连接线并且完全覆盖所述电连接焊盘，并且其中，所述局部导电屏蔽完全覆盖所述局部介电涂层。
3.根据权利要求1所述的器件，其特征在于，进一步包括至少一条附加电连接线，所述至少一条附加电连接线连接所述载体衬底的附加电连接焊盘和所述电子芯片的附加电连接焊盘，所述局部导电屏蔽与所述附加电连接线中的至少一条附加电连接线以及所述附加电连接焊盘中的至少一个附加电连接焊盘相接触。
4.一种电子器件，其特征在于，包括：
载体衬底；
电子芯片，所述电子芯片安装在所述载体衬底上；
键合接线，所述键合接线连接所述载体衬底的电连接焊盘和所述电子芯片的电连接焊盘；
硬化的液体介电材料，所述硬化的液体介电材料围绕所述键合接线以形成介电涂层；以及
硬化的液体导电材料，所述硬化的液体导电材料围绕所述介电涂层。
5.如权利要求4所述的电子器件，其特征在于，进一步包括：
附加键合接线，所述附加键合接线连接所述电子芯片的附加电连接焊盘和所述载体衬底的附加电连接焊盘；
其中，所述硬化的液体导电材料围绕所述附加键合接线。
CN201720588097.1U 2016-11-03 2017-05-24 电子器件 Active CN206877989U (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1660624 2016-11-03
FR1660624A FR3058261A1 (fr) 2016-11-03 2016-11-03 Procede de realisation d'une connexion electrique entre une puce electronique et une plaque de support et dispositif electronique

Publications (1)

Publication Number Publication Date
CN206877989U true CN206877989U (zh) 2018-01-12

Family

ID=58213196

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201710374185.6A Pending CN108022910A (zh) 2016-11-03 2017-05-24 用于在电子芯片与载体衬底之间形成电连接的方法以及电子器件
CN201720588097.1U Active CN206877989U (zh) 2016-11-03 2017-05-24 电子器件

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN201710374185.6A Pending CN108022910A (zh) 2016-11-03 2017-05-24 用于在电子芯片与载体衬底之间形成电连接的方法以及电子器件

Country Status (3)

Country Link
EP (1) EP3319114B1 (zh)
CN (2) CN108022910A (zh)
FR (1) FR3058261A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108022910A (zh) * 2016-11-03 2018-05-11 意法半导体(格勒诺布尔2)公司 用于在电子芯片与载体衬底之间形成电连接的方法以及电子器件
US11557566B2 (en) 2016-11-03 2023-01-17 Stmicroelectronics (Grenoble 2) Sas Method for forming an electrical connection between an electronic chip and a carrier substrate and electronic device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2514011C2 (de) * 1975-03-29 1983-10-27 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Gehäuse für ein Halbleiterelement
JP2689467B2 (ja) * 1988-03-29 1997-12-10 日本電気株式会社 半導体集積回路装置のパッケージ
JPH06268100A (ja) * 1993-03-12 1994-09-22 Nippon Telegr & Teleph Corp <Ntt> 半導体装置の封止構造および封止方法
JP2000058579A (ja) * 1998-08-04 2000-02-25 Hitachi Ltd 半導体装置およびその製造方法
JP2002064166A (ja) * 2000-06-06 2002-02-28 Nippon Steel Corp 半導体装置およびその製造方法、ならびに半導体装置の樹脂封止装置
US20040070065A1 (en) * 2002-10-11 2004-04-15 Aritharan Thurairajaratnam Controlled impedance for wire bonding interconnects
KR100575086B1 (ko) * 2004-11-11 2006-05-03 삼성전자주식회사 도전성 몰딩 컴파운드를 구비한 반도체 패키지 및 그제조방법
US20100025864A1 (en) * 2008-07-31 2010-02-04 International Business Machines Corporation Shielded wirebond
KR100950511B1 (ko) * 2009-09-22 2010-03-30 테세라 리써치 엘엘씨 와이어 본딩 및 도전성 기준 소자에 의해 제어되는 임피던스를 포함하는 마이크로전자 어셈블리
FR3058261A1 (fr) * 2016-11-03 2018-05-04 Stmicroelectronics (Grenoble 2) Sas Procede de realisation d'une connexion electrique entre une puce electronique et une plaque de support et dispositif electronique

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108022910A (zh) * 2016-11-03 2018-05-11 意法半导体(格勒诺布尔2)公司 用于在电子芯片与载体衬底之间形成电连接的方法以及电子器件
US11557566B2 (en) 2016-11-03 2023-01-17 Stmicroelectronics (Grenoble 2) Sas Method for forming an electrical connection between an electronic chip and a carrier substrate and electronic device

Also Published As

Publication number Publication date
EP3319114B1 (fr) 2022-06-29
FR3058261A1 (fr) 2018-05-04
CN108022910A (zh) 2018-05-11
EP3319114A1 (fr) 2018-05-09

Similar Documents

Publication Publication Date Title
KR101177039B1 (ko) 솔더 및 필름 접착제를 사용하여 플립 칩 패키지에 히트 스프레더/스티프너를 접지하는 방법
JP3082905B2 (ja) チップ・オン・ボード遮蔽構造およびその製造方法
US12002838B2 (en) Shielded integrated device packages
CN206877989U (zh) 电子器件
US20080224276A1 (en) Semiconductor device package
US8274797B2 (en) Electronic component
KR20100137183A (ko) 반도체 패키지의 제조 방법 및 이에 의해 제조된 반도체 패키지
CN207038521U (zh) 电子器件
TW201408149A (zh) 電路板組件及相機模組
JP2009277910A (ja) 半導体モジュールおよび半導体モジュールの製造方法
CN206877990U (zh) 电子器件
US11557566B2 (en) Method for forming an electrical connection between an electronic chip and a carrier substrate and electronic device
US20200105636A1 (en) Chip package structure having function of preventing adhesive from overflowing
KR101680978B1 (ko) 플렉시블 반도체 패키지 및 이의 제조 방법
US20230121780A1 (en) Method for forming an electrical connection between an electronic chip and a carrier substrate and electronic device
KR20090114493A (ko) 반도체 패키지 및 그 제조 방법
US11437306B2 (en) Electronics unit with integrated metallic pattern
JPH11145180A (ja) 電子部品およびその製造方法
CN108807294A (zh) 封装结构及其制法
TWI687140B (zh) 形成貼附式雙面載放零件之電子晶片模組的方法
JP2975782B2 (ja) 混成集積回路装置およびこれに用いるケース材
TWI243463B (en) Chip on board package and method for manufacturing the same
CN102254891A (zh) 倒装芯片封装结构及其制造方法
JP2000114683A (ja) 厚膜回路基板
JP2005353792A (ja) 樹脂封止型半導体装置

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant