CN207038521U - 电子器件 - Google Patents

电子器件 Download PDF

Info

Publication number
CN207038521U
CN207038521U CN201720569537.9U CN201720569537U CN207038521U CN 207038521 U CN207038521 U CN 207038521U CN 201720569537 U CN201720569537 U CN 201720569537U CN 207038521 U CN207038521 U CN 207038521U
Authority
CN
China
Prior art keywords
electrical connection
connection pad
pad
electronic device
electric connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201720569537.9U
Other languages
English (en)
Inventor
D·奥彻雷
F·奎尔恰
A·哈吉
J·洛佩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Grenoble 2 SAS
Original Assignee
STMicroelectronics Grenoble 2 SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Grenoble 2 SAS filed Critical STMicroelectronics Grenoble 2 SAS
Application granted granted Critical
Publication of CN207038521U publication Critical patent/CN207038521U/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4871Bases, plates or heatsinks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6605High-frequency electrical connections
    • H01L2223/6611Wire connections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554Coating
    • H01L2224/45565Single coating layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85007Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the wire connector during or after the bonding process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/858Bonding techniques
    • H01L2224/85801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/8592Applying permanent coating, e.g. protective coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Manufacturing & Machinery (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

本实用新型的实施例涉及电子器件。该电子器件包括:载体衬底;电子芯片,所述电子芯片安装在所述载体衬底上;至少一条电连接线,所述至少一条电连接线连接所述载体衬底的电连接焊盘与所述电子芯片的电连接焊盘;绝缘护套,所述绝缘护套由介电材料制成、围绕所述电连接线;局部介电涂层,所述局部介电涂层由介电材料制成、至少部分地覆盖所述电连接焊盘中的至少一个电连接焊盘并且至少部分地围绕与所述至少一个电连接焊盘相邻的所述绝缘护套的至少一端;以及局部导电屏蔽,所述局部导电屏蔽由导电材料制成、至少部分地覆盖所述局部介电涂层并且至少部分地围绕所述绝缘护套。

Description

电子器件
技术领域
实施例涉及电子器件领域并且更具体地涉及包括安装在载体衬底上的电子芯片以及将芯片连接至载体衬底的电连接线的那些电子器件,该载体衬底包括电连接网络或引线框。
在电连接线尤其是以高频率传送信号的情况下,这些信号可以通过围绕电磁场而被衰减或被破坏和/或发射可能破坏周围环境的电磁场。
背景技术
目前,为了应对这一问题,提出了向电子器件添加潜在连接至地的金属屏蔽板。尽管如此,定位这类金属屏蔽板并将其电连接至地,加上制造包封块或将包封盖放置就位造成了问题并且成本很高。此外,由于所获得的屏蔽是非特定的并且定位成距电连接线一定距离,因此,所获得的电磁保护水平仍然是不够的。
实用新型内容
本实用新型的实施例提供至少部分地解决上述技术问题的电子器件。
根据一些实施例,提供了一种电子器件。该电子器件包括:载体衬底;电子芯片,电子芯片安装在载体衬底上;至少一条电连接线,至少一条电连接线连接载体衬底的电连接焊盘与电子芯片的电连接焊盘;绝缘护套,绝缘护套由介电材料制成、围绕电连接线;局部介电涂层,局部介电涂层由介电材料制成、至少部分地覆盖电连接焊盘中的至少一个电连接焊盘并且至少部分地围绕与至少一个电连接焊盘相邻的绝缘护套的至少一端;以及局部导电屏蔽,局部导电屏蔽由导电材料制成、至少部分地覆盖局部介电涂层并且至少部分地围绕绝缘护套。
在一些实施例中,局部介电涂层包括:第一局部介电涂层,第一局部介电涂层至少部分地覆盖第一电连接焊盘以及与其相邻的第一电结并且至少部分地围绕与第一电结相邻的绝缘护套的第一端部;以及第二局部介电涂层,第二局部介电涂层至少部分地覆盖第二电连接焊盘以及与其相邻的第二电结并且至少部分地围绕与第二电结相邻的绝缘护套的第二端部。
在一些实施例中,导电材料覆盖第一局部介电涂层和第二局部介电涂层并且围绕第一局部介电涂层与第二局部介电涂层之间的绝缘护套。
在一些实施例中,该电子器件还包括至少一条附加电连接线,至少一条附加电连接线连接载体衬底的附加电连接焊盘和电子芯片的附加电连接焊盘,并且其中,局部导电屏蔽与附加电连接线中的至少一条附加电连接线以及附加电连接焊盘中的至少一个附加电连接焊盘相接触。
在一些实施例中,载体衬底包括附加电连接焊盘,并且其中,局部导电屏蔽与附加电连接焊盘相接触。
在一些实施例中,电子芯片包括附加电连接焊盘,并且其中,局部导电屏蔽与附加电连接焊盘相接触。
本实用新型的实施例所提供的电子器件可以以较低的成本提供较高的电磁保护水平。
附图说明
现在将以附图中所展示的非限制性示例的方式描述电子器件和制造模式,在附图中:
图1表示制造过程中的电子器件在一个制造步骤中的横截面视图;
图2表示图1的电子器件的俯视图;
图3表示制造过程中的电子器件在随后制造步骤中的横截面视图;
图4表示图3的电子器件的俯视图;
图5表示制造过程中的电子器件在随后制造步骤中的横截面视图,示出了所获得的电子器件;以及
图6表示图5的电子器件的俯视图。
具体实施方式
如在图1和图2中所展示的,电子器件1包括载体衬底2以及包括有集成电路的电子芯片3,该电子芯片的背面4借助于粘合层(未示出)固定至载体衬底2的正面5。
载体衬底2由介电材料制成并且包括用于连接至一个或多个金属层的集成电连接网络6,该集成电连接网络包括正面5的正面暴露的电连接焊盘7和8,这些正面暴露的电连接焊盘横向地位于与电子芯片3的侧面9相距一定距离处并且彼此靠近。
电子芯片3包括与其背面4相对的此电子芯片3的正面12的正面暴露的电连接焊盘10和11,这些正面暴露的电连接焊盘位于与电子芯片3的侧面9相距一定距离处,离载体衬底2的正面焊盘7和8不远。
现在将描述出于在载体衬底2和电子芯片3的焊盘7与10以及可选地焊盘8与11之间分别形成电连接的目的的步骤。
在图1和图2所展示的步骤中,由介电材料制成的护套113a围绕的电连接线113被放置就位在暴露的电连接焊盘7与10之间,并且借助于焊接在电连接线113的两端与焊盘7和10之间分别形成电结114和115。此外,裸露的或者被绝缘护套围绕的附加电连接线116被放置就位在附加的暴露的电连接焊盘8与11之间,并且借助于焊接在电连接线116的端部与焊盘8和11之间分别形成电结。电连接线113和116是邻近的但是彼此有一定距离。
可以使用专门的接线键合机来实施将电连接线113和116放置就位的这个操作。
在图3和图4所展示的随后步骤中,确定量的粘合液体介电材料局部地分配在焊盘7和/或结114的顶部和/或绝缘护套113a与结114相邻的端部,使得此介电材料完全覆盖焊盘7和结114并且完全围绕绝缘护套113a与结114相邻的端部。在硬化之后,此介电材料形成第一局部介电涂层117a。
以等效的方式,确定量的粘合液体介电材料局部地分配在焊盘10和/或结115的顶部和/或绝缘护套113a与结115相邻的端部,使得此介电材料完全覆盖焊盘7和结115并且完全围绕绝缘护套113a与结115相邻的端部。在硬化之后,此介电材料形成第二局部介电涂层117b。
这些操作可以例如使用专门的控制工具来实施,该控制工具包括能够递送该液体导电材料的至少一滴校准的液体介电材料的分注注射器118,此液体介电材料具体地借助于润湿效应或者毛细效应最终流动用于覆盖焊盘7和10以及结114和115并且用于围绕绝缘护套113a的相应端部。
接下来,液体介电材料凭借其在室温下固有的硬化品质或者通过在热源或者光辐射源效应下硬化而硬化以形成介电涂层117a和117b。例如,介电材料可以是适合的环氧树脂。
在图5和图6所展示的随后的步骤中,确定量的导电粘合液体材料局部地分配使得此导电材料完全围绕绝缘护套113a、覆盖局部介电涂层117a和117b并且与电连接线116和/或焊盘8和11相接触,此导电材料潜在地溢流到载体衬底2的以及电子芯片3的正面5和12上。在硬化之后,此导电材料形成局部导电屏蔽119,所述局部导电屏蔽尽可能地靠近电连接线113并且连接至电连接线116以及至焊盘8和11。
此操作可以例如使用专门的控制工具来实施,该控制工具包括能够递送该液体导电材料的至少一滴对应校准的液体导电材料的分注注射器120,此液体导电材料具体地借助于润湿效应或者毛细效应流动。
接下来,液体导电材料凭借其在室温下固有的硬化品质或者通过在热源或者光辐射源效应下硬化而硬化以形成局部导电屏蔽119。例如,导电材料可以是填充有金属颗粒的环氧树脂。
电连接线113旨在传送载体衬底2的以及电子芯片3的焊盘7与10之间的电信号。导电屏蔽119为这些电信号提供电磁保护。
由电连接线116连接的焊盘8和11形成电子器件1的电气电路的接地焊盘。因此,连接至焊盘8和11以及至电连接线116的导电屏蔽119连接至电子器件1的电气电路的地。
根据一个变体实施例,将有可能提供局部介电涂层117a和117b中的仅一个局部介电涂层并且在此减少的局部导电屏蔽119未与电连接线113和相对焊盘相接触的情况下,局部导电屏蔽119将有可能部分地覆盖此局部介电涂层以及护套113a的一部分。
根据一个变体实施例,将有可能真的省略电连接线116。
当然,电子器件1可以包括连接载体衬底2的以及电子芯片3的其他焊盘7和10的其他电连接线113,以及连接载体衬底2的以及电子芯片3的其他焊盘8和11的其他电连接线116,该载体衬底和该电子芯片还配备有局部介电涂层117a和117b以及局部导电屏蔽119,这些电连接线的对应制造步骤将会是相同的。
根据一个变体实施例,一个局部导电屏蔽119将有可能由多个邻近电连接线113共享并且局部地覆盖载体衬底的正面5和/或电子芯片3的正面12,使得此延伸的局部导电屏蔽119将会形成对电子器件1的电子电路中的一部分的电磁保护。这类延伸的局部导电屏蔽119可以例如借助于金属材料(例如,铜或铝)的物理气相沉积(PCV)形成。在此情况下,将潜在地有可能提供单条接地电连接线116。仍在此情况下并且作为变体,延伸的局部导电屏蔽119可以通过提供载体衬底2的未被介电涂层117覆盖的至少一个电连接焊盘8而连接至地。
根据一个变体实施例,载体衬底2可以包括金属框,该金属框包括电子芯片3将会安装在其上的平台,电连接线113和116将电子芯片3连接至此框的外围引线。

Claims (6)

1.一种电子器件,其特征在于,包括:
载体衬底;
电子芯片,所述电子芯片安装在所述载体衬底上;
至少一条电连接线,所述至少一条电连接线连接所述载体衬底的电连接焊盘与所述电子芯片的电连接焊盘;
绝缘护套,所述绝缘护套由介电材料制成、围绕所述电连接线;
局部介电涂层,所述局部介电涂层由介电材料制成、至少部分地覆盖所述电连接焊盘中的至少一个电连接焊盘并且至少部分地围绕与所述至少一个电连接焊盘相邻的所述绝缘护套的至少一端;以及
局部导电屏蔽,所述局部导电屏蔽由导电材料制成、至少部分地覆盖所述局部介电涂层并且至少部分地围绕所述绝缘护套。
2.根据权利要求1所述的电子器件,其特征在于,所述局部介电涂层包括:第一局部介电涂层,所述第一局部介电涂层至少部分地覆盖第一电连接焊盘以及与其相邻的第一电结并且至少部分地围绕与所述第一电结相邻的所述绝缘护套的第一端部;以及
第二局部介电涂层,所述第二局部介电涂层至少部分地覆盖第二电连接焊盘以及与其相邻的第二电结并且至少部分地围绕与所述第二电结相邻的所述绝缘护套的第二端部。
3.根据权利要求2所述的电子器件,其特征在于,所述导电材料覆盖所述第一局部介电涂层和所述第二局部介电涂层并且围绕所述第一局部介电涂层与所述第二局部介电涂层之间的所述绝缘护套。
4.根据权利要求1所述的电子器件,其特征在于,还包括至少一条附加电连接线,所述至少一条附加电连接线连接所述载体衬底的附加电连接焊盘和所述电子芯片的附加电连接焊盘,并且其中,所述局部导电屏蔽与所述附加电连接线中的至少一条附加电连接线以及所述附加电连接焊盘中的至少一个附加电连接焊盘相接触。
5.根据权利要求1所述的电子器件,其特征在于,所述载体衬底包括附加电连接焊盘,并且其中,所述局部导电屏蔽与所述附加电连接焊盘相接触。
6.根据权利要求1所述的电子器件,其特征在于,所述电子芯片包括附加电连接焊盘,并且其中,所述局部导电屏蔽与所述附加电连接焊盘相接触。
CN201720569537.9U 2016-11-03 2017-05-19 电子器件 Active CN207038521U (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1660623A FR3058260A1 (fr) 2016-11-03 2016-11-03 Procede de realisation d'une connexion electrique entre une puce electronique et une plaque de support et dispositif electronique
FR1660623 2016-11-03

Publications (1)

Publication Number Publication Date
CN207038521U true CN207038521U (zh) 2018-02-23

Family

ID=58213195

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201720569537.9U Active CN207038521U (zh) 2016-11-03 2017-05-19 电子器件
CN201710358792.3A Pending CN108022908A (zh) 2016-11-03 2017-05-19 用于形成电连接的方法和电子器件

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201710358792.3A Pending CN108022908A (zh) 2016-11-03 2017-05-19 用于形成电连接的方法和电子器件

Country Status (3)

Country Link
EP (1) EP3319115B1 (zh)
CN (2) CN207038521U (zh)
FR (1) FR3058260A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108022908A (zh) * 2016-11-03 2018-05-11 意法半导体(格勒诺布尔2)公司 用于形成电连接的方法和电子器件

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100309957B1 (ko) * 1997-09-08 2002-08-21 신꼬오덴기 고교 가부시키가이샤 반도체장치
JP2000058579A (ja) * 1998-08-04 2000-02-25 Hitachi Ltd 半導体装置およびその製造方法
JP3825197B2 (ja) * 1999-03-30 2006-09-20 ローム株式会社 半導体装置
JP2013197531A (ja) * 2012-03-22 2013-09-30 Sharp Corp 半導体装置およびその製造方法
FR3058260A1 (fr) * 2016-11-03 2018-05-04 Stmicroelectronics (Grenoble 2) Sas Procede de realisation d'une connexion electrique entre une puce electronique et une plaque de support et dispositif electronique

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108022908A (zh) * 2016-11-03 2018-05-11 意法半导体(格勒诺布尔2)公司 用于形成电连接的方法和电子器件

Also Published As

Publication number Publication date
EP3319115B1 (fr) 2022-06-29
EP3319115A1 (fr) 2018-05-09
CN108022908A (zh) 2018-05-11
FR3058260A1 (fr) 2018-05-04

Similar Documents

Publication Publication Date Title
TWI273679B (en) Optimized lid mounting for electronic device carriers
TWI431748B (zh) 具有阻抗控制引線接合及導電參考元件之微電子總成
CN107546140A (zh) 嵌入式芯片封装及用于制造嵌入式芯片封装的方法
JP2009016715A (ja) シールド及び放熱性を有する高周波モジュール及びその製造方法
TW201013882A (en) Integrated circuit package having integrated faraday shield
CN108701664A (zh) 用于经封装半导体裸片的内部热扩散的设备及方法
CN110268519A (zh) 功率半导体模块
KR20150047167A (ko) 반도체 패키지 및 이의 제조 방법
KR100788858B1 (ko) 집적 회로 패키지의 구조물 및 어셈블리 방법
CN206877989U (zh) 电子器件
CN207038521U (zh) 电子器件
CN103617991A (zh) 半导体封装电磁屏蔽结构及制作方法
CN103579201B (zh) 采用导电封装材料的半导体器件电磁屏蔽结构及制作方法
CN105280624A (zh) 电子装置模块及其制造方法
CN107452696A (zh) 电磁屏蔽封装体以及制造方法
CN206877990U (zh) 电子器件
TW201240058A (en) Electromagnetic interference shielding structure for integrated circuit substrate and method for fabricating the same
US11557566B2 (en) Method for forming an electrical connection between an electronic chip and a carrier substrate and electronic device
CN102651353B (zh) 半导体装置及其制造方法
JP2012015548A (ja) シールド及び放熱性を有する高周波モジュール及びその製造方法
US20230121780A1 (en) Method for forming an electrical connection between an electronic chip and a carrier substrate and electronic device
TWI281738B (en) Structure and assembly method of IC packaging
CN103579202A (zh) 有机基板半导体器件电磁屏蔽结构及制作方法
US20080272468A1 (en) Grounded shield for blocking electromagnetic interference in an integrated circuit package
CN108807294A (zh) 封装结构及其制法

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant