CN101685777A - 半导体装置的制造方法 - Google Patents

半导体装置的制造方法 Download PDF

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Publication number
CN101685777A
CN101685777A CN200910173269A CN200910173269A CN101685777A CN 101685777 A CN101685777 A CN 101685777A CN 200910173269 A CN200910173269 A CN 200910173269A CN 200910173269 A CN200910173269 A CN 200910173269A CN 101685777 A CN101685777 A CN 101685777A
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China
Prior art keywords
layer
substrate
free radical
semiconductor device
dielectric constant
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CN200910173269A
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张哲豪
侯承浩
余振华
吴泰伯
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN101685777A publication Critical patent/CN101685777A/zh
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Abstract

本发明公开一种半导体装置的制造方法。该方法包括提供一基底；以自由基(radical)对基底进行处理，而在其上形成一界面层；以及在界面层上形成一高介电常数材料层。上述自由基是择自于以下群族：含水自由基、氮/氢自由基及硫/氢自由基。本发明的优点包括：(1)基底(通道)/界面层界面钝化；(2)因高介电常数前驱物而改变界面层表面(较接的润湿界面)；(3)在高介电常数材料沉积之后，界面层/高介电常数材料的界面钝化；(4)界面处的大气污染源少；(5)抑制热引扩散；(6)栅极介电层的EOT小于10埃。因此，栅极介电层的EOT符合先进的技术要求(例如，45nm以下)。

Description

半导体装置的制造方法
技术领域
本发明涉及一种半导体工艺，特别涉及一种用于金属栅极的高介电常数栅极介电层的制造方法。
背景技术
半导体集成电路(integrated circuit，IC)工业已经历快速的成长。在IC材料与设计的技术进展已造就各个IC世代，每一世代的电路都比前世代来得更小更复杂。然而，这些进展却增加IC制造及加工的复杂度，而根据这些进展，IC制造及加工需要类似的演进。在IC进展课题中，功能密度(即，单位芯片面积的内连装置数量)普遍增加，而几何尺寸(即，工艺所能形成的最小部件(或线))则下降。上述尺寸微缩工艺因生产效率的增加及成本的降低而有所助益。而降低尺寸比例产生相对较高的功率消耗(powerdissipation)值，其可通过使用低功耗装置而获得解决，例如互补式金属氧化物半导体(complementary metal-oxide-semiconductor，CMOS)装置。
在尺寸比例微缩发展期间，使用各种不同的材料作为CMOS装置的栅极电极及栅极介电层。而这些装置的制造希望以金属材料作为栅极电极，且以高介电常数(high-k)材料作为栅极介电层。通常在高介电常数材料层与硅基底之间会形成一界面(interfacial)层，例如氧化层，以促进高介电常数材料层的形成并改善界面处的电特性。然而，当形成界面层时会引起一些问题，例如后续工艺期间对于高介电常数材料沉积的润湿(wetting)特性不佳及发生氧化物再成长(re-growth)。
因此，有必要寻求一种新的改善方法，用以在基底上形成界面层及高介电常数材料层。
发明内容
本发明一实施例提供一种半导体装置的制造方法，包括：提供一基底；以自由基对基底进行处理，而在其上形成一界面层，其中自由基是择自于以下群族：含水自由基、氮/氢自由基及硫/氢自由基；以及在界面层上形成一高介电常数材料层。
本发明另一实施例提供一种半导体装置的制造方法，包括：提供一基底；对基底进行一第一处理，以在基底上形成一第一介电层，第一处理包括第一自由基；对第一介电层进行一第二处理，以在基底上形成一第二介电层，第二处理包括不同于第一自由基的第二自由基，其中每一第一及第二自由基包括含水自由基或氮/氢自由基；以及在第一及第二介电层上形成一高介电常数材料层。
本发明又另一实施例提供一种半导体装置的制造方法，包括：提供一基底；对基底进行至少一处理，以在基底上形成一界面层，处理包括等离子体工艺及紫外线工艺的其中一个，且该处理是使用自由基，其择自于以下群族：含水自由基、氮/氢自由基及硫/氢自由基；以及在界面层上形成一高介电常数材料层。
本发明的优点包括：(1)基底(通道)/界面层界面钝化；(2)因高介电常数前驱物而改变界面层表面(较接的润湿界面)；(3)在高介电常数材料沉积之后，界面层/高介电常数材料的界面钝化；(4)界面处的大气污染源少；(5)抑制热引扩散；(6)栅极介电层的EOT小于10埃。因此，栅极介电层的EOT符合先尽的技术要求(例如，45nm以下)。
附图说明
图1是显示出在半导体基底上形成界面层及高介电常数材料层的方法示意图。
图2是显示出在半导体基底上形成界面层及高介电常数材料层的另一方法示意图。
图3是显示出在半导体基底上形成界面层及高介电常数材料层的另一方法示意图。
图4是显示出根据本发明各个实施例的在半导体基底上形成界面层及高介电常数材料层的方法流程图。
图5A～图5C是显示出根据图4方法来形成界面层及高介电常数材料层的剖面示意图。
图6A～图6C是显示出另一方法来形成界面层及高介电常数材料层的剖面示意图。
图7A～图7C是显示出又另一方法来形成界面层及高介电常数材料层的剖面示意图。
图8是显示出根据本发明各个实施例的在半导体基底上形成界面层及高介电常数材料层的另一方法流程图。
图9A～图9D是显示出根据图8方法来形成界面层及高介电常数材料层的剖面示意图。
图10A～图10D是显示出根据本发明各个实施例的以双重处理工艺形成界面层，且在半导体基底上沉积高介电常数材料层。
并且，上述附图中的附图标记说明如下：
100、200、300、500、600、700、900、1000～基底；
102、202、302、502、602、702～界面层；
104、206、306、506、606、706、912、1012～高介电常数材料层；
110、210、310、510、610、710、914、1014～原子层沉积(ALD)～工艺；
112～缺陷；
204、504、904～氢氧(-OH)官能基；
212～过量氢氧官能基；
214、312～电子陷阱；
304～上表面；
400、800～方法；
410、420、430、810、820、830、840～区块；
503～等离子体工艺；
603、703、903、908、1003、1008～处理；
604、909～官能基；
704～烷(-SHx)官能基；
902～第一介电层；
906～第二介电层；
1002、1002a、1006～介电层；
1004～氨(-NHx)官能基；
1009～(-OH)及/或(-NHx)官能基；
AMC～大气污染源。
具体实施方式
可了解的是以下的公开内容提供许多不同的实施例或范例，用以实施各个实施例的不同特征。而以下所公开的内容是叙述各个构件及其排列方式的特定范例，以求简化本发明的说明。当然，这些特定的范例并非用以限定本发明。再者，本说明书以下的公开内容叙述了将一第一特征形成于一第二特征之上或上方，其表示包含了所形成的上述第一特征与上述第二特征是直接接触的实施例，亦包含了尚可将额外的特征形成于第一特征与第二特征之间而使第一特征与第二特征并未直接接触的实施例。为了达到简化及清晰的目的，不同特征可能以不同尺寸比例显示。
请参照图1，其显示出在一半导体基底上形成一界面层及一高介电常数材料层的示意图。半导体基底100包括一硅基底。基底100可包括不同的掺杂型态，取决于公知设计需求。基底100亦包括其他单质(elementary)半导体，例如锗及钻石。另外，基底100可包括一化合物半导体及/或一合金半导体。再者，基底100可选择性地包括一外延层(epi layer)，其可具有应变以提高效能，且可包括一绝缘层上覆硅(silicon-on-insulator，SOI)的结构。
一界面层102形成于基底100上。界面层102可包括氧化硅(SiO2)，其以公知热氧化成长一SiO2层(例如，热氧化物)至所需厚度而成。然而，热氧化物的上表面对于后续高介电常数材料层沉积工艺具有不佳的润湿特性。通过原子层沉积(atomic layer deposition，ALD)工艺110或所谓的原子层化学气相沉积(atomic layer chemical vapor deposition，ALCVD)工艺(以A+B表示之)，于界面层102上形成一高介电常数材料层104，其由ALD工艺中二个半反应组合所构成。上述半反应其中一个包括提供一金属前驱物(A)，例如四-(乙基甲基胺基酸)-铪(Tetrakis(ethylmethylamino)hafnium)(即，Hf[NCH3C2H5]4，TEMAH)，以化学吸附基底表面。另一半反应包括提供一第二前驱物(B)，例如氧物质(O species)，以化学吸附基底表面。二个半反应之间，使用不具活性的惰性气体，例如Ar或N2，来清除物理吸附于基底表面的过量前驱物A及B。通常ALD工艺由前驱物A(B)脉冲、惰性气体清洁、前驱物B(A)脉冲、惰性气体清洁及重复此顺序步骤所组成。因此，ALD工艺110进行一连串步骤而形成高介电常数材料多层膜。一初始(例如，第一)高介电常数材料层104是通过ALD而形成于界面层102的上表面。重复ALD工艺110，以在后续形成每一高介电常数材料层104直到获得所需的厚度为止。可观察到ALD工艺的初始层具有较长的酝酿期(incubation-cycle)，其原因在于界面层102上表面的润湿性不佳。因此，后续的高介电常数材料层形成岛状加层状(island-to-layer)结构(例如，粗糙成长)。因此，高介电常数材料层104与界面层102之间的界面含有缺陷112，其严重影响装置效能，例如造成栅极漏电流。
请参照图2，其显示出在一半导体基底上形成一界面层及一高介电常数材料层的示意图。半导体基底200包括一硅基底。一界面层202形成于基底200上。界面层202可包括氧化硅(SiO2)，其以公知湿化学氧化工艺而形成。相较于热氧化成长，化学氧化物的厚度易于控制在低于1nm。再者，化学氧化物的表面含有氢氧(-OH)官能基204，其对于后续高介电常数材料层沉积工艺提供良好的润湿特性。因此，通过ALD工艺所形成的高介电常数材料层的初始(第一)层具有较短的酝酿期。
通过原子层沉积工艺210于界面层202上形成一高介电常数材料层206。ALD工艺210进行一连串步骤而形成高介电常数材料多层膜。举例来说，高介电常数材料层206包括氧化铪(HfO2)。一初始(例如，第一)高介电常数材料层是通过ALD而形成于界面层202的上表面。重复ALD工艺210(例如，A+B)，以在后续形成每一高介电常数材料层206直到获得所需的厚度为止。然而，可观察到化学氧化物在块体界面层202内所产生的过量氢氧官能基212，及在其与高介电常数材料层206的界面处由大气污染源(atmosphere contamination)AMC所引起的电子陷阱214。此将于后续工艺期间引起氧化物再成长，使界面层202的厚度不当的增加。
请参照图3，其显示出在一半导体基底上形成一界面层及一高介电常数材料层的示意图。半导体基底300包括一硅基底。一界面层302形成于基底300上。界面层302可包括氧化硅(SiO2)，其以公知伴随湿式处理的热氧化工艺而形成。亦即，氧化物以图1所述的热成长而形成，而氧化层的上表面304进行一湿式处理以对于后续高介电常数材料层沉积提供良好的润湿特性。因此，在块体界面层302内具有较少的氢氧(-OH)基，且对于通过ALD工艺所形成的高介电常数材料层的初始(第一)层具有较短的酝酿期。
通过原子层沉积工艺310于界面层302上形成一高介电常数材料层306。ALD工艺310进行一连串步骤而形成高介电常数材料多层膜。举例来说，高介电常数材料层306包括氧化铪(HfO2)。一初始(例如，第一)高介电常数材料层是通过ALD而形成于界面层302的上表面。重复ALD工艺310(例如，A+B)，以在后续形成每一高介电常数材料层306直到获得所需的厚度为止。然而，可观察到在界面层302与高介电常数材料层306的界面处出现电子陷阱314及大气污染源的问题，因而在界面处引起氧化物再成长。再者，可观察到当界面层的等效氧化层厚度(equivalent oxide thickness，EOT)小于7埃时，热氧化物较图2的化学氧化物难以控制。因此，对于达到先进技术的栅极堆叠设计需求(例如，EOT小于8埃)而言会是一种挑战。
请参照图4，其显示出在一基底上形成一界面层及一高介电常数材料层的方法400。上述方法400为以单一处理工艺在上表面形成界面层。请参照图5A至图5B，其显示出根据图4方法400在基底上形成界面层及高介电常数材料层的剖面示意图。上述方法400始于区块410。提供一基底500。请参照图5A，基底500可包括一硅(Si)基底。基底500可包括不同掺杂型态(例如，N型阱区或P型阱区)，取决于公知设计需求。基底500亦包括其他单质半导体，例如锗及钻石。另外，基底500可包括一化合物半导体及/或一合金半导体。再者，基底500可选择性地包括一外延层(epi layer)，其可具有应变以提高效能，且可包括一绝缘层上覆硅(silicon-on-insulator，SOI)的结构。再者，基底500可包括Ge、Ga、As、In、Sb、Al、其组合或是其他适用于半导体装置的基底。
方法400持续进行到区块420，在基底500上形成一界面层502。请参照图5B，以等离子体工艺503所产生的自由基对硅基底500的氢(H)端进行处理，以形成界面层502。自由基可包括含水自由基。含水自由基可由含O及H原子的等离子体所产生。基底500可置入一工艺反应室，以提供等离子体工艺一适当环境。在本实施例中，等离子体工艺503可为H2O/Ar等离子体(用于产生含水自由基)，以形成氧化硅(SiO2)作为界面层502。
等离子体工艺503在工艺反应室内可具有下列的工艺条件。等离子体工艺503的温度可低于或等于500℃、总压力在0.005至10Torr的范围、等离子体功率(RF功率)低于或等于200W、H2O的分压低于或等于0.1Torr(以Ar气体稀释)、Ar的流量在1000至200sccm的范围及处理时间低于或等于1分钟。气体流量参数可用于稳定压力及反应气体浓度。另外，可通过控制暴露期(exposure period)及等离子体产生自由基的全部时间来控制上述处理程序。等离子体可产生于主工艺反应室内或是远距产生于预备室(pre-camber)内且将远距等离子体供至主工艺反应室内。
须注意的是等离子体工艺503(例如，总压力及H2O的压力)在低温(≤500℃)较易促进界面层502的厚度控制及生成较致密及无缺陷的块体界面层502。界面层502的等效氧化层厚度(EOT)可小于或等于7埃
Figure A20091017326900111
就其而言，可抑制热引扩散所造成的氧化物再成长。再者，等离子体工艺503同时改变了界面层502的上表面，以对后续高介电常数材料层的沉积(ALD或CVD)提供较佳的润湿特性(例如，氢氧(-OH)官能基504)。另外，由SiO2所构成的界面层初始形成(以其他技术)的实际厚度小于或等于5埃
Figure A20091017326900112
且可对SiO2界面层/Si基底进行上述自由基表面处理，以改善界面层的表面条件，而形成较佳的高介电常数材料层，将于以下说明。
上述方法400持续进行到区块430，在界面层502上形成高介电常数材料层506。请参照图5C，高介电常数材料层506包括氧化铪(HfO2)。高介电常数材料层506是通过ALD工艺510而形成于界面层502上。ALD工艺510进行一连串步骤而形成高介电常数材料多层膜，如之前所述。每一膜层是通过在界面层502的上表面提供阳离子前驱物(A)(例如，Hf物质，如TEMAH)而形成，并接着提供阴离子前驱物(B)(例如，O物质，如D2O)，以与阳离子前驱物反应而形成一层高介电常数材料层506。重复ALD工艺510(例如，前驱物A+前驱物B)，以在后续形成每一高介电常数材料层506直到获得所需的厚度为止。可以理解的是也可使用其他前驱物来形成高介电常数材料层506。
另外，高介电常数材料层506可包括其他介电常数材料，诸如氮氧化铪(HfON)、铪硅酸盐(HfSiO)、氮氧化铪硅(HfSiON)、氧化铪钽(HfTaO)、氮氧化铪钽(HfTaON)、氧化铪钛(HfTiO)、氮氧化铪钛(HfTiON)、氧化铪锆(HfZrO)、氮氧化铪锆(HfZrON)、氧化铪铝(HfAlO)、氮氧化铪铝(HfAlON)、氧化铪镧(HfLaO)、氮氧化铪镧(HfLaON)及其组合。另外，高介电常数材料层可通过公知金属有机化学气相沉积(metal-organic chemical vapor deposition，MOCVD)或其他适当的CVD工艺而形成。须注意的是可以原位(in-situ)方式(例如，在ALD工艺反应室内)进行界面层及高介电常数材料层的制作。换句话说，界面层502及高介电常数材料层506的制作从基底处理至高介电常数材料沉积都无须暴露于大气中。因此，较少的大气污染源位于基底500(通道)/界面层502的界面，以及界面层502/高介电常数材料层506的界面。
可以理解的是上述方法400可继续进行半导体工艺，以形成各种不同的微电子装置，例如集成电路的晶体管、电阻、电容等等。举例来说，界面层502及高介电常数材料层506可用于形成于基底500内不同的nMOSFET及pMOSFET装置的栅极介电层。
请参照图6A～图6C，其显示出另一方法以在基底上形成界面层及高介电常数材料层的剖面示意图。请参照图6A，基底600可包括一硅(Si)基底。基底600可包括不同掺杂型态(例如，N型阱区或P型阱区)，取决于公知设计需求。基底600亦包括其他单质半导体，例如锗及钻石。另外，基底600可包括一化合物半导体及/或一合金半导体。再者，基底600可选择性地包括一外延层(epi layer)，其可具有应变以提高效能，且可包括一绝缘层上覆硅(SOI)的结构。再者，基底600可包括Ge、Ga、As、In、Sb、Al、其组合或是其他适用于半导体装置的基底。
请参照图6B，以等离子体工艺或紫外线(UV)工艺所产生的自由基对硅基底600进行处理603，以形成界面层602。上述处理603可以原位的方式或非原位(ex situ)的方式(例如，暴露于大气中)来进行。自由基可包括含水自由基及/或氮/氢自由基。自由基可选择取决于所需的界面层602型态。基底600可置入一工艺反应室，以提供等离子体工艺或紫外线(UV)工艺一适当环境。含水自由基可由等离子体或UV在含O及H原子的环境所产生。举例来说，含水自由基可由使用一气体所产生，例如H2O、H2O2、H2、O2、N2、Ar、He或其组合。氮/氢自由基可由等离子体或UV在含N及H原子的环境所产生。举例来说，氮/氢自由基可由使用一气体所产生，例如NH3、N2H2、N2H4、N2、H2、NO、N2O、Ar、He或其组合。界面层602可包括氧化硅(SiO2)，其通过等离子体工艺或UV工艺及下列的工艺条件而形成。另外，界面层可包括氮化硅(SiNx)或氮氧化硅(SiOxNy)。
在一实施例中，等离子体工艺可具有下列的工艺条件。等离子体工艺的温度可低于或等于500℃、总压力在0.005至10Torr的范围、等离子体功率(RF功率)低于或等于200W、H2O的分压低于或等于0.1Torr(以Ar气体稀释)以产生含水自由基、Ar的流量在1000至200sccm的范围及处理时间低于或等于1分钟。气体流量参数可用于稳定压力及反应气体浓度。另外，可通过控制暴露期及等离子体产生自由基的全部时间来控制上述处理程序。等离子体可产生于主工艺反应室内或是远距产生于预备室内且将远距等离子体供至主工艺反应室内。
在另一实施例中，UV工艺在工艺反应室内可具有下列的工艺条件。UV工艺的温度可低于或等于500℃、总压力在0.005至10Torr的范围、波长(UV源)小于或等于200nm、H2O的分压低于或等于0.1Torr(以Ar气体稀释)以产生含水自由基、NH3的流量低于或等于500sccm以产生氮/氢自由基、Ar的流量在1000至200sccm的范围及“启用”UV的时间低于或等于1分钟。气体流量参数可用于稳定压力及反应气体浓度。另外，可通过控制暴露期及UV产生自由基的全部时间来控制上述处理程序。
须注意的是等离子体工艺及UV工艺两者(例如，总压力及H2O的压力)在低温(≤500℃)较易促进界面层602的厚度控制及生成较致密及无缺陷的块体界面层602。界面层602的等效氧化层厚度(EOT)可小于或等于7埃
Figure A20091017326900131
就其而言，可抑制热引扩散所造成的氧化物再成长。再者，等离子体工艺及UV工艺两者同时改变了界面层602的上表面，以对后续高介电常数材料层的沉积(ALD或CVD)提供较佳的润湿特性(例如，-OH或-NHx官能基604)。另外，由SiON所构成的界面层初始形成(以其他技术)的实际厚度小于或等于5埃
Figure A20091017326900132
且可对SiON界面层/Si基底进行上述自由基表面处理，以改善界面层的表面条件，而形成较佳的高介电常数材料层，将于以下说明。
请参照图6C，高介电常数材料层606包括氧化铪(HfO2)。高介电常数材料层606是通过ALD工艺610而形成于界面层602上。ALD工艺610进行一连串步骤而形成高介电常数材料多层膜。每一膜层是通过在界面层602的上表面提供阳离子前驱物(A)(例如，Hf物质，如TEMAH)而形成，并接着提供阴离子前驱物(B)(例如，O物质，如D2O)，以与阳离子前驱物反应而形成一层高介电常数材料层606。重复ALD工艺610(例如，前驱物A+前驱物B)，以在后续形成每一高介电常数材料层606直到获得所需的厚度为止。可以理解的是也可使用其他前驱物来形成高介电常数材料层606。
另外，高介电常数材料层606可包括其他介电常数材料，诸如氮氧化铪(HfON)、铪硅酸盐(HfSiO)、氮氧化铪硅(HfSiON)、氧化铪钽(HfTaO)、氮氧化铪钽(HfTaON)、氧化铪钛(HfTiO)、氮氧化铪钛(HfTiON)、氧化铪锆(HfZrO)、氮氧化铪锆(HfZrON)、氧化铪铝(HfAlO)、氮氧化铪铝(HfAlON)、氧化铪镧(HfLaO)、氮氧化铪镧(HfLaON)及其组合。另外，高介电常数材料层可通过公知金属有机化学气相沉积(MOCVD)或其他适当的CVD工艺而形成。
请参照图7A～图7C，其显示出另一方法以在基底上形成界面层及高介电常数材料层的剖面示意图。请参照图7A，基底700可包括一GaAs基底。基底700可包括不同掺杂型态(例如，N型阱区或P型阱区)，取决于公知设计需求。基底700亦包括其他单质半导体，例如锗及钻石。另外，基底700可包括一化合物半导体及/或一合金半导体。再者，基底700可选择性地包括一外延层(epi layer)，其可具有应变以提高效能，且可包括一绝缘层上覆硅(SOI)的结构。再者，基底700可包括Ge、Ga、As、In、Sb、Al、其组合或是其他适用于半导体装置的基底。
请参照图7B，以等离子体工艺或紫外线(UV)工艺所产生的自由基对GaAs基底700进行处理703，以形成界面层702。上述处理703可以原位的方式(例如，从基底处理至高介电常数材料沉积期间未暴露于大气中)或非原位(ex situ)的方式(例如，暴露于大气中)来进行。自由基可包括含硫/氢自由基。基底700可置入一工艺反应室，以提供等离子体工艺或UV工艺一适当环境。硫/氢自由基可由使用一气体所产生，例如H2S、(NH4)2S、NH3、Ar、He及其组合。在一些实施例中，可使用H2S/Ar气体混合物。在其他实施例中，可使用(NH4)2S/Ar气体混合物。在某些其他实施例中，可使用NH3/H2S/Ar气体混合物。在另一些其他实施例中，可使用H2S/He气体混合物。界面层702可包括GaSx及/或AsSx层，其通过等离子体工艺或UV工艺及下列的工艺条件而形成。
在一实施例中，等离子体工艺在工艺反应室内可具有下列的工艺条件。等离子体工艺的温度可低于或等于500℃、总压力在0.005至10Torr的范围、等离子体功率(RF功率)低于或等于200W、H2S的分压低于或等于0.1Torr(以惰性气体稀释)、NH3的流量低于或等于500sccm(以惰性气体稀释)、Ar的流量在1000至200sccm的范围及处理时间低于或等于1分钟。气体流量参数可用于稳定压力及反应气体浓度。另外，可通过控制暴露期及等离子体产生自由基的全部时间来控制上述处理程序。等离子体可产生于主工艺反应室内或是远距产生于预备室内且将远距等离子体供至主工艺反应室内。再者，可以He取代Ar或混入He，以控制自由基浓度及动量(momentum)。
在另一实施例中，UV工艺在工艺反应室内可具有下列的工艺条件。UV工艺的温度可低于或等于500℃、总压力在0.005至10Torr的范围、波长(UV源)小于或等于200nm、H2S的分压低于或等于0.1Torr(以Ar气体稀释)以产生含水自由基、NH3的流量低于或等于500sccm(以惰性气体稀释)、Ar的流量在1000至200sccm的范围及“启用”UV的时间低于或等于1分钟。气体流量参数可用于稳定压力及反应气体浓度。另外，可通过控制暴露期及UV产生自由基的全部时间来控制上述处理程序。再者，可以He取代Ar或混入He，以控制自由基浓度及动量。
须注意的是等离子体工艺及UV工艺两者(例如，总压力及H2O的压力)在低温(≤500℃)较易促进界面层702的厚度控制及生成较致密及无缺陷的块体界面层702。界面层702的等效氧化层厚度(EOT)可小于或等于7埃
Figure A20091017326900151
就其而言，可抑制热引扩散所造成的氧化物再成长。再者，等离子体工艺及UV工艺两者同时改变了界面层702的上表面，以对后续高介电常数材料层的沉积(ALD或CVD)提供较佳的润湿特性(例如，烷(-SHx)官能基704)。
请参照图7C，高介电常数材料层706包括氧化铪(HfO2)。高介电常数材料层706是通过ALD工艺710而形成于界面层702上。ALD工艺710进行一连串步骤而形成高介电常数材料多层膜。每一膜层是通过在界面层702的上表面提供阳离子前驱物(A)(例如，Hf物质，如TEMAH)而形成，并接着提供阴离子前驱物(B)(例如，O物质，如D2O)，以与阳离子前驱物反应而形成一层高介电常数材料层706。重复ALD工艺710(例如，前驱物A+前驱物B)，以在后续形成每一高介电常数材料层706直到获得所需的厚度为止。可以理解的是也可使用其他前驱物来形成高介电常数材料层706。
另外，高介电常数材料层706可包括其他介电常数材料，诸如氮氧化铪(HfON)、铪硅酸盐(HfSiO)、氮氧化铪硅(HfSiON)、氧化铪钽(HfTaO)、氮氧化铪钽(HfTaON)、氧化铪钛(HfTiO)、氮氧化铪钛(HfTiON)、氧化铪锆(HfZrO)、氮氧化铪锆(HfZrON)、氧化铪铝(HfAlO)、氮氧化铪铝(HfAlON)、氧化铪镧(HfLaO)、氮氧化铪镧(HfLaON)及其组合。另外，高介电常数材料层可通过公知金属有机化学气相沉积(MOCVD)或其他适当的CVD工艺而形成。
请参照图8，其显示出在一基底上形成一界面层及一高介电常数材料层的方法800。上述方法800为以双重处理工艺在上表面形成界面层。请参照图9A～图9D，其显示出根据图8方法800在基底上形成界面层及高介电常数材料层的剖面示意图。上述方法800始于区块810。提供一基底900。请参照图9A，基底900可包括一硅(Si)基底。基底900可包括不同掺杂型态(例如，N型阱区或P型阱区)，取决于公知设计需求。基底900亦包括其他单质半导体，例如锗及钻石。另外，基底900可包括一化合物半导体及/或一合金半导体。再者，基底900可选择性地包括一外延层(epi layer)，其可具有应变以提高效能，且可包括一绝缘层上覆硅(SOI)的结构。再者，基底900可包括Ge、Ga、As、In、Sb、Al、其组合或是其他适用于半导体装置的基底。
方法800持续进行到区块820，在基底900上形成一第一介电层902。请参照图9B，以等离子体工艺或UV工艺所产生的自由基对硅基底900进行处理903(第一处理)，以形成第一介电层902。上述处理903可以原位的方式(例如，从基底处理至高介电常数材料沉积期间未暴露于大气中)或非原位(ex situ)的方式(例如，暴露于大气中)来进行。自由基可包括含水自由基。含水自由基可由等离子体或UV在含O及H原子的环境所产生。举例来说，含水自由基可由使用一气体所产生，例如H2O、H2O2、H2、O2、N2、Ar、He或其组合。基底900可置入一工艺反应室，以提供等离子体工艺或UV工艺一适当环境。第一介电层902可包括氧化硅(SiOx)，其通过等离子体工艺或UV工艺及下列的工艺条件而形成。
在一实施例中，等离子体工艺在工艺反应室内使用一混合气体时，例如H2O/Ar，可具有下列的工艺条件。等离子体工艺的温度可低于或等于500℃、总压力在0.005至10Torr的范围、等离子体功率(RF功率)低于或等于200W、H2O的分压低于或等于0.1Torr(以惰性气体稀释)、Ar的流量在1000至200sccm的范围及处理时间低于或等于1分钟。
气体流量参数可用于稳定压力及反应气体浓度。另外，可通过控制暴露期及等离子体产生自由基的全部时间来控制上述处理程序。等离子体可产生于主工艺反应室内或是远距产生于预备室内且将远距等离子体供至主工艺反应室内。再者，可以He取代Ar或混入He，以控制自由基浓度及动量。
在另一实施例中，UV工艺在工艺反应室内使用一混合气体时，例如H2O/Ar，可具有下列的工艺条件。UV工艺的温度可低于或等于500℃、总压力在0.005至10Torr的范围、波长(UV源)小于或等于200nm、H2O的分压低于或等于0.1Torr(以惰性气体稀释)、Ar的流量在1000至200sccm的范围及“启用”UV的时间低于或等于1分钟。
气体流量参数可用于稳定压力及反应气体浓度。另外，可通过控制暴露期及UV产生自由基的全部时间来控制上述处理程序。再者，可以He取代Ar或混入He，以控制自由基浓度及动量。须注意的是第一处理903之后第一介电层902的上表面具有氢氧(-OH)官能基904。
上述方法800持续进行到区块830，在第一介电层902上形成第二介电层906。请参照图9C，以等离子体工艺或UV工艺所产生的自由基对第一介电层902进行处理908(第二处理)，以形成第二介电层906。上述处理908可以原位的方式(例如，从基底处理至高介电常数材料沉积期间未暴露于大气中)或非原位(ex situ)的方式(例如，暴露于大气中)来进行。自由基可包括氮/氢自由基。氮/氢自由基可由等离子体或UV在含N及H原子的环境所产生。举例来说，氮/氢自由基可由使用一气体所产生，例如NH3、N2H2、N2H4、N2、H2、NO、N2O、Ar、He或其组合。基底900可置入一工艺反应室，以提供等离子体工艺或UV工艺一适当环境。在本实施例中，第二介电层906可包括氮氧化硅(SiOxNy)或氮化硅(SiNx)，其通过等离子体工艺或UV工艺及下列的工艺条件而形成。
在一实施例中，等离子体工艺在工艺反应室内使用一混合气体时，例如NH3/Ar，可具有下列的工艺条件。等离子体工艺的温度可低于或等于600℃、总压力在0.005至10Torr的范围、等离子体功率(RF功率)低于或等于3000W、NH3的流量低于或等于500sccm、Ar的流量在1000至200sccm的范围及处理时间低于或等于5分钟。
气体流量参数可用于稳定压力及反应气体浓度。另外，可通过控制暴露期及等离子体产生自由基的全部时间来控制上述处理程序。等离子体可产生于主工艺反应室内或是远距产生于预备室内且将远距等离子体供至主工艺反应室内。再者，可以He取代Ar或混入He，以控制自由基浓度及动量。
在另一实施例中，UV工艺在工艺反应室内使用一混合气体时，例如NH3/Ar，可具有下列的工艺条件。UV工艺的温度可低于或等于600℃、总压力在0.005至10Torr的范围、波长(UV源)小于或等于200nm、NH3的流量低于或等于500sccm、Ar的流量在1000至200sccm的范围及“启用”UV的时间低于或等于5分钟。
气体流量参数可用于稳定压力及反应气体浓度。另外，可通过控制暴露期及UV产生自由基的全部时间来控制上述处理程序。再者，可以He取代Ar或混入He，以控制自由基浓度及动量。须注意的是第二处理908之后第二介电层906的上表面具有氨(-NHx)及/或氢氧(-OH)官能基909。
须注意的是不同的气体组合可用于第一及第二处理903及908。在一实施例中，上述处理包括一气体混合物，例如H2O/Ar、H2O/O2/Ar、H2O2/Ar或H2/O2/Ar，通过调整H及O自由基的活性及浓度以形成SiOxHy。上述处理包括一气体混合物，例如H2O/N2/Ar、H2O2/N2/Ar或H2/O2//N2，通过调整H、O及N自由基(介电层内N掺杂≤3％)的活性及浓度以形成SiOxNyHz。在其他实施例中，上述处理包括一气体混合物，例如NH3/Ar、N2H2/Ar、N2H4/Ar、N2/H2/Ar或NH3/H2/Ar，通过调整H、O及N自由基(介电层内N掺杂＞3％)的活性及浓度以形成SiOxNyHz。上述处理包括一气体混合物，例如NO/H2/Ar、N2O/H2/Ar或NH3/NO/Ar，通过调整H、O及N自由基的活性及浓度以形成SiOxNyHz。再者，第一及第二处理903及908可为第一等离子体+第二等离子体、第一UV+第二等离子体、第一等离子体+第二UV及第一UV+第二UV。
须注意的是等离子体工艺及UV工艺两者(例如，总压力及H2O的压力)在低温(≤500℃)较易促进第一介电层902的厚度控制(等效氧化层厚度(EOT)≤7埃
Figure A20091017326900191
)及生成较致密及无缺陷的块体界面层。就其而言，可抑制热引扩散所造成的氧化物再成长。再者，等离子体工艺及UV工艺两者同时在低温(≤600℃)改变了界面层的上表面，以对后续高介电常数材料层的沉积(ALD或CVD)提供较佳的润湿特性(例如，-NHx或-OH官能基909)。就其而言，第二介电层906的实际厚度小于或等于3埃
Figure A20091017326900192
因此第一及第二介电层902及906总EOT小于或等于7埃
Figure A20091017326900193
方法800持续进行到区块840，在界面层(第一及第二介电层902及906)上形成高介电常数材料层912。第二处理908之后，第二介电层906的上表面具有-OH及/或-NHx官能基909，以对后续高介电常数材料层的沉积(ALD或CVD)提供较佳的润湿界面。请参照图9D，高介电常数材料层912包括氧化铪(HfO2)。高介电常数材料层912是通过ALD工艺914而形成于界面层902及906上。ALD工艺914进行一连串步骤而形成高介电常数材料多层膜，如之前所述。每一膜层是通过在界面层902及906的上表面提供阳离子前驱物(A)(例如，Hf物质，如TEMAH)而形成，并接着提供阴离子前驱物(B)(例如，O物质，如D2O)，以与阳离子前驱物反应而形成一层高介电常数材料层912。重复ALD工艺914(例如，前驱物A+前驱物B)，以在后续形成每一高介电常数材料层912直到获得所需的厚度为止。可以理解的是也可使用其他前驱物来形成高介电常数材料层912。
另外，高介电常数材料层912可包括其他介电常数材料，诸如氮氧化铪(HfON)、铪硅酸盐(HfSiO)、氮氧化铪硅(HfSiON)、氧化铪钽(HfTaO)、氮氧化铪钽(HfTaON)、氧化铪钛(HfTiO)、氮氧化铪钛(HfTiON)、氧化铪锆(HfZrO)、氮氧化铪锆(HfZrON)、氧化铪铝(HfAlO)、氮氧化铪铝(HfAlON)、氧化铪镧(HfLaO)、氮氧化铪镧(HfLaON)及其组合。另外，高介电常数材料层可通过公知金属有机化学气相沉积(MOCVD)或其他适当的CVD工艺而形成。
可以理解的是上述方法400可继续进行半导体工艺，以形成各种不同的微电子装置，例如集成电路的晶体管、电阻、电容等等。举例来说，界面层502及高介电常数材料层506可用于形成于基底500内不同的nMOSFET及pMOSFET装置的栅极介电层。
请参照图10A～图10D，其显示出根据图8方法800的另一实施例而在基底上形成界面层及高介电常数材料层的剖面示意图。图10A～图10D的实施例同样在一基底上进行双重处理工艺以及沉积高介电常数材料层。因此，除了以下所述的差异之外，图10A～图10D的半导体装置相似于图9A～图9D的半导体装置。请参照图10A，一基底1000可包括一硅(Si)基底。基底1000可包括不同掺杂型态(例如，N型阱区或P型阱区)，取决于公知设计需求。基底1000亦包括其他单质半导体，例如锗及钻石。另外，基底1000可包括一化合物半导体及/或一合金半导体。再者，基底1000可选择性地包括一外延层(epi layer)，其可具有应变以提高效能，且可包括一绝缘层上覆硅(SOI)的结构。再者，基底1000可包括Ge、Ga、As、In、Sb、Al、其组合或是其他适用于半导体装置的基底。
请参照图10B，一介电层1002是通过等离子体工艺或UV工艺所产生的自由基对硅基底1000进行处理1003(第一处理)而形成。上述处理1003可以原位的方式(例如，从基底处理至高介电常数材料沉积期间未暴露于大气中)或非原位(ex situ)的方式(例如，暴露于大气中)来进行。在本实施例中，自由基可包括氮/氢自由基。氮/氢自由基可由等离子体或UV在含N及H原子的环境所产生。举例来说，氮/氢自由基可由使用一气体所产生，例如NH3、N2H2、N2H4、N2、H2、NO、N2O、Ar、He或其组合。基底1000可置入一工艺反应室，以提供等离子体工艺或UV工艺一适当环境。在本实施例中，介电层1002可通过等离子体工艺或UV工艺及下列的工艺条件而形成。
在一实施例中，等离子体工艺在工艺反应室内使用一混合气体时，例如NH3/Ar，可具有下列的工艺条件。等离子体工艺的温度可低于或等于600℃、总压力在0.005至10Torr的范围、等离子体功率(RF功率)低于或等于3000W、NH3的流量低于或等于500sccm、Ar的流量在1000至200sccm的范围及处理时间低于或等于5分钟。
气体流量参数可用于稳定压力及反应气体浓度。另外，可通过控制暴露期及等离子体产生自由基的全部时间来控制上述处理程序。等离子体可产生于主工艺反应室内或是远距产生于预备室内且将远距等离子体供至主工艺反应室内。再者，可以He取代Ar或混入He，以控制自由基浓度及动量。
在另一实施例中，UV工艺在工艺反应室内使用一混合气体时，例如NH3/Ar，可具有下列的工艺条件。UV工艺的温度可低于或等于600℃、总压力在0.005至10Torr的范围、波长(UV源)小于或等于200nm、NH3的流量低于或等于500sccm、Ar的流量在1000至200sccm的范围及“启用”UV的时间低于或等于5分钟。
气体流量参数可用于稳定压力及反应气体浓度。另外，可通过控制暴露期及UV产生自由基的全部时间来控制上述处理程序。再者，可以He取代Ar或混入He，以控制自由基浓度及动量。
在本实施例中，介电层1002可包括一氮化硅(SiNx)，其上表面具有氨(-NHx)官能基1004。在一些实施例中，介电层1002可包括一氮氧化硅(SiOxNy)，其上表面具有氨(-NHx)官能基。介电层1002一开始形成部分的界面层。
请参照图10C，对分别含有SiNx及Si再氧化的介电层1002进行处理1008，以形成介电层1006。再氧化工艺可在氧化环境下进行热退火。在本实施例中，通过等离子体工艺或UV工艺所产生的自由基对介电层1002的上表面及其与硅基底1000的界面进行处理1008。因此，介电层1006形成于硅基底1000上，而一介电层1002a形成于介电层1006上。上述处理1008可以原位的方式(例如，未暴露于大气中)或非原位(ex situ)的方式(例如，从基底处理至高介电常数材料沉积期间暴露于大气中)来进行。在本实施例中，自由基可包括含水自由基。含水自由基可由等离子体或UV在含O及H原子的环境所产生。举例来说，含水自由基可由使用一气体所产生，例如H2O、H2O2、H2、O2、N2、Ar、He或其组合。基底1000可置入一工艺反应室，以提供等离子体工艺或UV工艺一适当环境。介电层1006可通过下列的工艺条件而形成。
在一实施例中，等离子体工艺在工艺反应室内使用一混合气体时，例如H2O/Ar，可具有下列的工艺条件。等离子体工艺的温度可低于或等于500℃、总压力在0.005至10Torr的范围、等离子体功率(RF功率)低于或等于200W、H2O的分压低于或等于0.1Torr(以惰性气体稀释)、Ar的流量在1000至200sccm的范围及处理时间低于或等于1分钟。
气体流量参数可用于稳定压力及反应气体浓度。另外，可通过控制暴露期及等离子体产生自由基的全部时间来控制上述处理程序。等离子体可产生于主工艺反应室内或是远距产生于预备室内且将远距等离子体供至主工艺反应室内。再者，可以He取代Ar或混入He，以控制自由基浓度及动量。
在另一实施例中，UV工艺在工艺反应室内使用一混合气体时，例如H2O/Ar，可具有下列的工艺条件。UV工艺的温度可低于或等于500℃、总压力在0.005至10Torr的范围、波长(UV源)小于或等于200nm、H2O的分压低于或等于0.1Torr(以惰性气体稀释)、Ar的流量在1000至200sccm的范围及“启用”UV的时间低于或等于1分钟。
气体流量参数可用于稳定压力及反应气体浓度。另外，可通过控制暴露期及UV产生自由基的全部时间来控制上述处理程序。再者，可以He取代Ar或混入He，以控制自由基浓度及动量。
在本实施例中，经过等离子体或UC工艺之后，介电层1006可包括氧化硅(SiOx)，而介电层1002a可包括氮氧化硅(SiOxNy)。在其他实施例中，介电层1006可包括氧化硅氮氧化硅(SiOxNy)。介电层1002a及1006构成界面层。
须注意的是不同的气体组合可用于第一及第二处理1003及1008。在一实施例中，上述处理包括一气体混合物，例如H2O/Ar、H2O/O2/Ar、H2O2/Ar或H2/O2/Ar，通过调整H及O自由基的活性及浓度以形成SiOxHy。上述处理包括一气体混合物，例如H2O/N2/Ar、H2O2/N2/Ar或H2/O2//N2，通过调整H、O及N自由基(介电层内N掺杂≤3％)的活性及浓度以形成SiOxNyHz。在其他实施例中，上述处理包括一气体混合物，例如NH3/Ar、N2H2/Ar、N2H4/Ar、N2/H2/Ar或NH3/H2/Ar，通过调整H、O及N自由基(介电层内N掺杂＞3％)的活性及浓度以形成SiOxNyHz。上述处理包括一气体混合物，例如NO/H2/Ar、N2O/H2/Ar或NH3/NO/Ar，通过调整H、O及N自由基的活性及浓度以形成SiOxNyHz。再者，第一及第二处理1003及1008可为第一等离子体+第二等离子体、第一UV+第二等离子体、第一等离子体+第二UV及第一UV+第二UV。
须注意的是等离子体工艺及UV工艺两者(例如，总压力及H2O的压力)在低温(≤500℃)较易促进介电层1006的厚度控制(等效氧化层厚度(EOT)≤7埃
Figure A20091017326900231
)及生成较致密及无缺陷的块体界面层。就其而言，可抑制热引扩散所造成的氧化物再成长。再者，等离子体工艺及UV工艺两者同时在低温(≤600℃)改变了界面层的上表面，以对后续高介电常数材料层的沉积(ALD或CVD)提供较佳的润湿特性(例如，(-OH)或(-NHx)官能基1009)。就其而言，介电层1002a的实际厚度小于或等于3埃
Figure A20091017326900232
因此介电层1002a及1006总EOT小于或等于7埃
Figure A20091017326900233
第二处理1008之后，介电层1002a的上表面具有(-OH)及/或(-NHx)官能基1009，以对后续高介电常数材料层的沉积(ALD或CVD)提供较佳的润湿界面。请参照图10D，高介电常数材料层1012包括氧化铪(HfO2)。高介电常数材料层1012是通过ALD工艺1014而形成于界面层(介电层1002a及1006)上。ALD工艺1014进行一连串步骤而形成高介电常数材料多层膜，如之前图9所述。每一膜层是通过在界面层(介电层1002a及1006)的上表面提供阳离子前驱物(A)(例如，Hf物质，如TEMAH)而形成，并接着提供阴离子前驱物(B)(例如，O物质，如D2O)，以与阳离子前驱物反应而形成一层高介电常数材料层1012。重复ALD工艺1014(例如，前驱物A+前驱物B)，以在后续形成每一高介电常数材料层1012直到获得所需的厚度为止。可以理解的是也可使用其他前驱物来形成高介电常数材料层1012。
另外，高介电常数材料层1012可包括其他介电常数材料，诸如氮氧化铪(HfON)、铪硅酸盐(HfSiO)、氮氧化铪硅(HfSiON)、氧化铪钽(HfTaO)、氮氧化铪钽(HfTaON)、氧化铪钛(HfTiO)、氮氧化铪钛(HfTiON)、氧化铪锆(HfZrO)、氮氧化铪锆(HfZrON)、氧化铪铝(HfAlO)、氮氧化铪铝(HfAlON)、氧化铪镧(HfLaO)、氮氧化铪镧(HfLaON)及其组合。另外，高介电常数材料层可通过公知金属有机化学气相沉积(MOCVD)或其他适当的CVD工艺而形成。
可以理解的是上述基底900及1000可继续进行半导体工艺，以形成各种不同的微电子装置，例如集成电路的晶体管、电阻、电容等等。举例来说，界面层(介电层902及906及介电层1002a及1006)及高介电常数材料层912及1012可用于不同的nFET及pFET装置的栅极介电层。举例来说，可在高介电常数材料层上形成一金属层。金属层包括N功函数(work function)金属(N-金属)或P功函数(P-金属)。金属层可通过各种沉积技术而形成，例如物理气相沉积(physical vapor deposition，PVD)或溅镀、CVD、ALD、电镀或其他适当的技术。一多晶硅(poly)层可通过CVD或其他适当的技术而形成于金属层上。一硬式掩模(hard mask)层可行成于多晶硅层上。上述各个层可图案化而形成公知栅极结构。
本发明不同实施例具有不同的优点。举例来说，以上叙述的方法在低温下提供一致密且表面改变的界面层。因此，一些优点包括：(1)基底(通道)/界面层界面钝化；(2)因高介电常数前驱物而改变界面层表面(较接的润湿界面)；(3)在高介电常数材料沉积之后，界面层/高介电常数材料的界面钝化；(4)界面处的大气污染源少；(5)抑制热引扩散；(6)栅极介电层的EOT小于10埃。因此，栅极介电层的EOT符合先尽的技术要求(例如，45nm以下)。因此，上述方法相容于现行CMOS工艺技术，而可轻易整合至现行的工艺设备及装置技术。可以理解的是不同实施例提供不同的优点，而对于所有实施例而言，没有特定的优点是不可或缺的。
以上叙述许多实施例的特征，使本领域普通技术人员能够清楚理解以下的说明。本领域普通技术人员能够理解其可利用本发明公开内容为基础以设计或更动其他工艺及结构而完成相同于上述实施例的目的及/或达到相同于上述实施例的优点。本领域普通技术人员亦能够理解不脱离本发明的精神和范围的等效构造可在不脱离本发明的精神和范围内作任意的更动、替代与润饰。举例来说，上述实施例的界面层及高介电常数材料层可用于前栅极(gatefirst)工艺、后栅极(gate last)工艺以及包括前栅极工艺及后栅极工艺的混合工艺，以形成具有高介电常数栅极介电层及金属栅极配置的装置。

Claims (15)

1.一种半导体装置的制造方法，包括：
提供一基底；
以自由基对该基底进行处理，而在其上形成一界面层，其中该自由基是择自于以下群族：含水自由基、氮/氢自由基及硫/氢自由基；以及
在该界面层上形成一高介电常数材料层。
2.如权利要求1所述的半导体装置的制造方法，其中形成该界面层包括通过一等离子体工艺产生该自由基，其中该等离子体工艺条件包括温度低于500℃、总压力在0.005至10Torr的范围、等离子体功率低于200W及时间低于1分钟。
3.如权利要求1所述的半导体装置的制造方法，其中形成该界面层包括通过一紫外线工艺产生该自由基，其中紫外线工艺条件包括温度低于500℃、总压力在0.005至10Torr的范围、波长低于200nm及时间低于1分钟。
4.如权利要求1所述的半导体装置的制造方法，其中该自由基由一气体所产生，其择自于以下群族：H2O、H2O2、H2、O2、N2、H2S、(NH4)2S、NH3、N2H2、N2H4、NO、N2O、Ar、He及其组合。
5.如权利要求4所述的半导体装置的制造方法，其中该含水自由基由一H2O/Ar混合气体所产生，且H2O的分压低于0.1Torr。
6.如权利要求4所述的半导体装置的制造方法，其中该氮/氢自由基由一NH3/Ar混合气体所产生，且NH3的流量低于500sccm。
7.如权利要求4所述的半导体装置的制造方法，其中该硫/氢自由基由一H2S/He混合气体所产生，且H2S的分压低于0.1Torr。
8.一种半导体装置的制造方法，包括：
提供一基底；
对该基底进行一第一处理，以在该基底上形成一第一介电层，该第一处理包括第一自由基；
对该第一介电层进行一第二处理，以在该基底上形成一第二介电层，该第二处理包括不同于该第一自由基的第二自由基，其中每一第一及第二自由基包括含水自由基及氮/氢自由基的其中一个；以及
在该第一及第二介电层上形成一高介电常数材料层。
9.如权利要求8所述的半导体装置的制造方法，其中该第一及该第二自由基的其中一个由一气体所产生，其择自于以下群族：NH3、N2H2、N2H4、N2、NO、N2O、H2O、H2O2、H2、O2、Ar、He及其组合。
10.如权利要求8所述的半导体装置的制造方法，其中每一第一及第二处理包括等离子体工艺及紫外线工艺的其中一个。
11.如权利要求10所述的半导体装置的制造方法，其中该等离子体工艺条件包括以下其中一个：
使用一H2O/Ar混合气体，且H2O的分压低于0.1Torr、Ar的流量在1000至200sccm的范围、温度低于500℃、总压力在0.005至10Torr的范围、等离子体功率低于200W及时间低于1分钟；以及
使用一NH3/Ar混合气体，且NH3的流量低于500sccm、Ar的流量在1000至200sccm的范围、温度低于600℃、总压力在0.005至10Torr的范围、等离子体功率低于3kW及时间低于5分钟。
12.如权利要求10所述的半导体装置的制造方法，其中该紫外线工艺条件包括以下其中一个：
使用一H2O/Ar混合气体，且H2O的分压低于0.1Torr、Ar的流量在1000至200sccm的范围、温度低于500℃、总压力在0.005至10Torr的范围、波长低于200nm及时间低于1分钟；以及
使用一NH3/Ar混合气体，且NH3的流量低于500sccm、Ar的流量在1000至200sccm的范围、温度低于600℃、总压力在0.005至10Torr的范围、波长低于200nm及时间低于5分钟。
13.一种半导体装置的制造方法，包括：
提供一基底；
对该基底进行至少一处理，以在该基底上形成一界面层，该处理包括等离子体工艺及紫外线工艺的其中一个，且该处理是使用自由基，其择自于以下群族：含水自由基、氮/氢自由基及硫/氢自由基；以及
在该界面层上形成一高介电常数材料层。
14.如权利要求13所述的半导体装置的制造方法，其中形成该界面层包括：
对该基底进行一第一处理，以在该基底上形成一第一介电层，该第一处理包括第一自由基；
对该第一介电层进行一第二处理，以在该基底上形成一第二介电层，该第二处理包括不同于该第一自由基的第二自由基。
15.如权利要求13所述的半导体装置的制造方法，其中形成该界面层包括：
在硅基底上形成一SiO2层及一SiON层的其中一个；以及
对该SiO2层/硅基底及该SiON层/硅基底的其中一个进行至少一处理；
其中该SiO2层及该SiON层的其中一个的初始实际厚度不超过5埃。
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