TWI397124B - 半導體裝置的製造方法 - Google Patents

半導體裝置的製造方法 Download PDF

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Publication number
TWI397124B
TWI397124B TW098131886A TW98131886A TWI397124B TW I397124 B TWI397124 B TW I397124B TW 098131886 A TW098131886 A TW 098131886A TW 98131886 A TW98131886 A TW 98131886A TW I397124 B TWI397124 B TW I397124B
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Taiwan
Prior art keywords
layer
dielectric constant
substrate
constant material
high dielectric
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TW098131886A
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English (en)
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TW201013784A (en
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Che Hao Chang
Cheng Hao Hou
Chen Hua Yu
Tai Bor Wu
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Taiwan Semiconductor Mfg
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Publication of TW201013784A publication Critical patent/TW201013784A/zh
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Description

半導體裝置的製造方法
本發明係有關於一種半導體製程，特別是有關於一種用於金屬閘極的高介電常數閘極介電層的製造方法。
半導體積體電路(integrated circuit,IC)工業已經歷快速的成長。在IC材料與設計的技術進展已造就各個IC世代，每一世代的電路都比前世代來得更小更複雜。然而，這些進展卻增加IC製造及加工的複雜度，而因應這些進展，IC製造及加工需要類似的演進。在IC進展課題中，功能密度(即，單位晶片面積的內連裝置數量)普遍增加，而幾何尺寸(即，製程所能形成的最小部件(或線))則下降。上述尺寸微縮製程因生產效率的增加及成本的降低而有所助益。而降低尺寸比例產生相對較高的功率消耗(power dissipation)值，其可藉由使用低功耗裝置而獲得解決，例如互補式金氧半(complementary metal-oxide-semiconductor,CMOS)裝置。
在尺寸比例微縮發展期間，使用各種不同的材料作為CMOS裝置的閘極電極及閘極介電層。而這些裝置的製造希望以金屬材料作為閘極電極，且以高介電常數(high-k)材料作為閘極介電層。通常在高介電常數材料層與矽基底之間會形成一界面(interfacial)層，例如氧化層，以促進高介電常數材料層的形成並改善界面處的電特性。然而，當形成界面層時會引起一些問題，例如後續製程期間對於高介電常數材料沉積的潤濕(wetting)特性不佳及發生氧化物再成長(re-growth)。
因此，有必要尋求一種新的改善方法，用以在基底上形成界面層及高介電常數材料層。
本發明一實施例提供一種半導體裝置的製造方法，包括：提供一基底；以自由基對基底進行處理，而在其上形成一界面層，其中自由基係擇自於以下群族：含水自由基、氮/氫自由基及硫/氫自由基；以及在界面層上形成一高介電常數材料層。
本發明另一實施例提供一種半導體裝置的製造方法，包括：提供一基底；對基底進行一第一處理，以在基底上形成一第一介電層，第一處理包括第一自由基；對第一介電層進行一第二處理，以在基底上形成一第二介電層，第二處理包括不同於第一自由基的第二自由基，其中每一第一及第二自由基包括含水自由基或氮/氫自由基；以及在第一及第二介電層上形成一高介電常數材料層。
本發明又另一實施例提供一種半導體裝置的製造方法，包括：提供一基底；對基底進行至少一處理，以在基底上形成一界面層，處理包括電漿製程及紫外線製程的其中一個，且該處理係使用自由基，其擇自於以下群族：含水自由基、氮/氫自由基及硫/氫自由基；以及在界面層上形成一高介電常數材料層。
可瞭解的是以下的揭露內容提供許多不同的實施例或範例，用以實施各個實施例的不同特徵。而以下所揭露的內容是敘述各個構件及其排列方式的特定範例，以求簡化本發明的說明。當然，這些特定的範例並非用以限定本發明。再者，本說明書以下的揭露內容敘述了將一第一特徵形成於一第二特徵之上或上方，其表示包含了所形成的上述第一特徵與上述第二特徵是直接接觸的實施例，亦包含了尚可將額外的特徵形成於第一特徵與第二特徵之間而使第一特徵與第二特徵並未直接接觸的實施例。為了達到簡化及清晰的目的，不同特徵可能以不同尺寸比例繪示。
請參照第1圖，其繪示出在一半導體基底上形成一界面層及一高介電常數材料層的示意圖。半導體基底100包括一矽基底。基底100可包括不同的摻雜型態，取決於習知設計需求。基底100亦包括其他單質(elementary)半導體，例如鍺及鑽石。另外，基底100可包括一化合物半導體及/或一合金半導體。再者，基底100可選擇性地包括一磊晶層(epi layer)，其可具有應變以提高效能，且可包括一絕緣層上覆矽(silicon-on-insulator,SOI)的結構。
一界面層102形成於基底100上。界面層102可包括氧化矽(SiO2 )，其以習知熱氧化成長一SiO2 層(例如，熱氧化物)至所需厚度而成。然而，熱氧化物的上表面對於後續高介電常數材料層沉積製程具有不佳的潤濕特性。藉由原子層沉積(atomic layer deposition,ALD)製程110或所謂的原子層化學氣相沉積(atomic layer chemical vapor deposition,ALCVD)製程(以A+B表示之)，於界面層102上形成一高介電常數材料層104，其由ALD製程中二個半反應組合所構成。上述半反應其中一個包括提供一金屬前驅物(A)，例如四-(乙基甲基胺基酸)-鉿(Tetrakis(ethylmethylamino)hafnium)(即，Hf[NCH3 C2 H5 ]4 ,TEMAH)，以化學吸附基底表面。另一半反應包括提供一第二前驅物(B)，例如氧物質(O species)，以化學吸附基底表面。二個半反應之間，使用不具活性的惰性氣體，例如Ar或N2 ，來清除物理吸附於基底表面的過量前驅物A及B。通常ALD製程由前驅物A(B)脈衝、惰性氣體清潔、前驅物B(A)脈衝、惰性氣體清潔及重複此順序步驟所組成。因此，ALD製程110進行一連串步驟而形成高介電常數材料多層膜。一初始(例如，第一)高介電常數材料層104係藉由ALD而形成於界面層102的上表面。重複ALD製程110，以在後續形成每一高介電常數材料層104直到獲得所需的厚度為止。可觀察到ALD製程的初始層具有較長的醞釀期(incubation-cycle)，其原因在於界面層102上表面的潤濕性不佳。因此，後續的高介電常數材料層形成島狀加層狀(island-to-layer)結構(例如，粗糙成長)。因此，高介電常數材料層104與界面層102之間的界面含有缺陷112，其嚴重影響裝置效能，例如造成閘極漏電流。
請參照第2圖，其繪示出在一半導體基底上形成一界面層及一高介電常數材料層的示意圖。半導體基底200包括一矽基底。一界面層202形成於基底200上。界面層202可包括氧化矽(SiO2 )，其以習知濕化學氧化製程而形成。相較於熱氧化成長，化學氧化物的厚度易於控制在低於1nm。再者，化學氧化物的表面含有氫氧(-OH)官能基204，其對於後續高介電常數材料層沉積製程提供良好的潤濕特性。因此，藉由ALD製程所形成的高介電常數材料層的初始(第一)層具有較短的醞釀期。
藉由原子層沉積製程210於界面層202上形成一高介電常數材料層206。ALD製程210進行一連串步驟而形成高介電常數材料多層膜。舉例來說，高介電常數材料層206包括氧化鉿(HfO2 )。一初始(例如，第一)高介電常數材料層係藉由ALD而形成於界面層202的上表面。重複ALD製程210(例如，A+B)，以在後續形成每一高介電常數材料層206直到獲得所需的厚度為止。然而，可觀察到化學氧化物在塊體界面層202內所產生的過量氫氧官能基212，及在其與高介電常數材料層206的界面處由大氣污染源(atmosphere contamination)AMC所引起的電子陷阱214。此將於後續製程期間引起氧化物再成長，使界面層202的厚度不當的增加。
請參照第3圖，其繪示出在一半導體基底上形成一界面層及一高介電常數材料層的示意圖。半導體基底300包括一矽基底。一界面層302形成於基底300上。界面層302可包括氧化矽(SiO2 )，其以習知伴隨濕式處理的熱氧化製程而形成。亦即，氧化物以第1圖所述的熱成長而形成，而氧化層的上表面304進行一濕式處理以對於後續高介電常數材料層沉積提供良好的潤濕特性。因此，在塊體界面層302內具有較少的氫氧(-OH)基，且對於藉由ALD製程所形成的高介電常數材料層的初始(第一)層具有較短的醞釀期。
藉由原子層沉積製程310於界面層302上形成一高介電常數材料層306。ALD製程310進行一連串步驟而形成高介電常數材料多層膜。舉例來說，高介電常數材料層306包括氧化鉿(HfO2 )。一初始(例如，第一)高介電常數材料層係藉由ALD而形成於界面層302的上表面。重複ALD製程310(例如，A+B)，以在後續形成每一高介電常數材料層306直到獲得所需的厚度為止。然而，可觀察到在界面層302與高介電常數材料層306的界面處出現電子陷阱314及大氣污染源的問題，因而在界面處引起氧化物再成長。再者，可觀察到當界面層的等效氧化層厚度(equivalent oxide thickness,EOT)小於7埃()時，熱氧化物較第2圖的化學氧化物難以控制。因此，對於達到先進技術的閘極堆疊設計需求(例如，EOT小於8埃)而言會是一種挑戰。
請參照第4圖，其繪示出在一基底上形成一界面層及一高介電常數材料層的方法400。上述方法400為以單一處理製程在上表面形成界面層。請參照第5A至5B圖，其繪示出根據第4圖方法400在基底上形成界面層及高介電常數材料層的剖面示意圖。上述方法400始於區塊410。提供一基底500。請參照第5A圖，基底500可包括一矽(Si)基底。基底500可包括不同摻雜型態(例如，N型井區或P型井區)，取決於習知設計需求。基底500亦包括其他單質半導體，例如鍺及鑽石。另外，基底500可包括一化合物半導體及/或一合金半導體。再者，基底500可選擇性地包括一磊晶層(epi layer)，其可具有應變以提高效能，且可包括一絕緣層上覆矽(silicon-on-insulator,SOI)的結構。再者，基底500可包括Ge、Ga、As、In、Sb、Al、其組合或是其他適用於半導體裝置的基底。
方法400持續進行到區塊420，在基底500上形成一界面層502。請參照第5B圖，以電漿製程503所產生的自由基對矽基底500的氫(H)端進行處理，以形成界面層502。自由基可包括含水自由基。含水自由基可由含O及H原子的電漿所產生。基底500可置入一製程反應室，以提供電漿製程一適當環境。在本實施例中，電漿製程503可為H2 O/Ar電漿(用於產生含水自由基)，以形成氧化矽(SiO2 )作為界面層502。
電漿製程503在製程反應室內可具有下列的製程條件。電漿製程503的溫度可低於或等於500℃、總壓力在0.005至10Torr的範圍、電漿功率(RF功率)低於或等於200W、H2 O的分壓低於或等於0.1Torr(以Ar氣體稀釋)、Ar的流量在1000至200sccm的範圍及處理時間低於或等於1分鐘。氣體流量參數可用於穩定壓力及反應氣體濃度。另外，可藉由控制暴露期(exposure period)及電漿產生自由基的全部時間來控制上述處理程序。電漿可產生於主製程反應室內或是遠距產生於預備室(pre-camber)內且將遠距電漿供至主製程反應室內。
須注意的是電漿製程503(例如，總壓力及H2 O的壓力)在低溫()較易促進界面層502的厚度控制及生成較緻密及無缺陷的塊體界面層502。界面層502的等效氧化層厚度(EOT)可小於或等於7埃()。就其而言，可抑制熱引擴散所造成的氧化物再成長。再者，電漿製程503同時改變了界面層502的上表面，以對後續高介電常數材料層的沉積(ALD或CVD)提供較佳的潤濕特性(例如，氫氧(-OH)官能基504)。另外，由SiO2 所構成的界面層初始形成(以其他技術)的實際厚度小於或等於5埃()，且可對SiO2 界面層/Si基底進行上述自由基表面處理，以改善界面層的表面條件，而形成較佳的高介電常數材料層，將於以下說明。
上述方法400持續進行到區塊430，在界面層502上形成高介電常數材料層506。請參照第5C圖，高介電常數材料層506包括氧化鉿(HfO2 )。高介電常數材料層506係藉由ALD製程510而形成於界面層502上。ALD製程510進行一連串步驟而形成高介電常數材料多層膜，如之前所述。每一膜層係藉由在界面層502的上表面提供陽離子前驅物(A)(例如，Hf物質，如TEMAH)而形成，並接著提供陰離子前驅物(B)(例如，O物質，如D2 O)，以與陽離子前驅物反應而形成一層高介電常數材料層506。重複ALD製程510(例如，前驅物A+前驅物B)，以在後續形成每一高介電常數材料層506直到獲得所需的厚度為止。可以理解的是也可使用其他前驅物來形成高介電常數材料層506。
另外，高介電常數材料層506可包括其他介電常數材料，諸如氮氧化鉿(HfON)、鉿矽酸鹽(HfSiO)、氮氧化鉿矽(HfSiON)、氧化鉿鉭(HfTaO)、氮氧化鉿鉭(HfTaON)、氧化鉿鈦(HfTiO)、氮氧化鉿鈦(HfTiON)、氧化鉿鋯(HfZrO)、氮氧化鉿鋯(HfZrON)、氧化鉿鋁(HfAlO)、氮氧化鉿鋁(HfAlON)、氧化鉿鑭(HfLaO)、氮氧化鉿鑭(HfLaON)及其組合。另外，高介電常數材料層可藉由習知金屬有機化學氣相沉積(metal-organic chemical vapor deposition,MOCVD)或其他適當的CVD製程而形成。須注意的是可以原位(in-situ)方式(例如，在ALD製程反應室內)進行界面層及高介電常數材料層的製作。換句話說，界面層502及高介電常數材料層506的製作從基底處理至高介電常數材料沉積都無須暴露於大氣中。因此，較少的大氣污染源位於基底500(通道)/界面層502的界面，以及界面層502/高介電常數材料層506的界面。
可以理解的是上述方法400可繼續進行半導體製程，以形成各種不同的微電子裝置，例如積體電路的電晶體、電阻、電容等等。舉例來說，界面層502及高介電常數材料層506可用於形成於基底500內不同的nMOSFET及pMOSFET裝置的閘極介電層。
請參照第6A至6C圖，其繪示出另一方法以在基底上形成界面層及高介電常數材料層的剖面示意圖。請參照第6A圖，基底600可包括一矽(Si)基底。基底600可包括不同摻雜型態(例如，N型井區或P型井區)，取決於習知設計需求。基底600亦包括其他單質半導體，例如鍺及鑽石。另外，基底600可包括一化合物半導體及/或一合金半導體。再者，基底600可選擇性地包括一磊晶層(epi layer)，其可具有應變以提高效能，且可包括一絕緣層上覆矽(SOI)的結構。再者，基底600可包括Ge、Ga、As、In、Sb、Al、其組合或是其他適用於半導體裝置的基底。
請參照第6B圖，以電漿製程或紫外線(UV)製程所產生的自由基對矽基底600進行處理603，以形成界面層602。上述處理603可以原位的方式或非原位(ex situ)的方式(例如，暴露於大氣中)來進行。自由基可包括含水自由基及/或氮/氫自由基。自由基可選擇取決於所需的界面層602型態。基底600可置入一製程反應室，以提供電漿製程或紫外線(UV)製程一適當環境。含水自由基可由電漿或UV在含O及H原子的環境所產生。舉例來說，含水自由基可由使用一氣體所產生，例如H2 O、H2 O2 、H2 、O2 、N2 、Ar、He或其組合。氮/氫自由基可由電漿或UV在含N及H原子的環境所產生。舉例來說，氮/氫自由基可由使用一氣體所產生，例如NH3 、N2 H2 、N2 H4 、N2 、H2 、NO、N2 O、Ar、He或其組合。界面層602可包括氧化矽(SiO2 )，其藉由電漿製程或UV製程及下列的製程條件而形成。另外，界面層可包括氮化矽(SiNx )或氮氧化矽(SiOx Ny )。
在一實施例中，電漿製程可具有下列的製程條件。電漿製程的溫度可低於或等於500℃、總壓力在0.005至10Torr的範圍、電漿功率(RF功率)低於或等於200W、H2 O的分壓低於或等於0.1Torr(以Ar氣體稀釋)以產生含水自由基、Ar的流量在1000至200sccm的範圍及處理時間低於或等於1分鐘。氣體流量參數可用於穩定壓力及反應氣體濃度。另外，可藉由控制暴露期及電漿產生自由基的全部時間來控制上述處理程序。電漿可產生於主製程反應室內或是遠距產生於預備室內且將遠距電漿供至主製程反應室內。
在另一實施例中，UV製程在製程反應室內可具有下列的製程條件。UV製程的溫度可低於或等於500℃、總壓力在0.005至10Torr的範圍、波長(UV源)小於或等於200nm、H2 O的分壓低於或等於0.1Torr(以Ar氣體稀釋)以產生含水自由基、NH3 的流量低於或等於500sccm以產生氮/氫自由基、Ar的流量在1000至200sccm的範圍及”啟用”UV的時間低於或等於1分鐘。氣體流量參數可用於穩定壓力及反應氣體濃度。另外，可藉由控制暴露期及UV產生自由基的全部時間來控制上述處理程序。
須注意的是電漿製程及UV製程兩者(例如，總壓力及H2 O的壓力)在低溫()較易促進界面層602的厚度控制及生成較緻密及無缺陷的塊體界面層602。界面層602的等效氧化層厚度(EOT)可小於或等於7埃()。就其而言，可抑制熱引擴散所造成的氧化物再成長。再者，電漿製程及UV製程兩者同時改變了界面層602的上表面，以對後續高介電常數材料層的沉積(ALD或CVD)提供較佳的潤濕特性(例如，-OH或-NHx 官能基604)。另外，由SiON所構成的界面層初始形成(以其他技術)的實際厚度小於或等於5埃()，且可對SiON界面層/Si基底進行上述自由基表面處理，以改善界面層的表面條件，而形成較佳的高介電常數材料層，將於以下說明。
請參照第6C圖，高介電常數材料層606包括氧化鉿(HfO2 )。高介電常數材料層606係藉由ALD製程610而形成於界面層602上。ALD製程610進行一連串步驟而形成高介電常數材料多層膜。每一膜層係藉由在界面層602的上表面提供陽離子前驅物(A)(例如，Hf物質，如TEMAH)而形成，並接著提供陰離子前驅物(B)(例如，O物質，如D2 O)，以與陽離子前驅物反應而形成一層高介電常數材料層606。重複ALD製程610(例如，前驅物A+前驅物B)，以在後續形成每一高介電常數材料層606直到獲得所需的厚度為止。可以理解的是也可使用其他前驅物來形成高介電常數材料層606。
另外，高介電常數材料層606可包括其他介電常數材料，諸如氮氧化鉿(HfON)、鉿矽酸鹽(HfSiO)、氮氧化鉿矽(HfSiON)、氧化鉿鉭(HfTaO)、氮氧化鉿鉭(HfTaON)、氧化鉿鈦(HfTiO)、氮氧化鉿鈦(HfTiON)、氧化鉿鋯(HfZrO)、氮氧化鉿鋯(HfZrON)、氧化鉿鋁(HfAlO)、氮氧化鉿鋁(HfAlON)、氧化鉿鑭(HfLaO)、氮氧化鉿鑭(HfLaON)及其組合。另外，高介電常數材料層可藉由習知金屬有機化學氣相沉積(MOCVD)或其他適當的CVD製程而形成。
請參照第7A至7C圖，其繪示出另一方法以在基底上形成界面層及高介電常數材料層的剖面示意圖。請參照第7A圖，基底700可包括一GaAs基底。基底700可包括不同摻雜型態(例如，N型井區或P型井區)，取決於習知設計需求。基底700亦包括其他單質半導體，例如鍺及鑽石。另外，基底700可包括一化合物半導體及/或一合金半導體。再者，基底700可選擇性地包括一磊晶層(epi layer)，其可具有應變以提高效能，且可包括一絕緣層上覆矽(SOI)的結構。再者，基底700可包括Ge、Ga、As、In、Sb、Al、其組合或是其他適用於半導體裝置的基底。
請參照第7B圖，以電漿製程或紫外線(UV)製程所產生的自由基對GaAs基底700進行處理703，以形成界面層702。上述處理703可以原位的方式(例如，從基底處理至高介電常數材料沉積期間未暴露於大氣中)或非原位(ex situ)的方式(例如，暴露於大氣中)來進行。自由基可包括含硫/氫自由基。基底700可置入一製程反應室，以提供電漿製程或UV製程一適當環境。硫/氫自由基可由使用一氣體所產生，例如H2 S、(NH4 )2 S、NH3 、Ar、He及其組合。在一些實施例中，可使用H2 S/Ar氣體混合物。在其他實施例中，可使用(NH4 )2 S/Ar氣體混合物。在某些其他實施例中，可使用NH3 /H2 S/Ar氣體混合物。在另一些其他實施例中，可使用H2 S/He氣體混合物。界面層702可包括GaSx 及/或AsSx 層，其藉由電漿製程或UV製程及下列的製程條件而形成。
在一實施例中，電漿製程在製程反應室內可具有下列的製程條件。電漿製程的溫度可低於或等於500℃、總壓力在0.005至10Torr的範圍、電漿功率(RF功率)低於或等於200W、H2 S的分壓低於或等於0.1Torr(以惰性氣體稀釋)、NH3 的流量低於或等於500sccm(以惰性氣體稀釋)、Ar的流量在1000至200sccm的範圍及處理時間低於或等於1分鐘。氣體流量參數可用於穩定壓力及反應氣體濃度。另外，可藉由控制暴露期及電漿產生自由基的全部時間來控制上述處理程序。電漿可產生於主製程反應室內或是遠距產生於預備室內且將遠距電漿供至主製程反應室內。再者，可以He取代Ar或混入He，以控制自由基濃度及動量(momentum)。
在另一實施例中，UV製程在製程反應室內可具有下列的製程條件。UV製程的溫度可低於或等於500℃、總壓力在0.005至10Torr的範圍、波長(UV源)小於或等於200nm、H2 S的分壓低於或等於0.1Torr(以Ar氣體稀釋)以產生含水自由基、NH3 的流量低於或等於500sccm(以惰性氣體稀釋)、Ar的流量在1000至200sccm的範圍及”啟用”UV的時間低於或等於1分鐘。氣體流量參數可用於穩定壓力及反應氣體濃度。另外，可藉由控制暴露期及UV產生自由基的全部時間來控制上述處理程序。再者，可以He取代Ar或混入He，以控制自由基濃度及動量。
須注意的是電漿製程及UV製程兩者(例如，總壓力及H2 O的壓力)在低溫()較易促進界面層702的厚度控制及生成較緻密及無缺陷的塊體界面層702。界面層702的等效氧化層厚度(EOT)可小於或等於7埃()。就其而言，可抑制熱引擴散所造成的氧化物再成長。再者，電漿製程及UV製程兩者同時改變了界面層702的上表面，以對後續高介電常數材料層的沉積(ALD或CVD)提供較佳的潤濕特性(例如，烷(-SHx )官能基704)。
請參照第7C圖，高介電常數材料層706包括氧化鉿(HfO2 )。高介電常數材料層706係藉由ALD製程710而形成於界面層702上。ALD製程710進行一連串步驟而形成高介電常數材料多層膜。每一膜層係藉由在界面層702的上表面提供陽離子前驅物(A)(例如，Hf物質，如TEMAH)而形成，並接著提供陰離子前驅物(B)(例如，O物質，如D2 O)，以與陽離子前驅物反應而形成一層高介電常數材料層706。重複ALD製程710(例如，前驅物A+前驅物B)，以在後續形成每一高介電常數材料層706直到獲得所需的厚度為止。可以理解的是也可使用其他前驅物來形成高介電常數材料層706。
另外，高介電常數材料層706可包括其他介電常數材料，諸如氮氧化鉿(HfON)、鉿矽酸鹽(HfSiO)、氮氧化鉿矽(HfSiON)、氧化鉿鉭(HfTaO)、氮氧化鉿鉭(HfTaON)、氧化鉿鈦(HfTiO)、氮氧化鉿鈦(HfTiON)、氧化鉿鋯(HfZrO)、氮氧化鉿鋯(HfZrON)、氧化鉿鋁(HfAlO)、氮氧化鉿鋁(HfAlON)、氧化鉿鑭(HfLaO)、氮氧化鉿鑭(HfLaON)及其組合。另外，高介電常數材料層可藉由習知金屬有機化學氣相沉積(MOCVD)或其他適當的CVD製程而形成。
請參照第8圖，其繪示出在一基底上形成一界面層及一高介電常數材料層的方法800。上述方法800為以雙重處理製程在上表面形成界面層。請參照第9A至9D圖，其繪示出根據第8圖方法800在基底上形成界面層及高介電常數材料層的剖面示意圖。上述方法800始於區塊810。提供一基底900。請參照第9A圖，基底900可包括一矽(Si)基底。基底900可包括不同摻雜型態(例如，N型井區或P型井區)，取決於習知設計需求。基底900亦包括其他單質半導體，例如鍺及鑽石。另外，基底900可包括一化合物半導體及/或一合金半導體。再者，基底900可選擇性地包括一磊晶層(epi layer)，其可具有應變以提高效能，且可包括一絕緣層上覆矽(SOI)的結構。再者，基底900可包括Ge、Ga、As、In、Sb、Al、其組合或是其他適用於半導體裝置的基底。
方法800持續進行到區塊820，在基底900上形成一第一介電層902。請參照第9B圖，以電漿製程或UV製程所產生的自由基對矽基底900進行處理903(第一處理)，以形成第一介電層902。上述處理903可以原位的方式(例如，從基底處理至高介電常數材料沉積期間未暴露於大氣中)或非原位(ex situ)的方式(例如，暴露於大氣中)來進行。自由基可包括含水自由基。含水自由基可由電漿或UV在含O及H原子的環境所產生。舉例來說，含水自由基可由使用一氣體所產生，例如H2 O、H2 O2 、H2 、O2 、N2 、Ar、He或其組合。基底900可置入一製程反應室，以提供電漿製程或UV製程一適當環境。第一介電層902可包括氧化矽(SiOx )，其藉由電漿製程或UV製程及下列的製程條件而形成。
在一實施例中，電漿製程在製程反應室內使用一混合氣體時，例如H2 O/Ar，可具有下列的製程條件。電漿製程的溫度可低於或等於500℃、總壓力在0.005至10Torr的範圍、電漿功率(RF功率)低於或等於200W、H2 O的分壓低於或等於0.1Torr(以惰性氣體稀釋)、Ar的流量在1000至200sccm的範圍及處理時間低於或等於1分鐘。
氣體流量參數可用於穩定壓力及反應氣體濃度。另外，可藉由控制暴露期及電漿產生自由基的全部時間來控制上述處理程序。電漿可產生於主製程反應室內或是遠距產生於預備室內且將遠距電漿供至主製程反應室內。再者，可以He取代Ar或混入He，以控制自由基濃度及動量。
在另一實施例中，UV製程在製程反應室內使用一混合氣體時，例如H2 O/Ar，可具有下列的製程條件。UV製程的溫度可低於或等於500℃、總壓力在0.005至10Torr的範圍、波長(UV源)小於或等於200nm、H2 O的分壓低於或等於0.1Torr(以惰性氣體稀釋)、Ar的流量在1000至200sccm的範圍及”啟用”UV的時間低於或等於1分鐘。
氣體流量參數可用於穩定壓力及反應氣體濃度。另外，可藉由控制暴露期及UV產生自由基的全部時間來控制上述處理程序。再者，可以He取代Ar或混入He，以控制自由基濃度及動量。須注意的是第一處理903之後第一介電層902的上表面具有氫氧(-OH)官能基904。
上述方法800持續進行到區塊830，在第一介電層902上形成第二介電層906。請參照第9C圖，以電漿製程或UV製程所產生的自由基對第一介電層902進行處理908(第二處理)，以形成第二介電層906。上述處理908可以原位的方式(例如，從基底處理至高介電常數材料沉積期間未暴露於大氣中)或非原位(ex situ)的方式(例如，暴露於大氣中)來進行。自由基可包括氮/氫自由基。氮/氫自由基可由電漿或UV在含N及H原子的環境所產生。舉例來說，氮/氫自由基可由使用一氣體所產生，例如NH3 、N2 H2 、N2 H4 、N2 、H2 、NO、N2 O、Ar、He或其組合。基底900可置入一製程反應室，以提供電漿製程或UV製程一適當環境。在本實施例中，第二介電層906可包括氮氧化矽(SiOx Ny )或氮化矽(SiNx )，其藉由電漿製程或UV製程及下列的製程條件而形成。
在一實施例中，電漿製程在製程反應室內使用一混合氣體時，例如NH3 /Ar，可具有下列的製程條件。電漿製程的溫度可低於或等於600℃、總壓力在0.005至10Torr的範圍、電漿功率(RF功率)低於或等於3000W、NH3 的流量低於或等於500sccm、Ar的流量在1000至200sccm的範圍及處理時間低於或等於5分鐘。
氣體流量參數可用於穩定壓力及反應氣體濃度。另外，可藉由控制暴露期及電漿產生自由基的全部時間來控制上述處理程序。電漿可產生於主製程反應室內或是遠距產生於預備室內且將遠距電漿供至主製程反應室內。再者，可以He取代Ar或混入He，以控制自由基濃度及動量。
在另一實施例中，UV製程在製程反應室內使用一混合氣體時，例如NH3 /Ar，可具有下列的製程條件。UV製程的溫度可低於或等於600℃、總壓力在0.005至10Torr的範圍、波長(UV源)小於或等於200nm、NH3 的流量低於或等於500sccm、Ar的流量在1000至200sccm的範圍及”啟用”UV的時間低於或等於5分鐘。
氣體流量參數可用於穩定壓力及反應氣體濃度。另外，可藉由控制暴露期及UV產生自由基的全部時間來控制上述處理程序。再者，可以He取代Ar或混入He，以控制自由基濃度及動量。須注意的是第二處理908之後第二介電層906的上表面具有氨(-NHx )及/或氫氧(-OH)官能基909。
須注意的是不同的氣體組合可用於第一及第二處理903及908。在一實施例中，上述處理包括一氣體混合物，例如H2 O/Ar、H2 O/O2 /Ar、H2 O2 /Ar或H2 /O2 /Ar，藉由調整H及O自由基的活性及濃度以形成SiOx Hy 。上述處理包括一氣體混合物，例如H2 O/N2 /Ar、H2 O2 /N2 /Ar或H2 /O2 //N2 ，藉由調整H、O及N自由基(介電層內N摻雜)的活性及濃度以形成SiOx Ny Hz 。在其他實施例中，上述處理包括一氣體混合物，例如NH3 /Ar、N2 H2 /Ar、N2 H4 /Ar、N2 /H2 /Ar或NH3 /H2 /Ar，藉由調整H、O及N自由基(介電層內N摻雜>3%)的活性及濃度以形成SiOx Ny Hz 。上述處理包括一氣體混合物，例如NO/H2 /Ar、N2 O/H2 /Ar或NH3 /NO/Ar，藉由調整H、O及N自由基的活性及濃度以形成SiOx Ny Hz 。再者，第一及第二處理903及908可為第一電漿+第二電漿、第一UV+第二電漿、第一電漿+第二UV及第一UV+第二UV。
須注意的是電漿製程及UV製程兩者(例如，總壓力及H2 O的壓力)在低溫()較易促進第一介電層902的厚度控制(等效氧化層厚度(EOT)埃())及生成較緻密及無缺陷的塊體界面層。就其而言，可抑制熱引擴散所造成的氧化物再成長。再者，電漿製程及UV製程兩者同時在低溫()改變了界面層的上表面，以對後續高介電常數材料層的沉積(ALD或CVD)提供較佳的潤濕特性(例如，-NHx 或-OH官能基909)。就其而言，第二介電層906的實際厚度小於或等於3埃()，因此第一及第二介電層902及906總EOT小於或等於7埃()。
方法800持續進行到區塊840，在界面層(第一及第二介電層902及906)上形成高介電常數材料層912。第二處理908之後，第二介電層906的上表面具有-OH及/或-NHx 官能基909，以對後續高介電常數材料層的沉積(ALD或CVD)提供較佳的潤濕界面。請參照第9D圖，高介電常數材料層912包括氧化鉿(HfO2 )。高介電常數材料層912係藉由ALD製程914而形成於界面層902及906上。ALD製程914進行一連串步驟而形成高介電常數材料多層膜，如之前所述。每一膜層係藉由在界面層902及906的上表面提供陽離子前驅物(A)(例如，Hf物質，如TEMAH)而形成，並接著提供陰離子前驅物(B)(例如，O物質，如D2 O)，以與陽離子前驅物反應而形成一層高介電常數材料層912。重複ALD製程914(例如，前驅物A+前驅物B)，以在後續形成每一高介電常數材料層912直到獲得所需的厚度為止。可以理解的是也可使用其他前驅物來形成高介電常數材料層912。
另外，高介電常數材料層912可包括其他介電常數材料，諸如氮氧化鉿(HfON)、鉿矽酸鹽(HfSiO)、氮氧化鉿矽(HfSiON)、氧化鉿鉭(HfTaO)、氮氧化鉿鉭(HfTaON)、氧化鉿鈦(HfTiO)、氮氧化鉿鈦(HfTiON)、氧化鉿鋯(HfZrO)、氮氧化鉿鋯(HfZrON)、氧化鉿鋁(HfAlO)、氮氧化鉿鋁(HfAlON)、氧化鉿鑭(HfLaO)、氮氧化鉿鑭(HfLaON)及其組合。另外，高介電常數材料層可藉由習知金屬有機化學氣相沉積(MOCVD)或其他適當的CVD製程而形成。
可以理解的是上述方法400可繼續進行半導體製程，以形成各種不同的微電子裝置，例如積體電路的電晶體、電阻、電容等等。舉例來說，界面層502及高介電常數材料層506可用於形成於基底500內不同的nMOSFET及pMOSFET裝置的閘極介電層。
請參照第10A至10D圖，其繪示出根據第8圖方法800的另一實施例而在基底上形成界面層及高介電常數材料層的剖面示意圖。第10圖的實施例同樣在一基底上進行雙重處理製程以及沉積高介電常數材料層。因此，除了以下所述的差異之外，第10圖的半導體裝置相似於第9圖的半導體裝置。請參照第10A圖，一基底1000可包括一矽(Si)基底。基底1000可包括不同摻雜型態(例如，N型井區或P型井區)，取決於習知設計需求。基底1000亦包括其他單質半導體，例如鍺及鑽石。另外，基底1000可包括一化合物半導體及/或一合金半導體。再者，基底1000可選擇性地包括一磊晶層(epi layer)，其可具有應變以提高效能，且可包括一絕緣層上覆矽(SOI)的結構。再者，基底1000可包括Ge、Ga、As、In、Sb、Al、其組合或是其他適用於半導體裝置的基底。
請參照第10B圖，一介電層1002係藉由電漿製程或UV製程所產生的自由基對矽基底1000進行處理1003(第一處理)而形成。上述處理1003可以原位的方式(例如，從基底處理至高介電常數材料沉積期間未暴露於大氣中)或非原位(ex situ)的方式(例如，暴露於大氣中)來進行。在本實施例中，自由基可包括氮/氫自由基。氮/氫自由基可由電漿或UV在含N及H原子的環境所產生。舉例來說，氮/氫自由基可由使用一氣體所產生，例如NH3 、N2 H2 、N2 H4 、N2 、H2 、NO、N2 O、Ar、He或其組合。基底1000可置入一製程反應室，以提供電漿製程或UV製程一適當環境。在本實施例中，第介電層1002可藉由電漿製程或UV製程及下列的製程條件而形成。
在一實施例中，電漿製程在製程反應室內使用一混合氣體時，例如NH3 /Ar，可具有下列的製程條件。電漿製程的溫度可低於或等於600℃、總壓力在0.005至10Torr的範圍、電漿功率(RF功率)低於或等於3000W、NH3 的流量低於或等於500sccm、Ar的流量在1000至200sccm的範圍及處理時間低於或等於5分鐘。
氣體流量參數可用於穩定壓力及反應氣體濃度。另外，可藉由控制暴露期及電漿產生自由基的全部時間來控制上述處理程序。電漿可產生於主製程反應室內或是遠距產生於預備室內且將遠距電漿供至主製程反應室內。再者，可以He取代Ar或混入He，以控制自由基濃度及動量。
在另一實施例中，UV製程在製程反應室內使用一混合氣體時，例如NH3 /Ar，可具有下列的製程條件。UV製程的溫度可低於或等於600℃、總壓力在0.005至10Torr的範圍、波長(UV源)小於或等於200nm、NH3 的流量低於或等於500sccm、Ar的流量在1000至200sccm的範圍及”啟用”UV的時間低於或等於5分鐘。
氣體流量參數可用於穩定壓力及反應氣體濃度。另外，可藉由控制暴露期及UV產生自由基的全部時間來控制上述處理程序。再者，可以He取代Ar或混入He，以控制自由基濃度及動量。
在本實施例中，介電層1002可包括一氮化矽(SiNx )，其上表面具有氨(-NHx )官能基1004。在一些實施例中，介電層1002可包括一氮氧化矽(SiOx Ny )，其上表面具有氨(-NHx )官能基。介電層1002一開始形成部分的界面層。
請參照第10C圖，對分別含有SiNx 及Si再氧化的介電層1002進行處理1008，以形成介電層1006。再氧化製程可在氧化環境下進行熱退火。在本實施例中，藉由電漿製程或UV製程所產生的自由基對介電層1002的上表面及其與矽基底1000的界面進行處理1008。因此，介電層1006形成於矽基底1000上，而一介電層1002a形成於介電層1006上。上述處理1008可以原位的方式(例如，未暴露於大氣中)或非原位(ex situ)的方式(例如，從基底處理至高介電常數材料沉積期間暴露於大氣中)來進行。在本實施例中，自由基可包括含水自由基。含水自由基可由電漿或UV在含O及H原子的環境所產生。舉例來說，含水自由基可由使用一氣體所產生，例如H2 O、H2 O2 、H2 、O2 、N2 、Ar、He或其組合。基底1000可置入一製程反應室，以提供電漿製程或UV製程一適當環境。介電層1006可藉由下列的製程條件而形成。
在一實施例中，電漿製程在製程反應室內使用一混合氣體時，例如H2 O/Ar，可具有下列的製程條件。電漿製程的溫度可低於或等於500℃、總壓力在0.005至10Torr的範圍、電漿功率(RF功率)低於或等於200W、H2 O的分壓低於或等於0.1Torr(以惰性氣體稀釋)、Ar的流量在1000至200sccm的範圍及處理時間低於或等於1分鐘。
氣體流量參數可用於穩定壓力及反應氣體濃度。另外，可藉由控制暴露期及電漿產生自由基的全部時間來控制上述處理程序。電漿可產生於主製程反應室內或是遠距產生於預備室內且將遠距電漿供至主製程反應室內。再者，可以He取代Ar或混入He，以控制自由基濃度及動量。
在另一實施例中，UV製程在製程反應室內使用一混合氣體時，例如H2 O/Ar，可具有下列的製程條件。UV製程的溫度可低於或等於500℃、總壓力在0.005至10Torr的範圍、波長(UV源)小於或等於200nm、H2 O的分壓低於或等於0.1Torr(以惰性氣體稀釋)、Ar的流量在1000至200sccm的範圍及”啟用”UV的時間低於或等於1分鐘。
氣體流量參數可用於穩定壓力及反應氣體濃度。另外，可藉由控制暴露期及UV產生自由基的全部時間來控制上述處理程序。再者，可以He取代Ar或混入He，以控制自由基濃度及動量。
在本實施例中，經過電漿或UC製程之後，介電層1006可包括氧化矽(SiOx )，而介電層1002a可包括氮氧化矽(SiOx Ny )。在其他實施例中，介電層1006可包括氧化矽氮氧化矽(SiOx Ny )。介電層1002a及1006係構成界面層。
須注意的是不同的氣體組合可用於第一及第二處理1003及1008。在一實施例中，上述處理包括一氣體混合物，例如H2 O/Ar、H2 O/O2 /Ar、H2 O2 /Ar或H2 /O2 /Ar，藉由調整H及O自由基的活性及濃度以形成SiOx Hy 。上述處理包括一氣體混合物，例如H2 O/N2 /Ar、H2 O2 /N2 /Ar或H2 /O2 //N2 ，藉由調整H、O及N自由基(介電層內N摻雜)的活性及濃度以形成SiOx Ny Hz 。在其他實施例中，上述處理包括一氣體混合物，例如NH3 /Ar、N2 H2 /Ar、N2 H4 /Ar、N2 /H2 /Ar或NH3 /H2 /Ar，藉由調整H、O及N自由基(介電層內N摻雜>3%)的活性及濃度以形成SiOx Ny Hz 。上述處理包括一氣體混合物，例如NO/H2 /Ar、N2 O/H2 /Ar或NH3 /NO/Ar，藉由調整H、O及N自由基的活性及濃度以形成SiOx Ny Hz 。再者，第一及第二處理1003及1008可為第一電漿+第二電漿、第一UV+第二電漿、第一電漿+第二UV及第一UV+第二UV。
須注意的是電漿製程及UV製程兩者(例如，總壓力及H2 O的壓力)在低溫()較易促進介電層1006的厚度控制(等效氧化層厚度(EOT)埃())及生成較緻密及無缺陷的塊體界面層。就其而言，可抑制熱引擴散所造成的氧化物再成長。再者，電漿製程及UV製程兩者同時在低溫()改變了界面層的上表面，以對後續高介電常數材料層的沉積(ALD或CVD)提供較佳的潤濕特性(例如，(-OH)或(-NHx )官能基1009)。就其而言，介電層1002a的實際厚度小於或等於3埃()，因此介電層1002a及1006總EOT小於或等於7埃()。
第二處理1008之後，介電層1002a的上表面具有(-OH)及/或(-NHx )官能基1009，以對後續高介電常數材料層的沉積(ALD或CVD)提供較佳的潤濕界面。請參照第10D圖，高介電常數材料層1012包括氧化鉿(HfO2 )。高介電常數材料層1012係藉由ALD製程1014而形成於界面層(介電層1002a及1006)上。ALD製程1014進行一連串步驟而形成高介電常數材料多層膜，如之前第9圖所述。每一膜層係藉由在界面層(介電層1002a及1006)的上表面提供陽離子前驅物(A)(例如，Hf物質，如TEMAH)而形成，並接著提供陰離子前驅物(B)(例如，O物質，如D2 O)，以與陽離子前驅物反應而形成一層高介電常數材料層1012。重複ALD製程1014(例如，前驅物A+前驅物B)，以在後續形成每一高介電常數材料層1012直到獲得所需的厚度為止。可以理解的是也可使用其他前驅物來形成高介電常數材料層1012。
另外，高介電常數材料層1012可包括其他介電常數材料，諸如氮氧化鉿(HfON)、鉿矽酸鹽(HfSiO)、氮氧化鉿矽(HfSiON)、氧化鉿鉭(HfTaO)、氮氧化鉿鉭(HfTaON)、氧化鉿鈦(HfTiO)、氮氧化鉿鈦(HfTiON)、氧化鉿鋯(HfZrO)、氮氧化鉿鋯(HfZrON)、氧化鉿鋁(HfAlO)、氮氧化鉿鋁(HfAlON)、氧化鉿鑭(HfLaO)、氮氧化鉿鑭(HfLaON)及其組合。另外，高介電常數材料層可藉由習知金屬有機化學氣相沉積(MOCVD)或其他適當的CVD製程而形成。
可以理解的是上述基底900及1000可繼續進行半導體製程，以形成各種不同的微電子裝置，例如積體電路的電晶體、電阻、電容等等。舉例來說，界面層(介電層902及906及介電層1002a及1006)及高介電常數材料層912及1012可用於不同的nFET及pFET裝置的閘極介電層。舉例來說，可在高介電常數材料層上形成一金屬層。金屬層包括N功函數(work function)金屬(N-金屬)或P功函數(P-金屬)。金屬層可藉由各種沉積技術而形成，例如物理氣相沉積(physical vapor deposition,PVD)或濺鍍、CVD、ALD、電鍍或其他適當的技術。一多晶矽(poly)層可藉由CVD或其他適當的技術而形成於金屬層上。一硬式罩幕(hard mask)層可行成於多晶矽層上。上述各個層可圖案化而形成習知閘極結構。
本發明不同實施例具有不同的優點。舉例來說，以上敘述的方法在低溫下提供一緻密且表面改變的界面層。因此，一些優點包括：(1)基底(通道)/界面層界面鈍化；(2)因高介電常數前驅物而改變界面層表面(較接的潤濕界面)；(3)在高介電常數材料沉積之後，界面層/高介電常數材料的界面鈍化；(4)界面處的大氣污染源少；(5)抑制熱引擴散；(6)閘極介電層的EOT小於10埃。因此，閘極介電層的EOT符合先盡的技術要求(例如，45nm以下)。因此，上述方法相容於現行CMOS製程技術，而可輕易整合至現行的製程設備及裝置技術。可以理解的是不同實施例提供不同的優點，而對於所有實施例而言，沒有特定的優點是不可或缺的。
以上敘述許多實施例的特徵，使所屬技術領域中具有通常知識者能夠清楚理解以下的說明。所屬技術領域中具有通常知識者能夠理解其可利用本發明揭示內容為基礎以設計或更動其他製程及結構而完成相同於上述實施例的目的及/或達到相同於上述實施例的優點。所屬技術領域中具有通常知識者亦能夠理解不脫離本發明之精神和範圍的等效構造可在不脫離本發明之精神和範圍內作任意之更動、替代與潤飾。舉例來說，上述實施例的界面層及高介電常數材料層可用於前閘極(gate first)製程、後閘極(gate last)製程以及包括前閘極製程及後閘極製程的混合製程，以形成具有高介電常數閘極介電層及金屬閘極配置的裝置。
100、200、300、500、600、700、900、1000．．．基底
102、202、302、502、602、702．．．界面層
104、206、306、506、606、706、912、1012．．．高介電常數材料層
110、210、310、510、610、710、914、1014．．．原子層沉積(ALD)~製程
112．．．缺陷
204、504、904．．．氫氧(-OH)官能基
212．．．過量氫氧官能基
214、312．．．電子陷阱
304．．．上表面
400、800．．．方法
410、420、430、810、820、830、840．．．區塊
503．．．電漿製程
603、703、903、908、1003、1008．．．處理
604、909．．．官能基
704．．．烷(-SHx )官能基
902．．．第一介電層
906．．．第二介電層
1002、1002a、1006．．．介電層
1004．．．氨(-NHx )官能基
1009．．．(-OH)及/或(-NHx )官能基
AMC．．．大氣污染源
第1圖係繪示出在半導體基底上形成界面層及高介電常數材料層的方法示意圖。
第2圖係繪示出在半導體基底上形成界面層及高介電常數材料層的另一方法示意圖。
第3圖係繪示出在半導體基底上形成界面層及高介電常數材料層的另一方法示意圖。
第4圖係繪示出根據本發明各個實施例之在半導體基底上形成界面層及高介電常數材料層的方法流程圖。
第5A至5C圖係繪示出根據第4圖方法來形成界面層及高介電常數材料層的剖面示意圖。
第6A至6C圖係繪示出另一方法來形成界面層及高介電常數材料層的剖面示意圖。
第7A至7C圖係繪示出又另一方法來形成界面層及高介電常數材料層的剖面示意圖。
第8圖係繪示出根據本發明各個實施例之在半導體基底上形成界面層及高介電常數材料層的另一方法流程圖。
第9A至9D圖係繪示出根據第8圖方法來形成界面層及高介電常數材料層的剖面示意圖。
第10A至10D圖係繪示出根據本發明各個實施例之以雙重處理製程形成界面層，且在半導體基底上沉積高介電常數材料層。
400．．．方法
410、420、430．．．區塊

Claims (5)

  1. 一種半導體裝置的製造方法，包括：提供一基底；對該基底進行一第一處理，以在該基底上形成一第一介電層，該第一處理包括第一自由基；對該第一介電層進行一第二處理，以在該基底上形成一第二介電層，該第二處理包括不同於該第一自由基的第二自由基，其中每一第一及第二自由基包括含水自由基及含氮及/或氫自由基的其中一個；以及在該第一及第二介電層上形成一高介電常數材料層。
  2. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中該第一及該第二自由基的其中一個由一氣體所產生，其擇自於以下群族：NH3 、N2 H2 、N2 H4 、N2 、NO、N2 O、H2 O、H2 O2 、H2 、O2 、Ar、He及其組合。
  3. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中每一第一及第二處理包括電漿製程及紫外線製程的其中一個。
  4. 如申請專利範圍第3項所述之半導體裝置的製造方法，其中該電漿製程條件包括以下其中一個：使用一H2 O/Ar混合氣體，且H2 O的分壓低於0.1Torr、Ar的流量在1000至200 sccm的範圍、溫度低於500℃、總壓力在0.005至10 Torr的範圍、電漿功率低於200 W及時間低於1分鐘；以及使用一NH3 /Ar混合氣體，且NH3 的流量低於500 sccm、Ar的流量在1000至200 sccm的範圍、溫度低於600℃、總壓力在0.005至10 Torr的範圍、電漿功率低於3 kW及時間低於5分鐘。
  5. 如申請專利範圍第3項所述之半導體裝置的製造方法，其中該紫外線製程條件包括以下其中一個：使用一H2 O/Ar混合氣體，且H2 O的分壓低於0.1 Torr、Ar的流量在1000至200 sccm的範圍、溫度低於500℃、總壓力在0.005至10 Torr的範圍、波長低於200nm及時間低於1分鐘；以及使用一NH3 /Ar混合氣體，且NH3 的流量低於500 sccm、Ar的流量在1000至200 sccm的範圍、溫度低於600℃、總壓力在0.005至10 Torr的範圍、波長低於200nm及時間低於5分鐘。
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