TWI635539B - 高介電常數介電層、其製造方法及執行該方法之多功能設備 - Google Patents

高介電常數介電層、其製造方法及執行該方法之多功能設備 Download PDF

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TWI635539B
TWI635539B TW106131698A TW106131698A TWI635539B TW I635539 B TWI635539 B TW I635539B TW 106131698 A TW106131698 A TW 106131698A TW 106131698 A TW106131698 A TW 106131698A TW I635539 B TWI635539 B TW I635539B
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layer
reaction chamber
plasma
bias
dielectric layer
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TW106131698A
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English (en)
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TW201916167A (zh
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陳敏璋
鍾鎮陽
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金巨達國際股份有限公司
陳敏璋
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Priority to TW106131698A priority Critical patent/TWI635539B/zh
Priority to CN201810920927.5A priority patent/CN109509788B/zh
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Publication of TWI635539B publication Critical patent/TWI635539B/zh
Priority to US16/131,249 priority patent/US10923343B2/en
Publication of TW201916167A publication Critical patent/TW201916167A/zh
Priority to US17/141,935 priority patent/US11322348B2/en

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    • H—ELECTRICITY
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    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
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Abstract

本發明揭露一種高介電常數介電層、其製造方法及執行該方法之多功能設備。本發明之高介電常數介電層包含依序形成於半導體元件之一材料層上之M層原子層沉積薄膜，其中M係大於1的整數。該材料層可以是半導體材料層、金屬層或另一介電層。每一層原子層沉積薄膜係由氧化物且藉由原子層沈積製程所形成。M層原子層沉積薄膜中之N層選定的薄膜，於原子層沈積製程期間或之後，經非反應性氣體電漿轟擊，其中N係自然數且小於或等於M。

Description

高介電常數介電層、其製造方法及執行該方法之多功能設備
本發明係關於一種高介電常數介電層、其製造方法及執行該方法之多功能設備，並且特別地，本發明是關於一種具有低漏電流密度之高介電常數介電層、其製造方法及執行該方法之多功能設備。
為了滿足半導體元件在尺寸的縮小以及降低閘極漏電流上的要求，許多具有高介電常數的閘極介電材料已被提出來替代傳統的介電層。以矽基半導體元件為例，Al2O3、HfO2、ZrO2、TiO2、Y2O3與La2O3等，已被提出來代替傳統的SiO2閘極介電層。
然而，介電層本身的薄膜品質與缺陷密度對閘極漏電流的影響甚大。目前，對於製造具有優良的薄膜品質與低缺陷密度之介電層的製程，以及製程中或製程後處理的研究，仍有相當大的空間。
因此，本發明所欲解決之一技術問題在於提供一種具有優良薄膜品質與低缺陷密度，進而具有低漏電流密度之高介電常數介電層，以及其製造方法及執行該方法之多功能設備。並且，根據本發明之高介電常數介電層具有優良的可靠度。
根據本發明之一較佳具體實施例之高介電常數介電層，係形成於半導體元件內。根據本發明之高介電常數介電層包含M層原子層沉積薄膜，其中M係大於1的整數。M層原子層沉積薄膜係依序形成於半導體元件之一材料層上。該材料層可以是半導體材料層、金屬層或另一介電層。每一層原子層沉積薄膜係由氧化物且藉由原子層沈積製程(atomic layer deposition process,ALD process)所形成。在製備M層原子層沉積薄膜的過程當中，本發明針對M層原子層沉積薄膜中之N層選定的薄膜，於原子層沈積製程期間或之後，執行非反應性氣體電漿轟擊，以對此N層選定的薄膜產生退火的效果，以降低此N層選定的薄膜之缺陷密度，其中N係自然數且小於或等於M。
於一具體實施例中，根據本發明之高介電常數介電層具有較低之漏電流密度，在電容等效厚度(capacitance equivalent thickness,CET)小於2nm時，漏電流密度小於1×10-4A/cm2。並且，根據本發明之高介電常數介電層具有厚度範圍從1nm至50nm。
根據本發明之一較佳具體實施例之製造高介電常數介電層於半導體元件內之方法。首先，係藉由原子層沉積製程，依序形成氧化物之M層原子層沉積薄膜於半導體元件之一材料層上，其中M係大於1的整數。該材料層可以是半導體材料層、金屬層或另一介電層。在製備M層原子層沉積薄膜的過程當中，根據本發明之方法，針對M層原子層沉積薄膜中之N層選定的薄膜，執行非反應性氣體電漿轟擊，以對此N層選定的薄膜產生退火的效果，以降低此N層選定的薄膜之缺陷密度，即完成高介電常數介電層，其中N係自然數且小於或等於M。
於一具體實施例中，氧化物可以是HfO2、ZrO2、Al2O3、La2O3、SiO2、TiO2與Y2O3等。
於一具體實施中，用以產生非反應性氣體電漿之惰性氣體可以是Ar、He、Ne、He/Ar、He/N2與He/Ne等。
根據本發明之一較佳具體實施例之執行根據本發明之方法的多功能設備，包含反應腔體、電漿源、電漿源功率產生單元、偏壓電極、交流偏壓產生單元、直流偏壓產生單元、金屬夾盤、第一先驅物(precursor)供應源、第二先驅物供應源、載送氣體(carrier gas)供應源、氧氣供應源、惰性氣體供應源、自動壓力控制器以及抽氣泵。電漿源係設置於反應腔體內之頂部。電漿源功率產生單元係電連接至電漿源，並且被控制輸出交流功率至電漿源。偏壓電極係設置於反應腔體內之底部。交流偏壓產生單元係電連接至偏壓電極，並且被控制選擇性地輸出交流偏壓或直流電偏壓重疊交流偏壓至偏壓電極，以控制該非反應性氣體電漿轟擊的能量。直流偏壓產生單元係電連接至偏壓電極，並且被控制選擇性地輸出正直流電偏壓或負直流電偏壓至偏壓電極，以控制非反應性氣體電漿轟擊的能量。金屬夾盤係設置於偏壓電極上，並且用以夾持半導體元件之半成品。第一先驅物供應源係經由第一控制閥連通至反應腔體，並且被控制供應形成氧化物之第一先驅物至反應腔體內。第二先驅物供應源係經由第二控制閥連通至反應腔體，並且被控制供應形成氧化物之第二先驅物至反應腔體內。載送氣體供應源係經由第一流量控制器連通至反應腔體，並且被控制供應載送氣體至反應腔體內。氧氣供應源係經由第二流量控制器連通至反應腔體之頂部。氧氣供應源被控制供應氧氣，由電漿源之交流功率游離成氧氣電漿。惰性氣體供應源係經由第三流量控制器連通至反應腔體之頂部。惰性氣體供應源被控制供應惰性氣體，由電漿源之交流功率游離成非反應性氣體電漿。抽氣泵經由自動壓力控制器連通至反應腔體之底部，並且由自動壓力控制器控制對反應腔體進行抽氣。
與先前技術不同，本發明之高介電常數介電層具有優良薄膜品質與低缺陷密度，並且具有低漏電流密度。
關於本發明之優點與精神可以藉由以下的發明詳述及所附圖式得到進一步的瞭解。
1‧‧‧高介電常數介電層
10‧‧‧原子層沉積薄膜
11‧‧‧未經非反應性氣體電漿轟擊的原子層沉積薄膜
12‧‧‧選定的薄膜
2‧‧‧半導體元件
3‧‧‧多功能設備
30‧‧‧反應腔體
302‧‧‧頂部
304‧‧‧底部
31‧‧‧電漿源
32‧‧‧電漿源功率產生單元
33‧‧‧偏壓電極
34‧‧‧交流偏壓產生單元
35‧‧‧直流偏壓產生單元
36‧‧‧金屬夾盤
37‧‧‧第一先驅物供應源
372‧‧‧第一控制閥
38‧‧‧第二先驅物供應源
382‧‧‧第二控制閥
39‧‧‧氧氣供應源
392‧‧‧第二流量控制器
40‧‧‧惰性氣體供應源
402‧‧‧第三流量控制器
41‧‧‧自動壓力控制器
42‧‧‧抽氣泵
44‧‧‧載送氣體供應源
442‧‧‧第一流量控制器
圖1係根據本發明之一較佳具體實施例之高介電常數介電層的截面視圖。
圖2係根據本發明之一較佳具體實施例之高介電常數介電層之一變形的截面視圖。
圖3係根據本發明之一較佳具體實施例之高介電常數介電層之另一變形的截面視圖。
圖4係執行根據本發明之方法的多功能設備之架構示意圖。
圖5係本發明製作DHe試片、THe試片及Hf0試片的ALD循環流程示意圖。
圖6係經PMA處理的DHe試片、THe試片及Hf0試片經XPS量測所得之能譜。
圖7係經PMA處理的DHe試片、THe試片及Hf0試片的HRTEM照片。
圖8係經PMA處理的DHe試片、THe試片及Hf0試片經定電壓應力(constant voltage stress,CVS)測試的結果。
請參閱圖1、圖2及圖3，該等圖式係以截面視圖示意地繪示根據本發明之一較佳具體實施例之高介電常數介電層1。
如圖1、圖2及圖3所示，根據本發明之較佳具體實施例之高介電常數介電層1係形成於半導體元件2內。高介電常數介電層1係形成於半導體元件之一材料層上。該材料層可以是半導體材料層、金屬層或另一介電層。
於一具體實施中，半導體材料層可以由Si、Ge、SiGe、GeSn、絕緣層覆矽、III-V族化合物、II-VI族化合物與IV-VI族化合物等半導體材料所形成。金屬材料層可以由鉑、鉭、鈦、鎢、銅、鋁、鋁矽銅合金、鋁銅合金、氮化鈦、氮化鉭、重摻雜多晶矽等金屬材料所形成。
同樣示於圖1、圖2及圖3，根據本發明之高介電常數介電層1包含M層原子層沉積薄膜10，其中M係大於1的整數。M層原子層沉積薄膜10係依序形成於半導體元件2之一材料層上。該材料層可以是半導體材料層、金屬層或另一介電層。每一層原子層沉積薄膜10係為氧化物且藉由原子層沈積製程所形成。
原子層沉積製程具有以下優點：(1)可在原子等級控制材料的形成；(2)可更精準地控制薄膜的厚度；(3)可大面積量產；(4)有優異的均勻度(uniformity)；(5)有優異的三維包覆性(conformality)；(6)無孔洞結構；(7)缺陷密度低；以及(8)沉積溫度較低…等製程優點。本發明所採用的原子層沈積製程可以形成原子層沉積薄膜10。
於一具體實施例中，氧化物可以是HfO2、ZrO2、Al2O3、La2O3、SiO2、TiO2與Y2O3等。
特別地，針對M層原子層沉積薄膜10中之N層選定的薄膜12，於原子層沈積製程期間或之後，執行非反應 性氣體電漿轟擊，以對此N層選定的薄膜12，產生退火的效果，以降低此N層選定的薄膜12之缺陷密度，其中N係自然數且小於或等於M。於圖1中，符號”11”代表僅使用原子層沈積製程所形成的氧化物薄膜，未經非反應性氣體電漿轟擊。符號”12”代表使用原子層沈積製程期間或之後，並經非反應性氣體電漿轟擊，所形成的氧化物薄膜。
於圖1所示案例，N層選定的薄膜12的層數，佔所有薄膜層數的半數，且集中在本發明之高介電常數介電層1的下半部。
於圖2所示案例，N層選定的薄膜12的層數，佔所有薄膜層數的半數，且集中在本發明之高介電常數介電層1的上半部。
於圖3所示案例，選定的薄膜12與未經非反應性氣體電漿轟擊的原子層沉積薄膜11，穿插堆疊以形成本發明之高介電常數介電層1。但本發明之高介電常數介電層1並不以圖1、圖2及圖3所示未經非反應性氣體電漿轟擊的原子層沉積薄膜11與選定的薄膜12之間的排列關係為限，本發明之高介電常數介電層1也可以形成數層未經非反應性氣體電漿轟擊的原子層沉積薄膜11，再形成一層選定的薄膜12。
於一具體實施中，用以產生非反應性氣體電漿之惰性氣體可以是Ar、He、Ne、He/Ar、He/N2與He/Ne等。
一般在電漿製程中，Ar被廣泛用作為電漿源的工作氣體。另一方面，He在氣相沉積的過程中通常用作為緩衝氣體，其作為不可燃性氣體來控制工作壓力。與Ar電漿相比，由於He的半徑較小導致He具有較高的電離能，因此He電漿具有較高的能量。此外，由於He的質量較小，因此He電漿所引起的損傷低於Ar電漿所引起的損傷。因此，採用 He電漿等非反應性氣體電漿轟擊選定的薄膜12，藉由電漿轟擊將能量傳導至薄膜表面，進而導致退火效應。選定的薄膜12表面溫度的升高會增強吸附於表面的原子(adatoms)之運動和遷移，這有利於選定的薄膜12其薄膜品質的改善並且降低缺陷密度。由溫度升高引起的另一個效應，是有利於去除吸附於表面的先驅物的配體(ligands)。
藉此，根據本發明之高介電常數介電層1具有較低之漏電流密度，在其電容等效厚度(CET)小於2nm時，其漏電流密度小於1×10-4A/cm2。並且本發明之高介電常數介電層1應用於半導體元件內，其厚度範圍從1nm至50nm，可以取代傳統的超薄SiO2薄膜。
根據本發明之一較佳具體實施例之製造如圖1、圖2或圖3所示高介電常數介電層1於半導體元件2內之方法，首先，係藉由原子層沉積製程，依序形成氧化物之M層原子層沉積薄膜10於半導體元件2之一材料層上，其中M係大於1的整數。該材料層可以是半導體材料層、金屬層或另一介電層。
根據本發明之方法，針對M層原子層沉積薄膜10中之N層選定的薄膜12，執行非反應性氣體電漿轟擊，以對此N層選定的薄膜12產生退火的效果，以降低此N層選定的薄膜12之缺陷密度，即完成高介電常數介電層1，其中N係自然數且小於或等於M。本發明之高介電常數介電層1，其未經非反應性氣體電漿轟擊的原子層沉積薄膜11與選定的薄膜12之間的排列關係，已於上文中詳述，在此不再贅述。
形成半導體材料層的材料以及用以產生非反應性氣體電漿之惰性氣體，已於上文中詳述，在此不再贅述。
於一具體實施中，氧化物係HfO2。供應Hf元素的先驅物可以是HfCl4、HfI4、HfCl2[N(SiMe3)2]2、HfCp2Me2、HfCp2Cl2、 Hf(CpMe)2Me2、Hf(CpMe)2(OMe)Me、Hf(CpMe)2(OiPr)Me、Hf(CpMe)2(mmp)Me、Hf(Cp)(NMe2)3、Hf(CpMe)(NMe2)3、Hf(Cp2CMe2)Me2、Hf(Cp2CMe2)Me(OMe)、Hf(OiPr)4、Hf(OtBu)4、Hf(OtBu)2(mmp)2、Hf(OtBu)(NEtMe)3、Hf(mmp)4、Hf(mp)4、Hf(ONEt2)4、Hf(NMe2)4、Hf(NEt2)4、Hf(NEtMe)4、Hf[N(SiMe3)2]2Cl2、Hf(NO3)4。供應O元素的先驅物可以是O2電漿、N2O電漿、O3、H2O、H2O2。
於另一具體實施中，氧化物係ZrO2。供應Zr元素的先驅物可以是ZrCl4、ZrI4、ZrCp2Cl2、ZrCp2Me2、ZrCp2Me(OMe)、ZrCp(NMe2)3、Zr(CpMe)2Me2、Zr(CpMe)2Me(OMe)、Zr(CpMe)(NMe2)3、Zr(CpEt)(NMe2)3、Zr(Cp2CMe2)Me2、Zr(Cp2CMe2)Me(OMe)、Zr(OiPr)4、Zr(OiPr)2(dmae)2、Zr(OtBu)4、Zr(OtBu)2(dmae)2、Zr(dmae)4、Zr(thd)4、Zr(NMe2)4、Zr(NEt2)4、Zr(NEtMe)4、Zr[N(SiMe3)2]2Cl2、Zr(MeAMD)4。供應O元素的先驅物可以是O2電漿、N2O電漿、O3、H2O、H2O2。
於另一具體實施中，氧化物係Al2O3。供應Al元素的先驅物可以是AlCl3、AlBr3、AlMe3、AlMe2Cl、AlMe2OiPr、AlEt3、Al(OEt)3、Al(OnPr)3、Al(mmp)3、Al(NEt2)3、Al(NiPr2)3、Al(iPrAMD)Et2。供應O元素的先驅物可以是O2電漿、N2O電漿、O3、H2O、H2O2。
於另一具體實施中，氧化物係TiO2。供應Ti元素的先驅物可以是TiF4、TiCl4、TiI4、Ti(CpMe5)(OMe)3、Ti(CpMe)(OiPr)3、Ti(OMe)4、Ti(OEt)4、Ti(OiPr)4、Ti(OiPr)2(dmae)2、Ti(OiPr)2(thd)2、Ti(trhd)2(O(CMe2Et)2、Ti(OBu)4、Ti(NMe2)4、TiCp2((iPrN)2C(NHiPr))。供應O元素的先驅物可以是O2電漿、N2O電漿、O3、H2O、H2O2。
於另一具體實施中，氧化物係La2O3。供應La元素的先驅物可以是La(thd)3、La[N(SiMe3)2]3、La(iPrAMD)3、La(iPrfAMD)3、La(Cp)3、La(CpEt)3、La(CpiPr)3。供應O元素的先驅 物可以是O2電漿、N2O電漿、O3、H2O、H2O2。
於另一具體實施中，氧化物係SiO2。供應Si元素的先驅物可以是SiCl4、Si2Cl6、SiCl3H、SiCl2H2、SiH4、Si(OMe)4、Si(OEt)4、Si(OEt)3((CH2)3NH2)、Si(OtPe)3OH、HMDS、SiH2(N(CH3)2)2、SiH2(NHtBu)2、SiH2(NEt2)2、SiH(N(CH3)2)3、Si(NCO)4、MeOSi(NCO)3。。供應O元素的先驅物可以是O2電漿、N2O電漿、O3、H2O、H2O2。
於另一具體實施中，氧化物係Y2O3。供應Y元素的先驅物可以是Y(thd)3、YCp3、Y(CpMe)3、Y(CpEt)3、Y(iPrAMD)3。供應O元素的先驅物可以是O2電漿、N2O電漿、O3、H2O、H2O2。
於一具體實施例中，非反應性氣體電漿之流量範圍從1sccm至1000sccm。
於一具體實施例中，非反應性氣體電漿之工作壓力範圍從100~10-3torr.。
請參閱圖4，圖4係以示意圖繪示執行根據本發明之方法的多功能設備3的架構。
如圖4所示，根據本發明之多功能設備3包含反應腔體30、電漿源31、電漿源功率產生單元32、偏壓電極33、交流偏壓產生單元34、直流偏壓產生單元35、金屬夾盤36、第一先驅物供應源37、第二先驅物供應源38、載送氣體供應源44、氧氣供應源39、惰性氣體供應源40、自動壓力控制器41以及抽氣泵42。
電漿源31係設置於反應腔體30內之頂部302。電漿源功率產生單元32係電連接至電漿源31，並且被控制輸出交流功率至電漿源31。偏壓電極33係設置於反應腔體30內之底部304。交流偏壓產生單元34係電連接至偏壓電極33， 並且被控制選擇性地輸出交流偏壓或直流電偏壓重疊交流偏壓至偏壓電極33，以控制非反應性氣體電漿轟擊的能量。於一具體實施例中，交流偏壓產生單元34被控制選擇性地輸出交流偏壓或直流電偏壓重疊交流偏壓。
直流偏壓產生單元35係電連接至偏壓電極33，並且被控制選擇性地輸出正直流電偏壓或負直流電偏壓至偏壓電極33，以控制非反應性氣體電漿轟擊的能量。於一具體實施例中，直流偏壓產生單元35被控制選擇性地輸出正直流電偏壓或負直流電偏壓。
金屬夾盤36係設置於偏壓電極33上，並且用以夾持半導體元件2之半成品。
第一先驅物供應源37係經由第一控制閥372連通至該反應腔體30，並且被控制供應形成氧化物之第一先驅物至反應腔體30內。第二先驅物供應源38係經由第二控制閥382連通至反應腔體30，並且被控制供應形成氧化物之第二先驅物至反應腔體30內。
載送氣體供應源44係經由第一流量控制器442連通至反應腔體30，並且被控制供應載送氣體至反應腔體30內。
氧氣供應源39係經由第二流量控制器392連通至反應腔體30之頂部302。氧氣供應源39被控制供應氧氣，由電漿源之交流功率游離成氧氣電漿。惰性氣體供應源40係經由第三流量控制器402連通至反應腔體30之頂部302。惰性氣體供應源40被控制供應惰性氣體，由電漿源之交流功率游離成非反應性氣體電漿。抽氣泵42經由自動壓力控制器41連通至反應腔體30之底部304，並且經由自動壓力控制器41進行抽氣速率的自動調控，以達理想的製程壓力。
須強調的是，根據本發明之多功能設備3可以在 原地(in situ)執行非反應性氣體電漿轟擊，也就是不用將包含半導體元件2之半成品移至另一個腔體，在反應腔體30內即可執行電漿轟擊。此外，在製備M層原子層沉積薄膜的過程當中，根據本發明之多功能設備3，可以針對M層原子層沉積薄膜中之N層選定的薄膜，於原子層沈積製程期間或之後，執行非反應性氣體電漿轟擊。
同樣如圖4所示，金屬夾盤36相對於偏壓電極33具有可調整的傾斜角度，以改變非反應性氣體電漿轟擊選定的薄膜12的入射角度，進一步調控薄膜品質與缺陷密度。
為印證本發明之高介電常數介電層具有低漏電流密度。本發明在電阻率(resistivity)為1-10Ω-cm的p型矽基板上，製作原子層沈積的多層HfO2薄膜，且下半部層數薄膜經He電漿轟擊的試片(下文中標註為DHe)。本發明在電阻率(resistivity)為1-10Ω-cm的p型矽基板上，製作原子層沈積的多層HfO2薄膜，且上半部層數薄膜經He電漿轟擊的試片(下文中標註為THe)。作為對照，本發明並且在電阻律(resistivity)為1-10Ω-cm的p型矽基板上，製作原子層沈積的多層HfO2薄膜，且薄膜的所有層皆未經He電漿轟擊的試片(下文中標註為Hf0)。DHe試片、THe試片及Hf0試片的ALD循環流程請見圖5所示。
接著，在DHe試片、THe試片及Hf0試片中多層HfO2薄膜的表面與矽基板的背面分別被覆Pt和Al，分別作為閘極電極與下電極，形成金氧半導體(metal-oxide-semiconductor,MOS)結構。之後在合成氣體(forming gas)為5% H2/95% N2的氣氛中於400℃持溫30分鐘執行後金屬化退火(post-metallization annealing,PMA)處理。
請參閱圖6及圖7。經PMA處理的DHe試片、THe試片及Hf0試片，其X光光電子能譜(X-ray photoelectron spectroscopy,XPS)示於圖6。經PMA處理的DHe試片、THe試片及Hf0試片之高解析穿透式電子顯微鏡(high-resolution transmission electron microscopy,HRTEM)照片示於圖7。圖6所示結果顯示經PMA處理的DHe試片，具有較高的矽酸鹽(silicate)波峰強度，顯示其具有較厚之介面層(interfacial layer)。圖7的照片也證實經PMA處理的DHe試片具有較厚的介面層。這是由於DHe試片形成過程，He電漿轟影響到鄰近矽基板的區域。此外，由圖7可知，DHe試片、THe試片及Hf0試片中的介電層的總厚度約為4nm。
請參閱表1，經PMA處理的DHe試片、THe試片及Hf0試片，經測試所得電容等效厚度(CET)、等效介電常數(effective dielectric constant,Keff)、閘極漏電流密度(gate leakage current density,Jg)、接面缺陷密度(interfacial state density,Dit)列於表1中。其中Jg的定義為在閘極電極施加平帶電壓(flat-band voltage)減1V時，試片的閘極漏電流密度。其中，DHe試片、THe試片及Hf0試片的CET皆小於為2nm。
表1所示結果證實DHe試片、THe試片的漏電流密度皆低於1×10-4A/cm2，優於未經He電漿轟擊的Hf0試片，顯示He電漿轟擊能有效增進薄膜的品質與降低缺陷密度。
請參閱圖8，經PMA處理的DHe試片、THe試片及Hf0試片經定電壓應力(constant voltage stress,CVS)測試的結果示於圖8，其中在閘極電極所施加的電壓為-4V，施加電壓的時間分別為0、40、100、400與1000sec。圖8所示結果證實，與Hf0試片相比較，DHe試片與THe試片在經過定電壓應力測試之後，其在低閘極電壓(閘極電壓的絕對值小於2V)時，閘極漏電流密度上升的程度較低，顯示經He電漿轟擊處理的DHe試片與THe試片，具有較佳的可靠度(reliability)。
藉由以上較佳具體實施例之詳述，係希望能更加清楚描述本發明之特徵與精神，而並非以上述所揭露的較佳具體實施例來對本發明之面向加以限制。相反地，其目的是希望能涵蓋各種改變及具相等性的安排於本發明所欲申請之專利範圍的面向內。因此，本發明所申請之專利範圍的面向應該根據上述的說明作最寬廣的解釋，以致使其涵蓋所有可能的改變以及具相等性的安排。

Claims (10)

  1. 一種高介電常數介電層，係形成於一半導體元件內，該高介電常數介電層包含：M層原子層沉積薄膜，係依序形成於該半導體元件之一材料層上，每一層原子層沉積薄膜係由一氧化物且藉由一原子層沈積製程所形成，M係一大於1的整數，其中該M層原子層沉積薄膜中之N層選定的薄膜，於該原子層沈積製程期間或之後，執行一非反應性氣體電漿轟擊，以對該N層選定的薄膜產生退火的效果，以降低該N層選定的薄膜之缺陷密度，N係一自然數且小於或等於M。
  2. 如請求項1所述之高介電常數介電層，其中該氧化物係選自由HfO2、ZrO2、Al2O3、La2O3、SiO2、TiO2以及Y2O3所組成之群組中之其一。
  3. 如請求項2所述之高介電常數介電層，其中該高介電常數介電層在其電容等效厚度(capacitance equivalent thickness,CET)小於2nm時，具有小於1×10-4A/cm2之一漏電流密度。
  4. 一種製造一高介電常數介電層於一半導體元件內之方法，該方法包含下列步驟：藉由一原子層沉積製程，依序形成一氧化物之M層原子層沉積薄膜於該半導體元件之一材料層上，其中M係一大於1的整數；以及針對該M層原子層沉積薄膜中之N層選定的薄膜，於該原子層沈積製程期間或之後，執行一非反應性氣體電漿轟擊，以對該N層選定的薄膜產生退火的效果，以降低該N層選定的薄膜之缺陷密度，即完成該高介電常數介電層，其中N係一自然數且小於或等於M。
  5. 如請求項4所述之方法，其中該氧化物係選自由HfO2、ZrO2、Al2O3、La2O3、SiO2、TiO2以及Y2O3所組成之群組中之其一。
  6. 如請求項5所述之方法，其中該高介電常數介電層在其電容等效厚度(capacitance equivalent thickness,CET)小於2nm時，具有小於1×10-4A/cm2之一漏電流密度。
  7. 如請求項6所述之方法，其中用以產生該非反應性氣體電漿之一惰性氣體係選自由Ar、He、Ne、He/Ar、He/N2以及He/Ne所組成之群組中之其一。
  8. 如請求項7所述之方法，其中該非反應性氣體電漿之一流量範圍從1sccm至1000sccm。
  9. 一種執行如請求項4至8中任一項所述之方法的多功能設備，包含：一反應腔體；一電漿源，係設置於該反應腔體內之一頂部；一電漿源功率產生單元，係電連接至該電漿源且被控制輸出一交流功率至該電漿源；一偏壓電極，係設置於該反應腔體內之一底部；一交流偏壓產生單元，係電連接至該偏壓電極，且被控制選擇性地輸出一交流偏壓或一直流電偏壓重疊一交流偏壓至該偏壓電極，以控制一非反應性氣體電漿轟擊的能量；一直流偏壓產生單元，係電連接至該偏壓電極，且被控制選擇性地輸出一正直流電偏壓或一負直流電偏壓至該偏壓電極，以控制該非反應性氣體電漿轟擊的能量；一金屬夾盤，係設置於該偏壓電極上，用以夾持該半導體元件之一半成品；一第一先驅物供應源，係經由一第一控制閥連通至該反應腔體，且被控制供應形成該氧化物之一第一先驅物至該反應腔體內；一第二先驅物供應源，係經由一第二控制閥連通至該反應腔體，且被控制供應形成該氧化物之一第二先驅物至該反應腔體內；一載送氣體供應源，係經由一第一流量控制器連通至該反應腔體，且被控制供應一載送氣體至該反應腔體內；一氧氣供應源，係經由一第二流量控制器連通至該反應腔體之該頂部，該氧氣供應源被控制供應一氧氣，由該電漿源之該交流功率游離成一氧氣電漿；一惰性氣體供應源，係經由一第三流量控制器連通至該反應腔體之該頂部，該惰性氣體供應源被控制供應該惰性氣體，由該電漿源之該交流功率游離成該非反應性氣體電漿；一自動壓力控制器；以及一抽氣泵，經由該自動壓力控制器連通至該反應腔體之該底部，且經由該自動壓力控制器進行抽氣速率的自動調控，以達一理想的製程壓力。
  10. 如請求項9所述之多功能設備，其中該金屬夾盤相對於該偏壓電極具有一可調整的傾斜角度。
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