CN109509788A - 高介电常数介电层、其制造方法及执行该方法的设备 - Google Patents

高介电常数介电层、其制造方法及执行该方法的设备 Download PDF

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CN109509788A
CN109509788A CN201810920927.5A CN201810920927A CN109509788A CN 109509788 A CN109509788 A CN 109509788A CN 201810920927 A CN201810920927 A CN 201810920927A CN 109509788 A CN109509788 A CN 109509788A
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layer
plasma
bias
source
dielectric constant
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CN109509788B (zh
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陈敏璋
锺镇阳
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Chen Minzhang
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Corremax International Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
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    • C23C16/45523—Pulsed gas flow or change of composition over time
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    • C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • C23C16/503—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using dc or ac discharges
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    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
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Abstract

本发明揭示一种高介电常数介电层、其制造方法及执行该方法的设备。本发明的高介电常数介电层包含依序形成于半导体元件的材料层上的M层原子层沉积薄膜，其中M是大于1的整数。该材料层可以是半导体材料层、金属层或另一介电层。每一层原子层沉积薄膜是由氧化物且通过原子层沉积制程所形成。M层原子层沉积薄膜中的N层选定的薄膜，于原子层沉积制程期间或之后，经非反应性气体等离子体轰击，其中N是自然数且小于或等于M。

Description

高介电常数介电层、其制造方法及执行该方法的设备
技术领域
本发明涉及一种高介电常数介电层、其制造方法及执行该方法的设备，尤其涉及一种具有低漏电流密度的高介电常数介电层、其制造方法及执行该方法的多功能设备。
背景技术
为了满足半导体元件在尺寸的缩小以及降低栅极漏电流上的要求，许多具有高介电常数的栅极介电材料已被提出来替代传统的介电层。以硅基半导体元件为例，Al2O3、HfO2、ZrO2、TiO2、Y2O3与La2O3等，已被提出来代替传统的SiO2栅极介电层。
然而，介电层本身的薄膜品质与缺陷密度对栅极漏电流的影响甚大。目前，对于制造具有优良的薄膜品质与低缺陷密度的介电层的制程，以及制程中或制程后处理的研究，仍有相当大的空间。
发明内容
因此，本发明所欲解决的技术问题在于提供一种具有优良薄膜品质与低缺陷密度，进而具有低漏电流密度的高介电常数介电层，以及其制造方法及执行该方法的设备。并且，根据本发明的高介电常数介电层具有优良的可靠度。
根据本发明的一较佳具体实施例的高介电常数介电层，是形成于半导体元件内。根据本发明的高介电常数介电层包含M层原子层沉积薄膜，其中M是大于1的整数。M层原子层沉积薄膜是依序形成于半导体元件的材料层上。该材料层可以是半导体材料层、金属层或另一介电层。每一层原子层沉积薄膜是由氧化物且通过原子层沉积制程(atomic layerdeposition process,ALD process)所形成。在制备M层原子层沉积薄膜的过程当中，本发明针对M层原子层沉积薄膜中的N层选定的薄膜，于原子层沉积制程期间或的后，执行非反应性气体等离子体轰击，以对此N层选定的薄膜产生退火的效果，以降低此N层选定的薄膜的缺陷密度，其中N是自然数且小于或等于M。
于一具体实施例中，根据本发明的高介电常数介电层具有较低的漏电流密度，在电容等效厚度(capacitance equivalent thickness,CET)小于2nm时，漏电流密度小于1×10-4A/cm2。并且，根据本发明的高介电常数介电层具有厚度范围从1nm至50nm。
根据本发明的一较佳具体实施例的制造高介电常数介电层于半导体元件内的方法。首先，是通过原子层沉积制程，依序形成氧化物的M层原子层沉积薄膜于半导体元件的材料层上，其中M是大于1的整数。该材料层可以是半导体材料层、金属层或另一介电层。在制备M层原子层沉积薄膜的过程当中，根据本发明的方法，针对M层原子层沉积薄膜中的N层选定的薄膜，执行非反应性气体等离子体轰击，以对此N层选定的薄膜产生退火的效果，以降低此N层选定的薄膜的缺陷密度，即完成高介电常数介电层，其中N是自然数且小于或等于M。
于一具体实施例中，氧化物可以是HfO2、ZrO2、Al2O3、La2O3、SiO2、TiO2与Y2O3等。
于一具体实施中，用以产生非反应性气体等离子体的惰性气体可以是Ar、He、Ne、He/Ar、He/N2与He/Ne等。
根据本发明的一较佳具体实施例的执行根据本发明的方法的多功能设备，包含反应腔体、等离子体源、等离子体源功率产生单元、偏压电极、交流偏压产生单元、直流偏压产生单元、金属夹盘、第一先驱物(precursor)供应源、第二先驱物供应源、载送气体(carriergas)供应源、氧气供应源、惰性气体供应源、自动压力控制器以及抽气泵。等离子体源是设置于反应腔体内的顶部。等离子体源功率产生单元是电连接至等离子体源，并且被控制输出交流功率至等离子体源。偏压电极是设置于反应腔体内的底部。交流偏压产生单元是电连接至偏压电极，并且被控制选择性地输出交流偏压或直流电偏压重叠交流偏压至偏压电极，以控制该非反应性气体等离子体轰击的能量。直流偏压产生单元是电连接至偏压电极，并且被控制选择性地输出正直流电偏压或负直流电偏压至偏压电极，以控制非反应性气体等离子体轰击的能量。金属夹盘是设置于偏压电极上，并且用以夹持半导体元件的半成品。第一先驱物供应源是经由第一控制阀连通至反应腔体，并且被控制供应形成氧化物的第一先驱物至反应腔体内。第二先驱物供应源是经由第二控制阀连通至反应腔体，并且被控制供应形成氧化物的第二先驱物至反应腔体内。载送气体供应源是经由第一流量控制器连通至反应腔体，并且被控制供应载送气体至反应腔体内。氧气供应源是经由第二流量控制器连通至反应腔体的顶部。氧气供应源被控制供应氧气，由等离子体源的交流功率游离成氧气等离子体。惰性气体供应源是经由第三流量控制器连通至反应腔体的顶部。惰性气体供应源被控制供应惰性气体，由等离子体源的交流功率游离成非反应性气体等离子体。抽气泵经由自动压力控制器连通至反应腔体的底部，并且由自动压力控制器控制对反应腔体进行抽气。
与先前技术不同，本发明的高介电常数介电层具有优良薄膜品质与低缺陷密度，并且具有低漏电流密度。
关于本发明的优点与精神可以通过以下的发明详述及附图得到进一步的了解。
附图说明
图1是根据本发明的一较佳具体实施例的高介电常数介电层的截面视图。
图2是根据本发明的一较佳具体实施例的高介电常数介电层的一变形的截面视图。
图3是根据本发明的一较佳具体实施例的高介电常数介电层的另一变形的截面视图。
图4是执行根据本发明的方法的多功能设备的架构示意图。
图5是本发明制作DHe试片、THe试片及Hf0试片的ALD循环流程示意图。
图6是经PMA处理的DHe试片、THe试片及Hf0试片经XPS量测所得的能谱。
图7是经PMA处理的DHe试片、THe试片及Hf0试片的HRTEM照片。
图8是经PMA处理的DHe试片、THe试片及Hf0试片经定电压应力(constant voltagestress,CVS)测试的结果。
附图标记说明：
1：高介电常数介电层； 10：原子层沉积薄膜；
11：未经非反应性气体等离子体轰击的原子层沉积薄膜；
12：选定的薄膜； 2：半导体元件；
3：多功能设备； 30：反应腔体；
302：顶部； 304：底部；
31：等离子体源； 32：等离子体源功率产生单元；
33：偏压电极； 34：交流偏压产生单元；
35：直流偏压产生单元； 36：金属夹盘；
37：第一先驱物供应源； 372：第一控制阀；
38：第二先驱物供应源； 382：第二控制阀；
39：氧气供应源； 392：第二流量控制器；
40：惰性气体供应源； 402：第三流量控制器；
41：自动压力控制器； 42：抽气泵；
44：载送气体供应源； 442：第一流量控制器。
具体实施方式
请参阅图1、图2及图3，该等附图是以截面视图示意地示出根据本发明的一较佳具体实施例的高介电常数介电层1。
如图1、图2及图3所示，根据本发明的较佳具体实施例的高介电常数介电层1是形成于半导体元件2内。高介电常数介电层1是形成于半导体元件的材料层上。该材料层可以是半导体材料层、金属层或另一介电层。
于一具体实施中，半导体材料层可以由Si、Ge、SiGe、GeSn、绝缘层覆硅、III-V族化合物、II-VI族化合物与IV-VI族化合物等半导体材料所形成。金属材料层可以由铂、钽、钛、钨、铜、铝、铝硅铜合金、铝铜合金、氮化钛、氮化钽、重掺杂多晶硅等金属材料所形成。
同样示于图1、图2及图3，根据本发明的高介电常数介电层1包含M层原子层沉积薄膜10，其中M是大于1的整数。M层原子层沉积薄膜10是依序形成于半导体元件2的材料层上。该材料层可以是半导体材料层、金属层或另一介电层。每一层原子层沉积薄膜10是为氧化物且通过原子层沉积制程所形成。
原子层沉积制程具有以下优点：(1)可在原子等级控制材料的形成；(2)可更精准地控制薄膜的厚度；(3)可大面积量产；(4)有优异的均匀度(uniformity)；(5)有优异的三维包覆性(conformality)；(6)无孔洞结构；(7)缺陷密度低；以及(8)沉积温度较低等制程优点。本发明所采用的原子层沉积制程可以形成原子层沉积薄膜10。
于一具体实施例中，氧化物可以是HfO2、ZrO2、Al2O3、La2O3、SiO2、TiO2与Y2O3等。
特别地，针对M层原子层沉积薄膜10中的N层选定的薄膜12，于原子层沉积制程期间或之后，执行非反应性气体等离子体轰击，以对此N层选定的薄膜12，产生退火的效果，以降低此N层选定的薄膜12的缺陷密度，其中N是自然数且小于或等于M。于图1中，符号“11”代表仅使用原子层沉积制程所形成的氧化物薄膜，未经非反应性气体等离子体轰击。符号“12”代表使用原子层沉积制程期间或之后，并经非反应性气体等离子体轰击，所形成的氧化物薄膜。
于图1所示案例，N层选定的薄膜12的层数，占所有薄膜层数的半数，且集中在本发明的高介电常数介电层1的下半部。
于图2所示案例，N层选定的薄膜12的层数，占所有薄膜层数的半数，且集中在本发明的高介电常数介电层1的上半部。
于图3所示案例，选定的薄膜12与未经非反应性气体等离子体轰击的原子层沉积薄膜11，穿插堆叠以形成本发明的高介电常数介电层1。但本发明的高介电常数介电层1并不以图1、图2及图3所示未经非反应性气体等离子体轰击的原子层沉积薄膜11与选定的薄膜12的间的排列关系为限，本发明的高介电常数介电层1也可以形成数层未经非反应性气体等离子体轰击的原子层沉积薄膜11，再形成一层选定的薄膜12。
于一具体实施中，用以产生非反应性气体等离子体的惰性气体可以是Ar、He、Ne、He/Ar、He/N2与He/Ne等。
一般在等离子体制程中，Ar被广泛用作为等离子体源的工作气体。另一方面，He在气相沉积的过程中通常用作为缓冲气体，其作为不可燃性气体来控制工作压力。与Ar等离子体相比，由于He的半径较小导致He具有较高的电离能，因此He等离子体具有较高的能量。此外，由于He的质量较小，因此He等离子体所引起的损伤低于Ar等离子体所引起的损伤。因此，采用He等离子体等非反应性气体等离子体轰击选定的薄膜12，通过等离子体轰击将能量传导至薄膜表面，进而导致退火效应。选定的薄膜12表面温度的升高会增强吸附于表面的原子(adatoms)的运动和迁移，这有利于选定的薄膜12其薄膜品质的改善并且降低缺陷密度。由温度升高引起的另一个效应，是有利于去除吸附于表面的先驱物的配体(ligands)。
藉此，根据本发明的高介电常数介电层1具有较低的漏电流密度，在其电容等效厚度(CET)小于2nm时，其漏电流密度小于1×10-4A/cm2。并且本发明的高介电常数介电层1应用于半导体元件内，其厚度范围从1nm至50nm，可以取代传统的超薄SiO2薄膜。
根据本发明的一较佳具体实施例的制造如图1、图2或图3所示高介电常数介电层1于半导体元件2内的方法，首先，是通过原子层沉积制程，依序形成氧化物的M层原子层沉积薄膜10于半导体元件2的一材料层上，其中M是大于1的整数。该材料层可以是半导体材料层、金属层或另一介电层。
根据本发明的方法，针对M层原子层沉积薄膜10中的N层选定的薄膜12，执行非反应性气体等离子体轰击，以对此N层选定的薄膜12产生退火的效果，以降低此N层选定的薄膜12的缺陷密度，即完成高介电常数介电层1，其中N是自然数且小于或等于M。本发明的高介电常数介电层1，其未经非反应性气体等离子体轰击的原子层沉积薄膜11与选定的薄膜12的间的排列关系，已于上文中详述，在此不再赘述。
形成半导体材料层的材料以及用以产生非反应性气体等离子体的惰性气体，已于上文中详述，在此不再赘述。
于一具体实施中，氧化物是HfO2。供应Hf元素的先驱物可以是HfCl4、HfI4、HfCl2[N(SiMe3)2]2、HfCp2Me2、HfCp2Cl2、Hf(CpMe)2Me2、Hf(CpMe)2(OMe)Me、Hf(CpMe)2(OiPr)Me、Hf(CpMe)2(mmp)Me、Hf(Cp)(NMe2)3、Hf(CpMe)(NMe2)3、Hf(Cp2CMe2)Me2、Hf(Cp2CMe2)Me(OMe)、Hf(OiPr)4、Hf(OtBu)4、Hf(OtBu)2(mmp)2、Hf(OtBu)(NEtMe)3、Hf(mmp)4、Hf(mp)4、Hf(ONEt2)4、Hf(NMe2)4、Hf(NEt2)4、Hf(NEtMe)4、Hf[N(SiMe3)2]2Cl2、Hf(NO3)4。供应O元素的先驱物可以是O2等离子体、N2O等离子体、O3、H2O、H2O2。
于另一具体实施中，氧化物是ZrO2。供应Zr元素的先驱物可以是ZrCl4、ZrI4、ZrCp2Cl2、ZrCp2Me2、ZrCp2Me(OMe)、ZrCp(NMe2)3、Zr(CpMe)2Me2、Zr(CpMe)2Me(OMe)、Zr(CpMe)(NMe2)3、Zr(CpEt)(NMe2)3、Zr(Cp2CMe2)Me2、Zr(Cp2CMe2)Me(OMe)、Zr(OiPr)4、Zr(OiPr)2(dmae)2、Zr(OtBu)4、Zr(OtBu)2(dmae)2、Zr(dmae)4、Zr(thd)4、Zr(NMe2)4、Zr(NEt2)4、Zr(NEtMe)4、Zr[N(SiMe3)2]2Cl2、Zr(MeAMD)4。供应O元素的先驱物可以是O2等离子体、N2O等离子体、O3、H2O、H2O2。
于另一具体实施中，氧化物是Al2O3。供应Al元素的先驱物可以是AlCl3、AlBr3、AlMe3、AlMe2Cl、AlMe2OiPr、AlEt3、Al(OEt)3、Al(OnPr)3、Al(mmp)3、Al(NEt2)3、Al(NiPr2)3、Al(iPrAMD)Et2。供应O元素的先驱物可以是O2等离子体、N2O等离子体、O3、H2O、H2O2。
于另一具体实施中，氧化物是TiO2。供应Ti元素的先驱物可以是TiF4、TiCl4、TiI4、Ti(CpMe5)(OMe)3、Ti(CpMe)(OiPr)3、Ti(OMe)4、Ti(OEt)4、Ti(OiPr)4、Ti(OiPr)2(dmae)2、Ti(OiPr)2(thd)2、Ti(trhd)2(O(CMe2Et)2、Ti(OBu)4、Ti(NMe2)4、TiCp2((iPrN)2C(NHiPr))。供应O元素的先驱物可以是O2等离子体、N2O等离子体、O3、H2O、H2O2。
于另一具体实施中，氧化物是La2O3。供应La元素的先驱物可以是La(thd)3、La[N(SiMe3)2]3、La(iPrAMD)3、La(iPrfAMD)3、La(Cp)3、La(CpEt)3、La(CpiPr)3。供应O元素的先驱物可以是O2等离子体、N2O等离子体、O3、H2O、H2O2。
于另一具体实施中，氧化物是SiO2。供应Si元素的先驱物可以是SiCl4、Si2Cl6、SiCl3H、SiCl2H2、SiH4、Si(OMe)4、Si(OEt)4、Si(OEt)3((CH2)3NH2)、Si(OtPe)3OH、HMDS、SiH2(N(CH3)2)2、SiH2(NHtBu)2、SiH2(NEt2)2、SiH(N(CH3)2)3、Si(NCO)4、MeOSi(NCO)3。供应O元素的先驱物可以是O2等离子体、N2O等离子体、O3、H2O、H2O2。
于另一具体实施中，氧化物是Y2O3。供应Y元素的先驱物可以是Y(thd)3、YCp3、Y(CpMe)3、Y(CpEt)3、Y(iPrAMD)3。供应O元素的先驱物可以是O2等离子体、N2O等离子体、O3、H2O、H2O2。
于一具体实施例中，非反应性气体等离子体的流量范围从1sccm至1000sccm。
于一具体实施例中，非反应性气体等离子体的工作压力范围从100～10-3torr.。
请参阅图4，图4是以示意图示出执行根据本发明的方法的多功能设备3的架构。
如图4所示，根据本发明的多功能设备3包含反应腔体30、等离子体源31、等离子体源功率产生单元32、偏压电极33、交流偏压产生单元34、直流偏压产生单元35、金属夹盘36、第一先驱物供应源37、第二先驱物供应源38、载送气体供应源44、氧气供应源39、惰性气体供应源40、自动压力控制器41以及抽气泵42。
等离子体源31是设置于反应腔体30内的顶部302。等离子体源功率产生单元32是电连接至等离子体源31，并且被控制输出交流功率至等离子体源31。偏压电极33是设置于反应腔体30内的底部304。交流偏压产生单元34是电连接至偏压电极33，并且被控制选择性地输出交流偏压或直流电偏压重叠交流偏压至偏压电极33，以控制非反应性气体等离子体轰击的能量。于一具体实施例中，交流偏压产生单元34被控制选择性地输出交流偏压或直流电偏压重叠交流偏压。
直流偏压产生单元35是电连接至偏压电极33，并且被控制选择性地输出正直流电偏压或负直流电偏压至偏压电极33，以控制非反应性气体等离子体轰击的能量。于一具体实施例中，直流偏压产生单元35被控制选择性地输出正直流电偏压或负直流电偏压。
金属夹盘36是设置于偏压电极33上，并且用以夹持半导体元件2的半成品。
第一先驱物供应源37是经由第一控制阀372连通至该反应腔体30，并且被控制供应形成氧化物的第一先驱物至反应腔体30内。第二先驱物供应源38是经由第二控制阀382连通至反应腔体30，并且被控制供应形成氧化物的第二先驱物至反应腔体30内。
载送气体供应源44是经由第一流量控制器442连通至反应腔体30，并且被控制供应载送气体至反应腔体30内。
氧气供应源39是经由第二流量控制器392连通至反应腔体30的顶部302。氧气供应源39被控制供应氧气，由等离子体源的交流功率游离成氧气等离子体。惰性气体供应源40是经由第三流量控制器402连通至反应腔体30的顶部302。惰性气体供应源40被控制供应惰性气体，由等离子体源的交流功率游离成非反应性气体等离子体。抽气泵42经由自动压力控制器41连通至反应腔体30的底部304，并且经由自动压力控制器41进行抽气速率的自动调控，以达理想的制程压力。
须强调的是，根据本发明的多功能设备3可以在原地(in situ)执行非反应性气体等离子体轰击，也就是不用将包含半导体元件2的半成品移至另一个腔体，在反应腔体30内即可执行等离子体轰击。此外，在制备M层原子层沉积薄膜的过程当中，根据本发明的多功能设备3，可以针对M层原子层沉积薄膜中的N层选定的薄膜，于原子层沉积制程期间或的后，执行非反应性气体等离子体轰击。
同样如图4所示，金属夹盘36相对于偏压电极33具有可调整的倾斜角度，以改变非反应性气体等离子体轰击选定的薄膜12的入射角度，进一步调控薄膜品质与缺陷密度。
为印证本发明的高介电常数介电层具有低漏电流密度。本发明在电阻律(resistivity)为1–10Ω-cm的p型硅基板上，制作原子层沉积的多层HfO2薄膜，且下半部层数薄膜经He等离子体轰击的试片(下文中标注为DHe)。本发明在电阻率(resistivity)为1–10Ω-cm的p型硅基板上，制作原子层沉积的多层HfO2薄膜，且上半部层数薄膜经He等离子体轰击的试片(下文中标注为THe)。作为对照，本发明并且在电阻律(resistivity)为1–10Ω-cm的p型硅基板上，制作原子层沉积的多层HfO2薄膜，且薄膜的所有层皆未经He等离子体轰击的试片(下文中标注为Hf0)。DHe试片、THe试片及Hf0试片的ALD循环流程请见图5所示。
接着，在DHe试片、THe试片及Hf0试片中多层HfO2薄膜的表面与硅基板的背面分别被覆Pt和Al，分别作为栅极电极与下电极，形成金氧半导体(metal-oxide-semiconductor,MOS)结构。之后在合成气体(forming gas)为5％H2/95％N2的气氛中于400℃持温30分钟执行后金属化退火(post-metallization annealing,PMA)处理。
请参阅图6及图7。经PMA处理的DHe试片、THe试片及Hf0试片，其X光光电子能谱(X-ray photoelectron spectroscopy,XPS)示于图6。经PMA处理的DHe试片、THe试片及Hf0试片的高解析穿透式电子显微镜(high-resolution transmission electron microscopy,HRTEM)照片示于图7。图6所示结果显示经PMA处理的DHe试片，具有较高的硅酸盐(silicate)波峰强度，显示其具有较厚的介面层(interfacial layer)。图7的照片也证实经PMA处理的DHe试片具有较厚的介面层。这是由于DHe试片形成过程，He等离子体轰影响到邻近硅基板的区域。此外，由图7可知，DHe试片、THe试片及Hf0试片中的介电层的总厚度约为4nm。
请参阅表1，经PMA处理的DHe试片、THe试片及Hf0试片，经测试所得电容等效厚度(CET)、等效介电常数(effective dielectric constant,Keff)、栅极漏电流密度(gateleakage current density,Jg)、接面缺陷密度(interfacial state density,Dit)列于表1中。其中Jg的定义为在栅极电极施加平带电压(flat-band voltage)减1V时，试片的栅极漏电流密度。其中，DHe试片、THe试片及Hf0试片的CET皆小于为2nm。
表1
经PMA处理 Hf0 DHe THe
CET(nm) 1.61 1.85 1.61
K<sub>eff</sub> 9.69 8.43 9.7
J<sub>g</sub>(A/cm<sup>2</sup>) 1.67×10<sup>-4</sup> 1.34×10<sup>-5</sup> 2.44×10<sup>-5</sup>
D<sub>it</sub>(cm<sup>-2</sup>eV<sup>-1</sup>) 7.25×10<sup>11</sup> 3.46×10<sup>11</sup> 4.60×10<sup>11</sup>
表1所示结果证实DHe试片、THe试片的漏电流密度皆低于1×10-4A/cm2，优于未经He等离子体轰击的Hf0试片，显示He等离子体轰击能有效增进薄膜的品质与降低缺陷密度。
请参阅图8，经PMA处理的DHe试片、THe试片及Hf0试片经定电压应力(constantvoltage stress,CVS)测试的结果示于图8，其中在栅极电极所施加的电压为-4V，施加电压的时间分别为0、40、100、400与1000sec。图8所示结果证实，与Hf0试片相比较，DHe试片与THe试片在经过定电压应力测试之后，其在低栅极电压(栅极电压的绝对值小于2V)时，栅极漏电流密度上升的程度较低，显示经He等离子体轰击处理的DHe试片与THe试片，具有较佳的可靠度(reliability)。
通过以上较佳具体实施例的详述，是希望能更加清楚描述本发明的特征与精神，而并非以上述所揭示的较佳具体实施例来对本发明的面向加以限制。相反地，其目的是希望能涵盖各种改变及具相等性的安排于本发明所附的权利要求的面向内。因此，本发明所附权利要求的面向应该根据上述的说明作最宽广的解释，以致使其涵盖所有可能的改变以及具相等性的安排。

Claims (10)

1.一种高介电常数介电层，是形成于半导体元件内，所述高介电常数介电层包含：
M层原子层沉积薄膜，是依序形成于所述半导体元件的材料层上，每一层原子层沉积薄膜是由氧化物且通过原子层沉积制程所形成，M是大于1的整数，其中所述M层原子层沉积薄膜中的N层选定的薄膜，于所述原子层沉积制程期间或之后，执行非反应性气体等离子体轰击，以对所述N层选定的薄膜产生退火的效果，以降低所述N层选定的薄膜的缺陷密度，N是自然数且小于或等于M。
2.根据权利要求1所述的高介电常数介电层，其中所述氧化物是选自由HfO2、ZrO2、Al2O3、La2O3、SiO2、TiO2以及Y2O3所组成的群组中的其一。
3.根据权利要求2所述的高介电常数介电层，其中所述高介电常数介电层在其电容等效厚度CET小于2nm时，具有小于1×10-4A/cm2的漏电流密度。
4.一种制造高介电常数介电层于半导体元件内的方法，所述方法包含下列步骤：
通过原子层沉积制程，依序形成氧化物的M层原子层沉积薄膜于所述半导体元件的材料层上，其中M是大于1的整数；以及
针对所述M层原子层沉积薄膜中的N层选定的薄膜，于所述原子层沉积制程期间或之后，执行非反应性气体等离子体轰击，以对所述N层选定的薄膜产生退火的效果，以降低所述N层选定的薄膜的缺陷密度，即完成所述高介电常数介电层，其中N是自然数且小于或等于M。
5.根据权利要求4所述的方法，其中所述氧化物是选自由HfO2、ZrO2、Al2O3、La2O3、SiO2、TiO2以及Y2O3所组成的群组中的其一。
6.根据权利要求5所述的方法，其中所述高介电常数介电层在其电容等效厚度CET小于2nm时，具有小于1×10-4A/cm2的漏电流密度。
7.根据权利要求6所述的方法，其中用以产生所述非反应性气体等离子体的惰性气体是选自由Ar、He、Ne、He/Ar、He/N2以及He/Ne所组成的群组中的其一。
8.根据权利要求7所述的方法，其中所述非反应性气体等离子体的流量范围从1sccm至1000sccm。
9.一种执行根据权利要求4至8中任一项所述的方法的多功能设备，包含：
反应腔体；
等离子体源，是设置于所述反应腔体内的顶部；
等离子体源功率产生单元，是电连接至所述等离子体源且被控制输出交流功率至所述等离子体源；
偏压电极，是设置于所述反应腔体内的底部；
交流偏压产生单元，是电连接至所述偏压电极，且被控制选择性地输出交流偏压或直流电偏压重叠交流偏压至所述偏压电极，以控制非反应性气体等离子体轰击的能量；
直流偏压产生单元，是电连接至所述偏压电极，且被控制选择性地输出正直流电偏压或负直流电偏压至所述偏压电极，以控制所述非反应性气体等离子体轰击的能量；
金属夹盘，是设置于所述偏压电极上，用以夹持所述半导体元件的半成品；
第一先驱物供应源，是经由第一控制阀连通至所述反应腔体，且被控制供应形成所述氧化物的第一先驱物至所述反应腔体内；
第二先驱物供应源，是经由第二控制阀连通至所述反应腔体，且被控制供应形成所述氧化物的第二先驱物至所述反应腔体内；
载送气体供应源，是经由第一流量控制器连通至所述反应腔体，且被控制供应载送气体至所述反应腔体内；
氧气供应源，是经由第二流量控制器连通至所述反应腔体的所述顶部，所述氧气供应源被控制供应氧气，由所述等离子体源的所述交流功率游离成氧气等离子体；
惰性气体供应源，是经由第三流量控制器连通至所述反应腔体的所述顶部，所述惰性气体供应源被控制供应所述惰性气体，由所述等离子体源的所述交流功率游离成所述非反应性气体等离子体；
自动压力控制器；以及
抽气泵，经由所述自动压力控制器连通至所述反应腔体的所述底部，且经由所述自动压力控制器进行抽气速率的自动调控，以达理想的制程压力。
10.根据权利要求9所述的多功能设备，其中所述金属夹盘相对于所述偏压电极具有可调整的倾斜角度。
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