CN100505311C - 非对称凹陷栅极金属氧化物半导体场效应晶体管及其制法 - Google Patents

非对称凹陷栅极金属氧化物半导体场效应晶体管及其制法 Download PDF

Info

Publication number
CN100505311C
CN100505311C CNB2005100821574A CN200510082157A CN100505311C CN 100505311 C CN100505311 C CN 100505311C CN B2005100821574 A CNB2005100821574 A CN B2005100821574A CN 200510082157 A CN200510082157 A CN 200510082157A CN 100505311 C CN100505311 C CN 100505311C
Authority
CN
China
Prior art keywords
gate electrode
recessed
depressed area
impurity range
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2005100821574A
Other languages
English (en)
Chinese (zh)
Other versions
CN1794467A (zh
Inventor
徐文植
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of CN1794467A publication Critical patent/CN1794467A/zh
Application granted granted Critical
Publication of CN100505311C publication Critical patent/CN100505311C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/025—Manufacture or treatment forming recessed gates, e.g. by using local oxidation
    • H10D64/027—Manufacture or treatment forming recessed gates, e.g. by using local oxidation by etching at gate locations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/608—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having non-planar bodies, e.g. having recessed gate electrodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)
CNB2005100821574A 2004-12-24 2005-07-04 非对称凹陷栅极金属氧化物半导体场效应晶体管及其制法 Expired - Fee Related CN100505311C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020040112365A KR100574497B1 (ko) 2004-12-24 2004-12-24 비대칭 리세스된 게이트를 갖는 ｍｏｓｆｅｔ 및 그 제조방법
KR112365/04 2004-12-24

Publications (2)

Publication Number Publication Date
CN1794467A CN1794467A (zh) 2006-06-28
CN100505311C true CN100505311C (zh) 2009-06-24

Family

ID=36610395

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2005100821574A Expired - Fee Related CN100505311C (zh) 2004-12-24 2005-07-04 非对称凹陷栅极金属氧化物半导体场效应晶体管及其制法

Country Status (5)

Country Link
US (1) US7723768B2 (enExample)
JP (1) JP4999289B2 (enExample)
KR (1) KR100574497B1 (enExample)
CN (1) CN100505311C (enExample)
TW (1) TWI293777B (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102446962A (zh) * 2010-10-14 2012-05-09 上海华虹Nec电子有限公司 兼容自对准孔的mosfet闸极膜结构及图形制作方法
CN103296069A (zh) * 2012-02-28 2013-09-11 台湾积体电路制造股份有限公司 FinFET及其制造方法

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101204663B1 (ko) * 2006-05-09 2012-11-26 에스케이하이닉스 주식회사 반도체소자의 리세스 게이트 전극 구조 및 그 형성방법
US20080001215A1 (en) 2006-06-30 2008-01-03 Hynix Semiconductor Inc. Semiconductor device having recess gate and method of fabricating the same
KR100780620B1 (ko) * 2006-06-30 2007-11-30 주식회사 하이닉스반도체 리세스 게이트를 갖는 반도체소자 및 그 제조 방법
KR100842908B1 (ko) 2006-09-30 2008-07-02 주식회사 하이닉스반도체 리세스 게이트를 갖는 반도체 소자 및 그의 제조방법
KR100781874B1 (ko) * 2006-12-26 2007-12-05 주식회사 하이닉스반도체 반도체 소자의 제조방법
JP2008199027A (ja) * 2007-02-13 2008-08-28 Qimonda Ag ３次元チャネル電界効果トランジスタを備えた集積回路およびその製造方法
KR100908522B1 (ko) 2007-06-28 2009-07-20 주식회사 하이닉스반도체 반도체 소자 및 그 제조 방법
KR101397598B1 (ko) * 2007-07-16 2014-05-23 삼성전자 주식회사 반도체 집적 회로 장치 및 그 제조 방법
KR100875170B1 (ko) * 2007-08-09 2008-12-22 주식회사 동부하이텍 반도체 소자의 리세스 게이트 및 그의 형성 방법
JP5628471B2 (ja) * 2007-12-10 2014-11-19 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置及び半導体装置の製造方法
US20090309139A1 (en) * 2008-06-13 2009-12-17 International Business Machines Corporation Asymmetric gate electrode and method of manufacture
KR101083644B1 (ko) 2008-07-04 2011-11-16 주식회사 하이닉스반도체 반도체 장치 및 그 제조방법
KR101570178B1 (ko) 2008-11-07 2015-11-18 삼성전자주식회사 커패시터 없는 디램 소자
KR101061178B1 (ko) * 2008-12-30 2011-09-01 주식회사 하이닉스반도체 반도체 소자 및 그의 제조방법
KR101077301B1 (ko) * 2009-04-09 2011-10-26 주식회사 하이닉스반도체 낮은 콘택 저항을 가지는 반도체 장치의 제조 방법
KR101078731B1 (ko) 2009-06-09 2011-11-01 주식회사 하이닉스반도체 반도체 소자의 제조방법
JP2012134439A (ja) 2010-11-30 2012-07-12 Elpida Memory Inc 半導体装置及びその製造方法
KR101853316B1 (ko) 2012-03-29 2018-04-30 삼성전자주식회사 반도체 소자
WO2014158198A1 (en) * 2013-03-29 2014-10-02 Intel Corporation Transistor architecture having extended recessed spacer and source/drain regions and method of making same
US9240482B2 (en) 2014-05-30 2016-01-19 Globalfoundries Inc. Asymmetric stressor DRAM
US10014391B2 (en) 2016-06-28 2018-07-03 International Business Machines Corporation Vertical transport field effect transistor with precise gate length definition
WO2020198930A1 (en) 2019-03-29 2020-10-08 Shenzhen Xpectvision Technology Co., Ltd. Apparatuses for radiation detection and methods of making them
EP3948359B1 (en) * 2019-03-29 2023-12-27 Shenzhen Xpectvision Technology Co., Ltd. Apparatuses for detecting radiation and their methods of making
US11424360B1 (en) 2021-02-04 2022-08-23 Nanya Technology Corporation Semiconductor device and method for manufacturing the same
KR20220158340A (ko) * 2021-05-24 2022-12-01 삼성전자주식회사 게이트 구조체를 갖는 반도체 소자들 및 그 형성 방법
EP4123694A1 (en) * 2021-07-22 2023-01-25 Imec VZW A semiconductor structure with an epitaxial layer stack for fabricating back-side contacts
WO2023212887A1 (en) * 2022-05-06 2023-11-09 Yangtze Advanced Memory Industrial Innovation Center Co., Ltd Memory peripheral circuit having recessed channel transistors with elevated sources/drains and method for forming thereof

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5787545U (enExample) * 1980-11-17 1982-05-29
US5640034A (en) * 1992-05-18 1997-06-17 Texas Instruments Incorporated Top-drain trench based resurf DMOS transistor structure
JPH07153952A (ja) * 1993-11-30 1995-06-16 Sony Corp 半導体装置及びその製造方法
JPH07288324A (ja) * 1994-04-18 1995-10-31 Sony Corp Ｍｏｓ型トランジスタ
US5434435A (en) * 1994-05-04 1995-07-18 North Carolina State University Trench gate lateral MOSFET
US5828101A (en) * 1995-03-30 1998-10-27 Kabushiki Kaisha Toshiba Three-terminal semiconductor device and related semiconductor devices
US6034396A (en) * 1998-01-28 2000-03-07 Texas Instruments - Acer Incorporated Ultra-short channel recessed gate MOSFET with a buried contact
KR100304717B1 (ko) * 1998-08-18 2001-11-15 김덕중 트렌치형게이트를갖는반도체장치및그제조방법
US6190971B1 (en) * 1999-05-13 2001-02-20 International Business Machines Corporation Formation of 5F2 cell with partially vertical transistor and gate conductor aligned buried strap with raised shallow trench isolation region
KR100338104B1 (ko) * 1999-06-30 2002-05-24 박종섭 반도체 소자의 제조 방법
KR100307531B1 (ko) * 1999-08-09 2001-11-01 김영환 모스페트 소자와 이를 이용한 메모리셀 및 그 제조 방법
US6358800B1 (en) * 2000-09-18 2002-03-19 Vanguard International Semiconductor Corporation Method of forming a MOSFET with a recessed-gate having a channel length beyond photolithography limit
US6261894B1 (en) * 2000-11-03 2001-07-17 International Business Machines Corporation Method for forming dual workfunction high-performance support MOSFETs in EDRAM arrays
US6414347B1 (en) * 2001-01-10 2002-07-02 International Business Machines Corporation Vertical MOSFET
US6429068B1 (en) 2001-07-02 2002-08-06 International Business Machines Corporation Structure and method of fabricating embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect
US6677205B2 (en) * 2001-09-28 2004-01-13 Infineon Technologies Ag Integrated spacer for gate/source/drain isolation in a vertical array structure
KR100498476B1 (ko) * 2003-01-11 2005-07-01 삼성전자주식회사 리세스 채널 ｍｏｓｆｅｔ 및 그 제조방법
KR100539276B1 (ko) * 2003-04-02 2005-12-27 삼성전자주식회사 게이트 라인을 포함하는 반도체 장치 및 이의 제조 방법
GB0316407D0 (en) * 2003-07-12 2003-08-13 Rolls Royce Plc Electrical machine
KR100500473B1 (ko) 2003-10-22 2005-07-12 삼성전자주식회사 반도체 소자에서의 리세스 게이트 트랜지스터 구조 및형성방법
KR100518606B1 (ko) 2003-12-19 2005-10-04 삼성전자주식회사 실리콘 기판과 식각 선택비가 큰 마스크층을 이용한리세스 채널 어레이 트랜지스터의 제조 방법

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102446962A (zh) * 2010-10-14 2012-05-09 上海华虹Nec电子有限公司 兼容自对准孔的mosfet闸极膜结构及图形制作方法
CN103296069A (zh) * 2012-02-28 2013-09-11 台湾积体电路制造股份有限公司 FinFET及其制造方法

Also Published As

Publication number Publication date
US20060138477A1 (en) 2006-06-29
US7723768B2 (en) 2010-05-25
CN1794467A (zh) 2006-06-28
TWI293777B (en) 2008-02-21
JP4999289B2 (ja) 2012-08-15
KR100574497B1 (ko) 2006-04-27
JP2006186303A (ja) 2006-07-13
TW200623230A (en) 2006-07-01

Similar Documents

Publication Publication Date Title
CN100505311C (zh) 非对称凹陷栅极金属氧化物半导体场效应晶体管及其制法
US5998835A (en) High performance MOSFET device with raised source and drain
US7154154B2 (en) MOS transistors having inverted T-shaped gate electrodes
KR100843711B1 (ko) 리세스 채널 영역을 갖는 트랜지스터를 채택하는반도체소자 및 그 제조방법
US6924529B2 (en) MOS transistor having a recessed gate electrode and fabrication method thereof
KR20070002590A (ko) 반도체 소자의 리세스 게이트 형성 방법
JP5341639B2 (ja) 半導体装置および半導体装置の製造方法
US20080079071A1 (en) Semiconductor device for preventing reciprocal influence between neighboring gates and method for manufacturing the same
CN100463146C (zh) 具有凹进沟道与非对称结的半导体器件的制造方法
US20090209073A1 (en) Gate Structure in a Trench Region of a Semiconductor Device and Method for Manufacturing the Same
KR100668862B1 (ko) 리세스 채널 트랜지스터 및 그 형성방법
KR20080104779A (ko) 리세스 채널 영역을 갖는 트랜지스터를 채택하는 반도체소자 및 그 제조 방법
US6362060B2 (en) Method for forming semiconductor device having a gate in the trench
US7825463B2 (en) Semiconductor device having asymmetric bulb-type recess gate and method for manufacturing the same
US8658491B2 (en) Manufacturing method of transistor structure having a recessed channel
KR100488099B1 (ko) 쇼오트 채널 모오스 트랜지스터 및 그 제조 방법
KR20050045715A (ko) 리세스 채널 모오스 트렌지스터를 갖는 반도체 장치의제조 방법
KR100854502B1 (ko) 리세스 채널 영역을 갖는 트랜지스터를 채택하는반도체소자 및 그 제조방법
JP2007081107A (ja) 半導体装置及びその製造方法
KR20060128472A (ko) 리세스된 게이트 전극을 갖는 모스 트랜지스터 및 그제조방법
US6812522B2 (en) Lateral type power MOS transistor having trench gate formed on silicon-on-insulator (SOI) substrate
US7279741B2 (en) Semiconductor device with increased effective channel length and method of manufacturing the same
KR20050025206A (ko) 모스 전계효과 트랜지스터의 제조방법 및 그에 의해제조된 모스 전계효과 트랜지스터
KR20050047659A (ko) 리세스 채널 모오스 트렌지스터의 제조 방법
KR20060000552A (ko) 리세스 채널 트랜지스터를 갖는 반도체 장치의 제조 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090624

Termination date: 20130704