WO2023212887A1

WO2023212887A1 - Memory peripheral circuit having recessed channel transistors with elevated sources/drains and method for forming thereof

Info

Publication number: WO2023212887A1
Application number: PCT/CN2022/091082
Authority: WO
Inventors: Shao-Fu Sanford Chu; Jun Liu
Original assignee: Yangtze Advanced Memory Industrial Innovation Center Co., Ltd
Priority date: 2022-05-06
Filing date: 2022-05-06
Publication date: 2023-11-09
Also published as: CN115004377A

Abstract

In certain aspects, a memory device includes an array of memory cells and a plurality of peripheral circuits coupled to the array of memory cells. The peripheral circuits include a first peripheral circuit including a recessed channel transistor. The recessed channel transistor includes a well having a recess, a recess gate structure protruding into the recess of the well and including a gate dielectric, and a gate electrode on the gate dielectric, a spacer structure on a sidewall of the gate electrode, and a source and a drain spaced apart by the spacer structure. A top surface of the source and the drain is elevated from a bottom surface of the spacer structure.

Description

[Title established by the ISA under Rule 37.2] MEMORY PERIPHERAL CIRCUIT HAVING RECESSED CHANNEL TRANSISTORS WITH ELEVATED SOURCES/DRAINS AND METHOD FOR FORMING THEREOF

BACKGROUND

The present disclosure relates to semiconductor devices and fabrication methods thereof.

Memory peripheral circuits, such page buffer circuits, driving circuits, and input/output (I/O) circuits, are used for facilitating the operations of the memory cells in memory devices, for example, NAND and NOR Flash memory devices, phase-change memory (PCM) devices, and ferroelectric memory devices. Transistors, such as metal–oxide–semiconductor (MOS) transistors, are used to form the peripheral circuits. Continued MOS transistor shrinking is thus required for shrinking memory chips.

SUMMARY

In one aspect, a memory device includes an array of memory cells and a plurality of peripheral circuits coupled to the array of memory cells. The peripheral circuits include a first peripheral circuit including a recessed channel transistor. The recessed channel transistor includes a well having a recess, a recess gate structure protruding into the recess of the well and including a gate dielectric, and a gate electrode on the gate dielectric, a spacer structure on a sidewall of the gate electrode, and a source and a drain spaced apart by the spacer structure. A top surface of the source and the drain is elevated from a bottom surface of the spacer structure.

In some implementations, a depth between the top surface of the source and the drain and the bottom surface of the spacer structure is not less than 100 nm.

In some implementations, the depth is between 100 nm and 150 nm.

In some implementations, each of the source and the drain includes an elevated portion above the bottom surface of the spacer structure and in contact with the sidewall of the spacer structure.

In some implementations, the elevated portion includes single crystalline silicon.

In some implementations, a first doping concentration of the elevated portion is higher than a second doping concentration of a reminder of the respective source or drain.

In some implementations, a difference between the first and second doping concentrations is at least 10-fold.

In some implementations, the spacer structure includes an inner spacer in contact with the sidewall of the gate electrode, and an outer spacer having a different material from the inner spacer.

In some implementations, the peripheral circuits further include a second peripheral circuit comprising a planar transistor. In some implementations, the planar transistor includes a well, a flat gate structure on the well and including a gate dielectric, and a gate electrode on the gate dielectric, and a spacer structure on a sidewall of the gate electrode. In some implementations, a lateral dimension of the spacer structure of the recessed channel transistor is greater than a lateral dimension of the spacer structure of the planar transistor.

In some implementations, the spacer structure of the planar transistor includes an inner spacer having a same material as the inner spacer of the spacer structure of the recessed channel transistor. In some implementations, the spacer structure of the planar transistor does not include an outer spacer.

In some implementations, the planar transistor further includes a source and a drain. In some implementations, a top surface of the source and the drain is coplanar with a bottom surface of the spacer structure.

In some implementations, a thickness of the gate dielectric of the recessed channel transistor is greater than a thickness of the gate dielectric of the planar transistor.

In some implementations, the first peripheral circuit includes a driving circuit.

In some implementations, the first peripheral circuit is coupled to a voltage source of greater than 3.3 V.

In some implementations, the voltage source is between 5 V and 30 V.

In another aspect, a semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor includes a first well in the substrate and having a recess, a recess gate structure protruding into the recess of the first well and including a first gate dielectric, and a first gate electrode on the first gate dielectric, a first spacer structure on a sidewall of the first gate electrode, and a source and a drain spaced apart by the first spacer structure and each including an elevated portion above a bottom surface of the first spacer structure and in contact with the sidewall of the first spacer structure. The second transistor includes a second well in the substrate, a flat gate structure on the second well and including a second gate dielectric, and a second gate electrode on the second gate dielectric, and a second spacer structure on a sidewall of the second gate electrode. The lateral dimension of the first spacer structure is greater than a lateral dimension of the second spacer structure.

In some implementations, a thickness of the first gate dielectric is greater than a thickness of the second gate dielectric.

In some implementations, a depth of the elevated portion is not less than 100 nm.

In some implementations, the depth is between 100 nm and 150 nm.

In some implementations, the substrate and the elevated portion include single crystalline silicon.

In some implementations, the first spacer structure includes a first inner spacer in contact with the sidewall of the first gate electrode, and an outer spacer having a different material from the first inner spacer. In some implementations, the second spacer structure includes a second inner spacer having a same material as the first inner spacer, and does not include an outer spacer.

In still another aspect, a method for forming a semiconductor device is provided. A recess is formed in a substrate. A first gate dielectric is formed on a sidewall and a bottom surface of the recess, and a second gate dielectric is formed on the substrate. A first gate electrode is formed on the first gate dielectric, and a second gate electrode is formed on the second gate dielectric. A first spacer structure is formed on a sidewall of the first gate electrode above the substrate, and a second spacer structure is formed on a sidewall of the second gate electrode. A lateral dimension of the first spacer structure is greater than a lateral dimension of the second spacer structure. An elevated portion is formed above the substrate and in contact with a sidewall of the first spacer structure. A first source and a first drain are formed in at least the elevated portion.

In some implementations, to form the elevated portion, single crystalline silicon is epitaxially grown from the substrate.

In some implementations, the depth is between 100 nm and 150 nm.

In some implementations, to form the first spacer structure and the second spacer structure, a first inner spacer is formed in contact with the sidewall of the first gate dielectric, and a second inner spacer is formed in contact with the sidewall of the second gate electrode, a first outer spacer is formed in contact with a sidewall of the first inner spacer, and a second outer spacer is formed in contact with a sidewall of the second inner spacer, and the second outer spacer is removed.

In some implementations, to form the first source and the first drain, at least the elevated portion is doped.

In some implementations, to dope at least the elevated portion, dopants are doped into the elevated portion, and the dopants are locally annealed.

In some implementations, a first well and a second well are formed in the substrate, such that the recess is in the first well, and the second gate dielectric is on the second well. In some implementations, a second source and a second drain are formed in the second well.

In some implementations, the first source and the first drain are formed in the elevated portion and the first well.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

FIG. 1 illustrates a schematic diagram of an exemplary memory device having a memory cell array and peripheral circuits, according to some aspects of the present disclosure.

FIG. 2 illustrates a block diagram of exemplary peripheral circuits of the memory device in FIG. 1, according to some aspects of the present disclosure.

FIG. 3 illustrates a block diagram of peripheral circuits provided with various voltages, according to some aspects of the present disclosure

FIG. 4 illustrates a plan view and a side view of cross-sections of an exemplary planar transistor, according to some aspects of the present disclosure.

FIG. 5 illustrates a plan view and a side view of cross-sections of an exemplary recessed channel transistor, according to some aspects of the present disclosure.

FIG. 6A illustrates a side view of a cross-section of an exemplary recessed channel transistor, according to some aspects of the present disclosure.

FIG. 6B illustrates a side view of a cross-section of another exemplary recessed channel transistor, according to some aspects of the present disclosure.

FIG. 6C illustrates a side view of a cross-section of still another exemplary recessed channel transistor, according to some aspects of the present disclosure.

FIG. 7A illustrates an exemplary source/drain junction profile of the recessed channel transistor in FIG. 6B, according to some aspects of the present disclosure.

FIG. 7B illustrates another exemplary source/drain junction profile of the recessed channel transistor in FIG. 6C, according to some aspects of the present disclosure.

FIG. 8 illustrates a side view of a cross-section of an exemplary semiconductor device having recessed channel transistors and planar transistors, according to some aspects of the present disclosure.

FIGs. 9A–9K illustrate a fabrication process for forming an exemplary semiconductor device having recessed channel transistors and planar transistors, according to some aspects of the present disclosure.

FIG. 10 illustrates a flowchart of an exemplary method for forming a semiconductor device having a recessed channel transistor and a planar transistor, according to some aspects of the present disclosure.

FIG. 11 illustrates a flowchart of another exemplary method for forming a semiconductor device having a recessed channel transistor and a planar transistor, according to some aspects of the present disclosure.

The present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements can be used without departing from the scope of the present disclosure. Also, the present disclosure can also be employed in a variety of other applications. Functional and structural features as described in the present disclosures can be combined, adjusted, and modified with one another and in ways not specifically depicted in the drawings, such that these combinations, adjustments, and modifications are within the scope of the present disclosure.

In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a, ” “an, ” or “the, ” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

It should be readily understood that the meaning of “on, ” “above, ” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” not only means “directly on” something but also includes the meaning of “on” something with an intermediate feature or a layer therebetween, and that “above” or “over” not only means the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer therebetween (i.e., directly on something) .

Further, spatially relative terms, such as “beneath, ” “below, ” “lower, ” “above, ” “upper, ” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element (s) or feature (s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, the term “substrate” refers to a material onto which subsequent material layers are added. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpatterned. Furthermore, the substrate can include a wide array of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from an electrically non-conductive material, such as a glass, a plastic, or a sapphire wafer.

As used herein, the term “layer” refers to a material portion including a region with a thickness. A layer can extend over the entirety of an underlying or overlying structure or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layers thereupon, thereabove, and/or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductors and contact layers (in which interconnect lines and/or vertical interconnect access (via) contacts are formed) and one or more dielectric layers.

With the development of memory devices, such as NAND and NOR Flash memory devices, PCM devices, and ferroelectric memory devices, more memory cells require more peripheral circuits (and the components, e.g., transistors, forming the peripheral circuits) for operating the memory devices. For example, the number and/or size of page buffer circuits needs to increase to match the increased number of memory cells. In another example, the number of driving circuits in the word line drivers or bit line drivers is proportional to the number of word lines or bit lines in some memory devices. Moreover, in some 3D memory devices in which the memory cell array and peripheral circuits are fabricated on different substrates and bonded together, the continuous increase of peripheral circuits’ areas makes it the bottleneck for reducing the total chip size since the memory cell array can be scaled up vertically by increasing the number of levels instead of increasing the planar size.

Thus, it is desirable to reduce the planar areas occupied by the peripheral circuits of the memory devices with the increased numbers of peripheral circuits and the transistors thereof. However, scaling down the transistor size of the peripheral circuits following the advanced complementary metal-oxide-semiconductor (CMOS) technology node trend used for the logic devices would cause a significant cost increase and higher leakage current (a.k.a. off-state current I _off) due to device channel leakage and hot carrier injection (HCI) reliability constraints, which are undesirable for memory devices.

Moreover, because some memory devices, such as NAND and NOR Flash memory devices, require a relatively high voltage (e.g., above 5 V) in certain memory operations, such as write and erase, unlike logic devices, which can reduce its working voltage as the CMOS technology node advances, the voltage provided to the memory peripheral circuits cannot be reduced. As a result, scaling down the memory peripheral circuit sizes by following the trend for advancing the CMOS technology nodes, like the normal logic devices, becomes infeasible.

One way to reduce the size of the peripheral circuits is to shrink the transistor area by gate width and length shrinkage, which, however, can cause channel leakage degradation, thereby limiting the device area shrinkage percentage. Thus, the reduction of the peripheral circuits in memory devices without sacrificing much performance has become more and more challenging.

To address one or more of the aforementioned issues, the present disclosure introduces a solution in which recessed channel transistors (RCTs) replace the planar transistors in forming some of the peripheral circuits in a memory device. That is, the peripheral circuits can have a mixed type of transistors (both recessed channel transistors and planar transistors) , which can balance the device size shrinkage and the performance degradation. In some implementations, transistors working at relatively high voltages (e.g., above 3.3 V) in some peripheral circuits, such as driving circuits in word line drivers or bit line drivers, are recessed channel transistors in order to reduce the transistor size while using less advanced technology nodes (e.g., 55 nm and above) .

One drawback of recesses gate transistors is the larger gate-induced drain leakage (GIDL) current from a larger gate to source/drain overlap and depletion area (a.k.a., extended gated diode) due to the protrusion of the recess gate structure into the well in the substrate. Also, the GIDL leakage current can increase as the gate voltage of the recesses gate transistors increases, which becomes a more serious issue for recesses gate transistors working at relatively high voltages (e.g., above 3.3 V) in some peripheral circuits, such as driving circuits. The present disclosure further introduces various solutions to further address the issues of increased GIDL current associated with recesses gate transistors in memory peripheral circuits.

Consistent with the scope of the present disclosure, in some implementations, the top surface of the source/drain of a recess gate transistor is elevated from the top surface of the substrate (i.e., the bottom surface of the spacer structure) to reduce the depletion area (i.e., the gate to source/drain overlap area) and the electric field in the source/drain and well junction, thereby weakening the GIDL effect. The elevated portion of the source/drain can further shrink the transistor size, such as the channel length, because of shallow junction depth below the top surface of the substrate.

Consistent with the scope of the present disclosure, in some implementations, a high-low source/drain doping scheme is applied to minimize the GIDL current generation while maintaining an acceptable driving current for the memory cells. The high-low source/drain doping scheme can form two regions in the source/drain: a first region having a deep junction profile and a lower doping concentration, which serves to reduce the electric field in the source/drain and well diode region, and a second region having a shallow junction profile and a higher doping concentration for improving the contact and series resistances so as to maintain the drive current and breakdown voltage.

FIG. 1 illustrates a schematic diagram of an exemplary memory device 100 having a memory cell array 101 and peripheral circuits 102, according to some aspects of the present disclosure. Memory device 100 can include memory cell array 101 and peripheral circuits 102 coupled to memory cell array 101. Memory cell array 101 can be any suitable memory cell array in which each memory cell 108 can be a NAND Flash memory cell, a NOR Flash memory cell, a PCM cell, a ferroelectric memory cell, a dynamic random-access memory (DRAM) cell, a static random access memory (SRAM) cell, a resistive memory cell, a magnetic memory cell array, a spin transfer torque (STT) memory cell array, to name a few, or any combination thereof. As shown in FIG. 1, memory cells 108 can be arranged in a two-dimensional (2D) array having rows and columns. Memory device 100 can include word lines 104 coupling peripheral circuits 102 and memory cell array 101 for controlling memory cells 108 located in a same row, as well as bit lines 106 coupling peripheral circuits 102 and memory cell array 101 for controlling memory cells 108 located in a same column. That is, each word line 104 is coupled to a respective row of memory cells 108, and each bit line is coupled to a respective column of memory cells 108.

Peripheral circuits 102 (a.k.a., control and sensing circuits) can include any suitable digital, analog, and/or mixed-signal circuits used for facilitating the operations of memory cell array 101. For example, peripheral circuits 102 can include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder) , a sense amplifier, a driver (e.g., a word line driver or a bit line driver) , an I/O circuit, a charge pump, a current or voltage reference, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors) . Peripheral circuits 102 can include various types of peripheral circuits formed using MOS technologies. For example, FIG. 2 illustrates some exemplary peripheral circuits 102 including a page buffer 204, a column decoder/bit line driver 206, a row decoder/word line driver 208, a voltage generator 210, control logic 212, registers 214, an interface (I/F) 216, and a data bus 218. It is understood that in some examples, additional peripheral circuits 102 may be included as well.

Page buffer 204 can be configured to buffer data read from or written to memory cell array 101 according to the control signals of control logic 212. Row decoder/word line driver 208 can be configured to drive memory cell array 101. For example, row decoder/word line driver 208 may drive memory cells 108 coupled to selected word line 104 using a word line voltage generated from voltage generator 210. Column decoder/bit line driver 206 can be configured to be controlled by control logic 212 and select one or more columns of memory cells 108 by applying bit line voltages generated from voltage generator 210. For example, column decoder/bit line driver 206 may apply column signals for selecting a set of pieces of data from page buffer 204 to be outputted in a read operation.

Control logic 212 can be coupled to each peripheral circuit 102 and configured to control operations of peripheral circuits 102. Registers 214 can be coupled to control logic 212 and include status registers, command registers, and address registers for storing status information, command operation codes (OP codes) , and command addresses for controlling the operations of each peripheral circuit 102.

Interface 216 can be coupled to control logic 212 and configured to interface memory cell array 101 with a memory controller (not shown) . In some implementations, interface 216 acts as a control buffer to buffer and relay control commands received from the memory controller and/or a host (not shown) to control logic 212 and status information received from control logic 212 to the memory controller and/or the host. Interface 216 can also be coupled to page buffer 204 and column decoder/bit line driver 206 via a data bus 218 and act as an I/O interface and a data buffer to buffer and relay the write data received from the memory controller and/or the host to page buffer 204 and the read data from page buffer 204 to the memory controller and/or the host. In some implementations, interface 216 and data bus 218 are parts of an I/O circuit of peripheral circuits 102.

Voltage generator 210 can be configured to be controlled by control logic 212 and generate the word line voltages (e.g., read voltage, write voltage, etc. ) and the bit line voltages to be supplied to memory cell array 101. In some implementations, voltage generator 210 is part of a voltage source that provides voltages at various levels of different peripheral circuits 102 as described below in detail. Consistent with the scope of the present disclosure, in some implementations, the voltages provided by voltage generator 210, for example, to row decoder/word line driver 208, column decoder/bit line driver 206, and page buffer 204 are above certain levels that are sufficient to perform the memory operations. For example, the voltages provided to the page buffer circuits in page buffer 204 and/or the logic circuits in control logic 212 may be between 1.3 V and 5 V, such as 3.3 V, and the voltages provided to the driving circuits in row decoder/word line driver 208 and/or column decoder/bit line driver 206 may be between 5 V and 30 V.

Different from logic devices (e.g., microprocessors) , memory devices, such as NAND or NOR Flash memory, require a wide range of voltages to be supplied to different memory peripheral circuits. For example, FIG. 3 illustrates a block diagram of peripheral circuits provided with various voltages, according to some aspects of the present disclosure. In some implementations, a memory device (e.g., memory device 100) includes a low low voltage (LLV) source 301, a low voltage (LV) source 303, and a high voltage (HV) source 305, each of which is configured to provide a voltage at a respective level (Vdd1, Vdd2, or Vdd3) . For example, Vdd3 >Vdd2 > Vdd1. Each

voltage source

301, 303, or 305 can receive a voltage input at a suitable level from an external power source (e.g., a battery) . Each

voltage source

301, 303, or 305 can also include voltage converters and/or voltage regulators to convert the external voltage input to the respective level (Vdd1, Vdd2, or Vdd3) and maintain and output the voltage at the respective level (Vdd1, Vdd2, or Vdd3) through a corresponding power rail. In some implementations, voltage generator 210 of memory device 100 is part of

voltage sources

301, 303, and 305.

In some implementations, LLV source 301 is configured to provide a voltage below 1.3 V, such as between 0.9 V and 1.2 V (e.g., 0.9 V, 0.95 V, 1 V, 1.05 V, 1.1 V, 1.15 V, 1.2 V, any range bounded by the lower end by any of these values, or in any range defined by any two of these values) . In one example, the voltage is 1.2 V. In some implementations, LV source 303 is configured to provide a voltage between 1.3 V and 3.3 V (e.g., 1.3 V, 0.1.4 V, 1.5 V, 1.6 V, 1.7 V, 1.8 V, 1.9 V, 2 V, 2.1 V, 2.2 V, 2.3 V, 2.4 V, 2.5 V, 2.6 V, 2.7 V, 2.8 V, 2.9 V, 3 V, 3.1 V, 3.2 V, 3.3 V, any range bounded by the lower end by any of these values, or in any range defined by any two of these values) . In one example, the voltage is 3.3 V. In some implementations, HV source 305 is configured to provide a voltage greater than 3.3 V, such as between 5 V and 30 V (e.g., 5 V, 6 V, 7 V, 8 V, 9 V, 10 V, 11 V, 12 V, 13 V, 14 V, 15 V, 16 V, 17 V, 18 V, 19 V, 20 V, 21 V, 22 V, 23 V, 24 V, 25 V, 26 V, 27 V, 28 V, 29 V, 30 V, any range bounded by the lower end by any of these values, or in any range defined by any two of these values) . It is understood that the voltage ranges described above with respect to HV source 305, LV source 303, and LLV source 301 are for illustrative purposes and non-limiting, and any other suitable voltage ranges may be provided by HV source 305, LV source 303, and LLV source 301.

Based on their suitable voltage levels (Vdd1, Vdd 2, or Vdd3) , the memory peripheral circuits (e.g., peripheral circuits 102) can be categorized into LLV circuits 302, LV circuits 304, and HV circuits 306, which can be coupled to LLV source 301, LV source 303, and HV source 305, respectively. In some implementations, HV circuits 306 includes one or more driving circuits that are coupled to memory cell array 101 through word lines104 and bit lines 106 and configured to drive memory cell array 101 by applying a voltage at a suitable level to word lines104 and bit lines 106, when performing memory operations (e.g., read, write, or erase) . In one example, HV circuit 306 may include word line driving circuits (e.g., in row decoder/word line driver 208) that are coupled to word lines 104 and apply a write voltage in the range of, for example, 5 V and 30 V, to word lines 104 during write operations. In another example, HV circuit 306 may include bit line driving circuits (e.g., in column decoder/bit line driver 206) that are coupled to bit lines 106 and apply an erase voltage in the range of, for example, 5 V and 30 V, to bit lines 106 during erase operations. In some implementations, LV circuits 304 include page buffer circuits (e.g., in latches of page buffer 204) and are configured to buffer the data read from or written to memory cell array 101. For example, page buffer 204 may be provided with a voltage of, for example, 3.3 V, by LV source 303. LV circuits 304 can also include logic circuits (e.g., in control logic 212) . In some implementations, LLV circuits 302 include an I/O circuit (e.g., in interface 216 and/or data bus 218) configured to interface memory cell array 101 with a memory controller. For example, the I/O circuit may be provided with a voltage of, for example, 1.2 V, by LLV source 301.

Consistent with the scope of the present disclosure, in some implementations, HV circuits 306, such as driving circuits in row decoder/word line driver 208 and column decoder/bit line driver 206, have recessed channel transistors instead of planar transistors in order to shrink the device size while maintaining the comparable or even better device leakage performance. LLV circuits 302, such as I/O circuits in interface 216 and data bus 218, can still have planar transistors, because planar transistors can provide a higher operation speed than the recessed channel transistors, which is a desired feature for the I/O circuit that needs to frequently communicate with external devices. LV circuits 304, such as page buffer circuits in page buffer 204 and logic circuits in control logic 212, can have recessed channel transistors, planar transistors, or a combination thereof. For example, FIG. 4 illustrates a plan view and a side view of cross-sections of an exemplary planar transistor, according to some aspects of the present disclosure, and FIG. 5 illustrates a plan view and a side view of cross-sections of an exemplary recessed channel transistor, according to some aspects of the present disclosure.

As shown in FIG. 4, for a planar transistor, the effective channel length Leff is the same as the gate length L, whereas in FIG. 5, for a recessed channel transistor, the effective channel length Leff = Lb + 2Ld –2xj, where Lb represents the gate length at the bottom of the gate structure protruding into the substrate, Ld represents the depth of the gate structure protruding into the substrate (considering the slope for better accuracy if the slope is not 90 degrees) , and xj represents the junction depth of the source/drain. For a planar transistor, the reduction of device area can be achieved by reducing the gate length L (and also gate width W in some cases) , which in turn reduces the effective channel length. As a result, channel leakage can be degraded. In contrast, for a recessed channel transistor, the reduction of the device area (e.g., by reducing the gate length L) may not reduce the effective channel length Leff due to the addition of Ld. Moreover, better gate control can be realized due to the protrusion shape of the recess gate structure and the resulting U-shaped channel. Thus, the device area can be reduced while keeping comparable or even better device leakage performance.

However, comparing FIGs. 4 and 5, the protrusion shape of the recess gate structure into the substrate in the recessed gate transistor can cause an extended gate diode D (i.e., a junction between the source/drain and the well with different types of dopants) to form under the gate structure. In other words, a depletion region can be formed at the gate to source/drain overlapping area where the source/drain is in contact with the bent gate dielectric of the recess gate structure. A high electric field can be formed in the depletion region, thereby generating a high GIDL leakage current, which is a main component of the leakage current of a recessed channel transistor in HV circuit 306. To weaken the GIDL effect at the extended gate diode D of a recessed channel transistor, in particular in HV circuits 306, and reduce the resulting GIDL leakage current, various recessed

channel transistors

601, 603, and 605 with improved designs are provided and described below in FIGs. 6A–6C.

As shown in FIG. 6A, a semiconductor device 600 can include recessed channel transistor 601 on a substrate 602, which can include silicon (e.g., single crystalline silicon, c-Si) , silicon germanium (SiGe) , gallium arsenide (GaAs) , germanium (Ge) , silicon on insulator (SOI) , or any other suitable materials. Semiconductor device 600 can also include isolations 606, such as shallow trench isolations (STI) , in substrate 602 and between adjacent recessed channel transistors 601 to reduce current leakage. As shown in FIG. 6A, the top surface of isolations 606 can be coplanar with the top surface of substrate 602. Isolations 606 can include any suitable dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, or high dielectric constant (high-k) dielectrics (e.g., aluminum oxide, hafnium oxide, zirconium oxide, etc. ) . In some implementations, high-k dielectric materials include any dielectrics having a dielectric constant, or k-value, higher than that of silicon nitride (k > 7) . In some implementations, isolation 606 includes silicon oxide.

It is noted that x-and y-axes are added in FIG. 6A to further illustrate the spatial relationship of the components in semiconductor device 600. Substrate 602 includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x-direction (the lateral direction or width direction) . As used herein, whether one component (e.g., a layer or a device) is “on, ” “above, ” or “below” another component (e.g., a layer or a device) of a semiconductor device (e.g., semiconductor device 600) is determined relative to the substrate of the semiconductor device (e.g., substrate 602) in the y-direction (the vertical direction or thickness direction) when the substrate is positioned in the lowest plane of the semiconductor device in the y-direction. The same notion for describing the spatial relationship is applied throughout the present disclosure.

As shown in FIG. 6A, in some implementations, recessed channel transistors recessed channel transistor 601 can include a well 604 in substrate 602 and having a recess. Well 604 can be doped with any suitable P-type dopants, such as boron (B) or gallium (Ga) , or any suitable N-type dopants, such as phosphorus (P) or arsenic (As) . It is understood that well 604 in FIG. 6A is for illustrative purposes only. Depending on the doping type of substrate 602, well 604 may be omitted or have different ranges and limits in substrate 602. Recessed channel transistor 601 can further include a recess gate structure 608 protruding into the recess of well 604 in substrate 602. That is, recess gate structure 608 can have two portions in the side view: a protruding portion below the top surface of substrate 602 and a flat portion above the top surface of substrate 602. As described above with respect to FIG. 5, the depth and slope of the protruding portion of recess gate structure 608 determine Ld, which in turn affects the effective channel length Leff of recessed channel transistor 601. In some implementations, the depth of the protruding portion of recess gate structure 608, i.e., the depth in which recess gate structure 608 protrudes into substrate 601, is between 50 nm and 100 nm (e.g., 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, any range bounded by the lower end by any of these values, or in any range defined by any two of these values) .

In some implementations, recess gate structure 608 includes a bent gate dielectric 610 and a recess gate electrode 612 on bent gate dielectric 610. As shown in FIG. 6A, a recess is formed in a region of substrate 602 in which recessed channel transistor 601 is formed, according to some implementations. The recess can be surrounded by well 604. That is, part of substrate 602 in which well 604 is formed can be removed from the top surface to form a recess, as described below in detail with respect to the fabrication process. In some implementations, the depth of the recess is the same as the depth of the protruding portion of recess gate structure 608 and is between 50 nm and 100 nm (e.g., 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, any range bounded by the lower end by any of these values, or in any range defined by any two of these values) .

Bent gate dielectric 610 can be formed on the sidewall and the bottom surface of the recess. As a result, bent gate dielectric 610 has a bent shape in the side view, following the sidewall and bottom shape of the recess, according to some implementations. Bent gate dielectric 610 can include any suitable dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectrics. In some implementations, bent gate dielectric 610 includes silicon oxide, i.e., a bent gate oxide. Recess gate electrode 612 is above and in contact with bent gate dielectric 610, according to some implementations. As shown in FIG. 6A, recess gate electrode 612 can include two portions in the side view as well: a protruding portion below the top surface of substrate 602 and a flat portion above the top surface of substrate 602. That is, the recess in substrate 602 can be filled with bent gate dielectric 610 and the protruding portion of recess gate electrode 612. Recess gate electrode 612 can include any suitable conductive materials, such as doped polysilicon, metals (e.g., tungsten, copper, aluminum, etc. ) , metal compounds (e.g., titanium nitride, tantalum nitride, etc. ) , or silicides. In some implementations, recess gate electrode 612 includes doped polysilicon, i.e., a recess gate poly.

In some implementations, recessed channel transistor 601 further includes a spacer structure 614 on the sidewall of the flat portion of recess gate electrode 612, i.e., the part that is above substrate 602. That is, the sidewall of spacer structure 614 can be in contact with the sidewall of recess gate electrode 612. As shown in FIG. 6A, spacer structure 614 is also formed on the top surface of substrate 602, according to some implementations. That is, the bottom surface of spacer structure 614 can be coplanar with the top surface of substrate 602 as well as the top surface of isolation 606. Thus, the bottom surface of spacer structure 614, the top surface of isolations 606, and the top surface of substrate 602 may refer to herein the same plane. In some implementations, spacer structure 614 includes an inner spacer 616 in contact with the sidewall of recess gate electrode 612, and an outer spacer 618 in contact with the sidewall of inner spacer 616. That is, spacer structure 614 can include multiple spacers (e.g., inner and outer spacers 616 and 618) disposed laterally.

Spacers

616 and 618 can include any suitable dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectrics. In some implementations, outer spacer 618 has a different material from inner spacer 616. In one example, inner spacer 616 includes silicon oxide, and outer spacer 618 includes silicon nitride. In another example, inner spacer 616 includes silicon nitride, and outer spacer 618 includes silicon oxide. It is understood that in some examples, spacer structure 614 may include a single spacer or more than two spacers.

Recessed channel transistor 601 can further include a pair of a source 620 and a drain 620 (also referred to herein source/drain 620) spaced apart by spacer structure 614 and recess gate structure 608. Source and drain 620 can be doped with any suitable P-type dopants, such as B or Ga, or any suitable N-type dopants, such as P or Ar. The dopant type of source/drain 620 can be different from the dopant type of well 604. As shown in FIG. 6A, the top surface of source/drain 620 is elevated from the bottom surface of spacer structure 614 (i.e., the top surface of substrate 602) . That is, different from the conventional flat source/drain, source/drain 620 of recess channel transistor 601 is an elevated source/drain having an elevated portion 622 above the bottom surface of spacer structure 614 (i.e., the top surface of substrate 602) as well as a flat portion 624 below the bottom surface of spacer structure 614 (i.e., the top surface of substrate 602) , according to some implementations. For example, elevation portion 622 of source/drain 620 may be above the bottom surface of spacer structure 614 and in contact with the sidewall of spacer structure 614. However, as shown in FIG. 6A, elevation portion 622 of source/drain 620 does not extend to cover isolation 606, according to some implementations. That is, elevation portion 622 can be self-aligned between isolations 606 and spacer structures 614 using selective epitaxy growth as described below in detail with respect to the fabrication processes.

In some implementations, elevated portion 622 has the same material as substrate 602, such as single crystalline silicon when substrate 602 is a silicon substrate. As parts of source/drain 620, elevated portion 622 and flat portion 624 can be doped with the same type of dopants, either at the same or different doping concentrations. The depth of elevation portion 622 (i.e., the depth between the top surface of source/drain 620 and the bottom surface of spacer structure 614) is not less than 100 nm. In some implementations, the depth is between 100 nm and 150 nm (e.g., 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, any range bounded by the lower end by any of these values, or in any range defined by any two of these values) . As shown in FIG. 6A, in some implementation, recess gate structure 608 protrudes below source/drain 620. That is, the lower end of recess gate structure 608 can be lower than the lower ends of flat portion 624 of source/drain 620.

By elevating the top surface of source/drain 620 above the top surface of substrate 602, the gate to source/drain overlapping area (i.e., the extended gated diode) can be reduced (compared with FIG. 5) , which in turn reduces the electric field of the depletion area. As a result, the GIDL leakage current can be reduced by forming elevation portion 622 of elevated source/drain 620 in recessed channel transistor 601 without reducing the driving current (Ids) . Moreover, by elevating the top surface of source/drain 620 above the top surface of substrate 602, the gate length Lb of recess gate structure 608 can be further reduced while maintaining the same effective channel length Leff of recessed channel transistor 601 as described above with respect to FIG. 5.

It is understood that recessed channel transistor 601 may include or be coupled with additional components not shown in FIG. 6A, for example, additional dielectric layers or contacts (e.g., source and drain contacts) .

Another way to reduce the electric field at the depletion area, which causes the GIDL leakage current, is to reduce the doping concentration of the part of the source/drain that overlaps the gate structure (e.g., the gate dielectric) . For example, FIG. 6B shows another recessed channel transistor 603. Different from recessed channel transistor 601 in FIG. 6A, recessed channel transistor 603 in FIG. 6B includes flat source/drain 626 each including two

regions

628 and 630 with different doping concentrations. The same components of recessed

channel transistors

603 and 601 are not described below again for ease of description.

Recessed channel transistor 603 can include a source 626 and a drain 626 (also referred to herein as source/drain 626) spaced apart by recess gate structure 608. Source/drain 626 is a flat source/drain, i.e., the top surface of which is coplanar with the bottom surface of spacer structure 614 (the top surface of substrate 602) , according to some implementations. As shown in FIG. 6B, source/drain 626 can include a low-doping region 628 in contact with bent gate dielectric 610 of recess gate structure 608, and a high-doping region 630 having a doping concentration higher than low-doping region 628. The difference of doping concentrations between high-doping and low-doping

regions

630 and 628 of source/drain 626 is at least 10-fold, according to some implementations. In some implementations, the doping concentration of low-doping region 628 is between 10 ¹⁸/cm ³ and 10 ¹⁹/cm ³ (e.g., 10 ¹⁸/cm ³, 2×10 ¹⁸/cm ³, 3×10 ¹⁸/cm ³, 4×10 ¹⁸/cm ³, 5×10 ¹⁸/cm ³, 6×10 ¹⁸/cm ³, 7×10 ¹⁸/cm ³, 8×10 ¹⁸/cm ³, 9×10 ¹⁸/cm ³, 10 ¹⁹/cm ³, any range bounded by the lower end by any of these values, or in any range defined by any two of these values) . In some implementations, the doping concentration of high-doping region 630 is at least 10 ²⁰/cm ³, such as between 10 ²⁰/cm ³ and 10 ²¹/cm ³ (e.g., 10 ²⁰/cm ³, 2×10 ²⁰/cm ³, 3×10 ²⁰/cm ³, 4×10 ²⁰/cm ³, 5×10 ²⁰/cm ³, 6×10 ²⁰/cm ³, 7×10 ²⁰/cm ³, 8×10 ²⁰/cm ³, 9×10 ²⁰/cm ³, 10 ²¹/cm ³, any range bounded by the lower end by any of these values, or in any range defined by any two of these values) .

As shown in FIG. 6B, besides the different doping concentrations, high-doping and low-doping

regions

630 and 628 of source/drain 626 can also have different junction profiles. For example, FIG. 7A illustrates an exemplary source/drain junction profile of recessed channel transistor 603 in FIG. 6B, according to some aspects of the present disclosure. In some implementations, low-doping region 628 has a deep junction profile, while high-doping region 630 has a shallow junction profile. For example, the thickness (measured from the top surface of substrate 602) of low-doping region 628 is greater than the thickness of high-doping region 630. In some implementations, the thickness of low-doping region 628 is greater than 200 nm. For example, the thickness of low-doping region 628 may be between 200 nm and 400 nm (e.g., 200 nm, 210 nm, 220 nm, 230 nm, 240 nm, 250 nm, 260 nm, 270 nm, 280 nm, 290 nm, 300 nm, 310 nm, 320 nm, 330 nm, 340 nm, 350 nm, 360 nm, 370 nm, 380 nm, 390 nm, 400 nm, any range bounded by the lower end by any of these values, or in any range defined by any two of these values) . In some implementations, the thickness of high-doping region 630 is less than 100 nm. For example, the thickness of high-doping region 630 may be between 50 nm and 100 nm (e.g., 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, any range bounded by the lower end by any of these values, or in any range defined by any two of these values) .

As shown in FIGs. 6B and 7A, the deep junction profile of low-doping region 628 can ensure that low-doping region 628 of source/drain 626 with a relatively low doping concentration is in contact with bent gate dielectric 610, such that the doping concentration at the depletion region of the extended gated diode is relatively low. As a result, the electric field and the resulting GIDL leakage current can be reduced. On the other side, the shallow junction profile of high-doping region 630 can ensure that high-doping region 630 of source/drain 626 with a relatively high doping concentration is spaced apart from bent gate dielectric 610 to minimize the contribution of the high doping concentration to the electric field at the depletion region. Moreover, high-doping region 630 can be formed at the top surface of substrate 602 such that the source/drain contact (not shown) of recessed channel transistor 603 can be in contact with high-doping region 630, as opposed to low-doping region 628. As a result, the contact resistance between the source/drain contact and source/drain 626 as well as the series resistance of source/drain 626 can be maintained while reducing the doping concentration at the depletion region of the extended gated diode. Accordingly, the driving current and breakdown voltage of recessed channel transistor 603 can be maintained while reducing the GIDL leakage current. As described below in detail with respect to the fabrication processed, the formation of high-doping and low-doping

regions

630 and 628 in source/drain 626 can be achieved by a high-low doping scheme.

It is understood that in some examples, elevated source/drain of a recessed channel transistor can also have high-doping and low-doping regions to further reduce the GIDL effect at the extended gate diode. For example, FIG. 6C shows a recessed channel transistor 605 having elevated source/drain 632 each including elevation portion 622 and a flat portion 634. Different from elevated source/drain 620 of recessed channel transistor 601 in FIG. 6A, which has the same doping concentration in elevation portion 622 and flat portion 624, flat portion 634 of elevated source/drain 632 of recessed channel transistor 605 in FIG. 6C that is in contact with bent gate dielectric 610 of recess gate structure 608 can have a relatively low doping concentration (similar to low-doping region 628 in FIG. 6B) to further reduce the GIDL effect at the depletion region of the extended gated diode. The same components of recessed

channel transistors

605, 603, and 601 are not described below again for ease of description.

In some implementations, the doping concentration of elevated portion 622 is higher than the doping concentration of flat portion 634 of source/drain 632. It is understood that the high-doping region 630 and low-doping region 628 may not match exactly with elevation portion 622 and flat portion 634, respectively. For example, as shown in FIG. 7B, high-doping region 630 may extend beyond elevation portion 622 into flat portion 634. That is, elevation portion 622 may be fully filled with high-doping region 630, and flat portion 634 may include low-doping region 628 and part of high-doping region 630. Although not shown, it is also understood that in some examples, high-doping region 630 may not fully fill elevation portion 622, such that elevation portion 622 may include high-doping region 630 and part of low-doping region 628, while flat portion 634 may be fully filled with low-doping region 628. Nevertheless, high-doping region 630 is in at least elevation portion 622 of source/drain 632, according to some implementations.

Consistent with the scope of the present disclosure, recessed channel transistors and planar transistors can be used together in memory peripheral circuits, for example, for different peripheral circuits working at different voltages (e.g., HV circuits 306, LV circuits 304, and LLV circuits 302) . For example, FIG. 8 illustrates a side view of a cross-section of an exemplary semiconductor device 800 having recessed channel transistors 802 and planar transistors 804, according to some aspects of the present disclosure. Semiconductor device 800 can include memory peripheral circuits disclosed herein (e.g., peripheral circuits 102) . In some implementations, recessed channel transistors 802 are parts of HV circuits 306 (e.g., driving circuits) , and planar transistors 804 are parts of LLV circuits 302 (e.g., I/O circuits) . It is understood that LV circuits 304 (e.g., page buffer circuits and logic circuits) may include recessed channel transistors 802, planar transistors 804, or any combination thereof. It is also understood that semiconductor device 800 is not limited to peripheral circuits of a memory device and may include any semiconductor device that includes a mixed type of recessed channel transistors 802 and planar transistors 804.

Each recessed channel transistor 802 or planar transistor 804 can be a MOS field-effect-transistor (MOSFET) on a substrate 801, which can include silicon (e.g., single crystalline silicon, c-Si) , SiGe, GaAs, Ge, SOI, or any other suitable materials. Semiconductor device 800 can include isolations 803, such as STI, in substrate 801 and between adjacent recessed channel transistors 802 and planar transistors 804 to reduce current leakage. As shown in FIG. 8, in some implementations, recessed channel transistors 802 and planar transistors 804 are formed by complementary MOS (CMOS) technology and include pairs of adjacent P-type transistors (e.g., PMOS) and N-type transistors (NMOS) .

A P-type recessed channel transistor 806 can include an N-well 814 in substrate 801 and having a recess, and an N-type recessed channel transistor 807 can include a P-well 815 in substrate 801 and having a recess. P-well 815 can be doped with any suitable P-type dopants, such as B or Ga, and N-well 814 can be doped with any suitable N-type dopants, such as P or As. It is understood that

wells

814 and 815 in FIG. 8 are for illustrative purposes only. Depending on the doping type of substrate 801, N-well 814 or P-well 815 may be omitted or have different ranges and limits in substrate 801. Each recessed channel transistor 802 can further include a recess gate structure 819 protruding into the recess of well 814 or 815 in substrate 801. For example, recess gate structure 819 of P-type recessed channel transistor 806 may protrude into the recess of N-well 814, and recess gate structure 819 of N-type recessed channel transistor 807 may protrude into the recess of P-well 815.

In some implementations, recess gate structure 819 includes a bent gate dielectric 818 and a recess gate electrode 816 on bent gate dielectric 818. As shown in FIG. 8, recesses are formed in a region of substrate 801 in which recessed channel transistors 802 are formed, according to some implementations. Each recess can be surrounded by N-well 814 or P-well 815. Bent gate dielectric 818 can be formed on the sidewall and the bottom surface of each recess. As a result, bent gate dielectric 818 has a bent shape in the side view, following the sidewall and bottom shape of the recess, according to some implementations. In some implementations, bent gate dielectric 818 includes silicon oxide, i.e., a bent gate oxide. Recess gate electrode 816 is above and in contact with bent gate dielectric 818, according to some implementations. As shown in FIG. 8, recess gate electrode 816 can include two portions in the side view as well: a protruding portion below the top surface of substrate 801 and a flat portion above the top surface of substrate 801. In some implementations, recess gate electrode 816 includes doped polysilicon, i.e., a recess gate poly.

In some implementations, each recessed channel transistor 802 further includes spacer structures 820 on the sidewall of the flat portion of recess gate electrode 816, i.e., the part that is above substrate 801. Spacer structures 820 can include any suitable dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectrics. In some implementations, each spacer structure 820 includes multiple spacers, such as an inner spacer and an outer spacer having different dielectric materials.

As shown in FIG. 8, each recessed channel transistor 802 can further include a pair of a source and a drain spaced apart by recess gate structure 819 and spacer structure 820. For example, P-type recessed channel transistor 806 may include a P-type source 832 and a P-type drain 832 in N-well 814. Similarly, N-type recessed channel transistor 807 may include an N-type source 833 and an N-type drain 833 in P-well 815. P-type source and drain 832 can be doped with any suitable P-type dopants, such as B or Ga, and N-type source and drain 833 can be doped with any suitable N-type dopants, such as P or Ar. Consistent with the scope of the present disclosure, source/

drain

832 or 833 of recessed channel transistors 802 can be elevated source/drain 620, flat source/drain 626 with high-doping and low-doping regions, elevated source/drain 632 with high-doping and low-doping regions, or any combination thereof, as described above in detail with respect to FIGs. 6A–6C. As a result, the GILD leakage current of recessed channel transistor 802 can be reduced while maintaining the driving current and breakdown voltage.

It is understood that additional details of recessed channel transistor 802 may be described above with respect to counterparts of recessed

channel transistors

601, 603, and 605 in FIGs. 6A–6C and thus, are not repeated for ease of description. It is also understood that each recessed channel transistor 802 may include or be coupled with additional components not shown in FIG. 8, for example, additional dielectric layers or contacts (e.g., source and drain contacts) .

As shown in FIG. 8, a P-type planar transistor 808 can include an N-well 822 in substrate 801, and an N-type planar transistor 809 can include a P-well 823 in substrate 801. N-well 822 can be doped with any suitable N-type dopants, such as P or Ar, and P-well 823 can be doped with any suitable P-type dopants, such as B or Ga. It is understood that

wells

822 and 823 in FIG. 8 are for illustrative purposes only. Depending on the doping type of substrate 801, N-well 822 or P-well 823 may be omitted or have different ranges and limits in substrate 801. Each planar transistor 804 can further include a flat gate structure 827. Different from recess gate structure 819, flat gate structure 827 does not protrude into substrate 801, according to some implementations. In some implementations, due to the existence of the protruding portion of recess gate structure 819, the depth of well 814 or 815 in recessed channel transistor 802 is greater than the depth of well 822 or 823 in planar transistor 804.

In some implementations, flat gate structure 827 includes a flat gate dielectric 826 and a flat gate electrode 824 on bent gate dielectric 818. Different from recessed channel transistors 802, recesses are not formed in a region of substrate 801 in which planar transistors 804 are formed, according to some implementations. Thus, flat gate dielectric 826 can be formed on the top surface of substrate 801. As a result, flat gate dielectric 826 has a straight shape in the side view, according to some implementations. Flat gate dielectric 826 can include any suitable dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectrics. In some implementations, flat gate dielectric 826 includes silicon oxide, i.e., a flat gate oxide. Flat gate electrode 824 is above and in contact with flat gate dielectric 826, according to some implementations. Different from recessed channel transistors 802, the entirety of flat gate electrode 824 can be above the top surface of substrate 801. Flat gate electrode 824 can include any suitable conductive materials, such as polysilicon, metals, metal compounds, or silicides. In some implementations, flat gate electrode 824 includes doped polysilicon, i.e., a flat gate poly.

As shown in FIG. 8, each planar transistor 804 can further include a pair of a source and a drain in well 822 or 823. For example, P-type planar transistor 808 may include a P-type source 830 and a P-type drain 830 in N-well 822, and N-type planar transistor 809 may include an N-type source 831 and an N-type drain 831 in P-well 823. P-type source and drain 830 can be doped with any suitable P-type dopants, such as B or Ga, and N-type source and drain 831 can be doped with any suitable N-type dopants, such as P or Ar. In some implementations, the doping concentration of source/

drain

832 or 833 in recessed channel transistor 802 is different from the doping concentration of source/

drain

830 or 831 in planar transistor 804, such that the threshold voltage of recessed channel transistor 802 is different from the threshold voltage of planar transistor 804. For example, the doping concentration of source/

drain

832 or 833 in recessed channel transistor 802 and the doping concentration of source/

drain

830 or 831 in planar transistor 804 may be controlled in a manner such that the threshold voltage of planar transistor 804 is greater than the threshold voltage of recessed channel transistor 802. In some implementation, source/drain 830 of planar transistor 804 is flat source/drain, such that the top surface of source/drain 830 is coplanar with the top surface of substrate 801.

In some implementations, each planar transistor 804 further includes spacer structure 828 on the sidewall of flat gate electrode 824. Spacer structures 828 can include any suitable dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectrics. In some implementations, spacer structures 828 include silicon nitride. It is understood that each planar transistor 804 may include or be coupled with additional components not shown in FIG. 8, for example, additional dielectric layers or contacts (e.g., source and drain contacts) .

As described above, recessed channel transistors 802 and planar transistors 804 can be used to form different peripheral circuits working at different voltages. In some implementations, recessed channel transistors 802 are coupled to a voltage source of greater than 3.3 V, such as between 5 V and 30 V. In some implementations, planar transistors 804 are coupled to a voltage source of not greater than 3.3 V, such as between 1.2 V and 3.3 V. Due to the different working voltages, besides the different gate structures, other designs of recessed channel transistors 802 and planar transistors 804 may vary as well. In some implementations, the thickness of bent gate dielectric 818 of recessed channel transistor 802 is greater than the thickness of flat gate dielectric 826 of planar transistor 804 in order to sustain a higher gate voltage. In some implementations, the lateral dimension (e.g., in the x-direction) of spacer structure 820 of recessed channel transistor 802 is greater than the lateral dimension of spacer structure 828 of planar transistor 804 in order to prevent source/drain punch, leakage, and reliability issues at a higher gate voltage. For example, spacer structure 820 of recessed channel transistor 802 may include multiple spacers (e.g., inner and

outer spacers

616 and 618 in FIGs. 6A–6C) , while spacer structure 828 of planar transistor 804 may include a single spacer (e.g., inner spacer 616 only without outer spacer 618) . As described below in detail with respect to the fabrication processes, spacer structure 828 of planar transistor 804 includes an inner spacer having the same material as the inner spacer of spacer structure 820 of recessed channel transistor 802, but does not include an outer spacer (which is included in spacer structure 820) , according to some implementations.

FIGs. 9A–9K illustrate a fabrication process for forming an exemplary semiconductor device having recessed channel transistors and planar transistors, according to some aspects of the present disclosure. FIG. 10 illustrates a flowchart of an exemplary method 1000 for forming a semiconductor device having recessed channel transistors and planar transistors, according to some aspects of the present disclosure. FIG. 11 illustrates a flowchart of another exemplary method 1100 for forming a semiconductor device having recessed channel transistors and planar transistors, according to some aspects of the present disclosure. Examples of the semiconductor device depicted in FIGs. 9A–9K, 10, and 11 include

semiconductor devices

600 and 800 depicted in FIGs. 6A–6C and 8. FIGs. 9A–9K, 10, and 11 will be described together. It is understood that the operations shown in

methods

1000 and 1100 are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in FIGs. 10 and 11.

Referring to FIG. 10, method 1000 starts at operation 1002, in which a first well is formed in a substrate. The substrate can be a silicon substrate. As illustrated in FIG. 9A, a plurality of isolations 902, such as STIs, are formed in a silicon substrate 900, for example, using wet/dry etch and thin film deposition of silicon oxide. Isolations 902 can divide silicon substrates 900 into multiple regions in which multiple transistors can be formed, respectively. As illustrated in FIG. 9A, an N-well 904 and a P-well 906 are subsequently formed in silicon substrate 900. In some implementations, N-well 904 and P-well 906 are formed in regions for forming planar transistors. N-well 904 and P-well 906 can be patterned and aligned between isolation 902 using lithography, followed by ion implantation of respective N-type dopants and P-type dopants.

Method 1000 proceeds to operation 1004, as illustrated in FIG. 10, in which a second well is formed in the substrate. In some implementations, the depth of the second well is greater than the depth of the first well. As illustrated in FIG. 9B, an N-well 910 is formed in silicon substrate 900. N-well 910 may be part of a P-type recessed channel transistor and thus, may be formed in a region for forming the P-type recessed channel transistor. To form N-well 910, in some implementations, a mask layer 908 is formed on silicon substrate 900 and then patterned to expose the region in which N-well 910 is to be formed. Mask layer 908 can include a soft mask layer, such as a photoresist layer, and/or a hard mask layer, such as a silicon oxide layer. Mask layer 908 can be patterned and aligned between isolations 902 using lithography and wet/dry etch. Ion implantation of N-type dopants, such as P or As, can be performed with mask layer 908 to form N-well 910 into the desired region between isolations 902. In some implementations, the conditions of ion implantation for N-well 904, P-well 906, and N-well 910 are controlled, such that the depth of N-well 910 is greater than the depth of N-well 904 and P-well 906.

As illustrated in FIG. 9C, a P-well 912 is formed in silicon substrate 900. P-well 912 may be part of an N-type recessed channel transistor and thus, may be formed in a region for forming the N-type recessed channel transistor. To form P-well 912, in some implementations, a mask layer 909 is formed on silicon substrate 900 and then patterned to expose the region in which P-well 912 is to be formed. Mask layer 909 can include a soft mask layer, such as a photoresist layer, and/or a hard mask layer, such as a silicon oxide layer. Mask layer 909 can be patterned and aligned between isolations 902 using lithography and wet/dry etch. Ion implantation of P-type dopants, such as B or Ga, can be performed with mask layer 909 to form P-well 912 into the desired region between isolations 902. In some implementations, the conditions of ion implantation for N-well 904, P-well 906, and P-well 912 are controlled, such that the depth of P-well 912 is greater than the depth of N-well 904 and P-well 906.

Method 1000 proceeds to operation 1006, as illustrated in FIG. 10, in which a recess is formed in the first well in the substrate, such that the recess is surrounded by the first well. In some implementations, the depth of the recess is between 50 nm and 100 nm. As illustrated in FIG. 9D, recesses 914 are formed in N-well 910 and P-well 912, respectively, for example, by the same etching process. In some implementations, a mask layer 911 is formed on silicon substrate 900 and then patterned to expose the regions in N-well 910 and P-well 912 in which recesses 914 are to be formed. Mask layer 911 can include a soft mask layer, such as a photoresist layer, and/or a hard mask layer, such as a silicon oxide layer. Mask layer 911 can be patterned using lithography and wet/dry etch. Etching of silicon substrate 900 can then be performed with mask layer 911 to form recesses 914 in

wells

910 and 912. The etching process can include dry etching and/or wet etching. In some implementations, the etching process is a dry etching process, such as reactive ion etch (RIE) . The etching conditions, such as etch rate and etch duration, can be controlled to control the depth of recess 914. In some implementations, the depth of recess 914 is between 50 nm and 100. As shown in FIG. 9D, recesses 914 are formed only in

wells

910 and 912 of recessed channel transistors, but not in

wells

904 and 906 of planar transistors.

Method 1000 proceeds to operation 1008, as illustrated in FIG. 10, in which a bent gate dielectric on a sidewall and a bottom surface of the recess and a flat gate dielectric on the substrate are formed. In some implementations, to form the bent gate dielectric and the flat gate dielectric, a sacrificial dielectric layer is formed on the sidewall and the bottom surface of the recess, the sacrificial dielectric layer is removed, a gate dielectric layer is formed on the sidewall and the bottom surface of the recess, and the gate dielectric layer is patterned.

As illustrated in FIG. 9J, a bent gate dielectric 931 is formed on the sidewall and the bottom surface of each recess 914 (shown in FIG. 9D) , and a flat gate dielectric 925 is formed on silicon substrate 900. To form bent gate dielectric 931 and flat gate dielectric 925, as shown in FIG. 9E, a gate dielectric layer 916 can be formed on the sidewall and the bottom surface of each recess 914 as well as on the top surface of silicon substrate 900 (e.g., wells 904 and 906) by the same deposition process. In some implementations, a layer of dielectric materials, such as silicon oxide, is deposited using one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD) , physical vapor deposition (PVD) , atomic layer deposition (ALD) , or any combination thereof. For example, a silicon oxide layer may be deposited using in situ steam generation (ISSG) to form gate dielectric layer 916. In some implementations, before forming gate dielectric layer 916, a sacrificial dielectric layer (not shown) is formed on the sidewall and the bottom surface of recess 914, for example, using thermal oxidation to remove the defects on the sidewall and the bottom surface of recess 914 caused by the etching process. The sacrificial dielectric layer can then be removed, for example, using wet etching, before forming gate dielectric layer 916. As shown in FIGs. 9I and 9J, gate dielectric layer 916 can be patterned to form flat gate dielectric 925 and bent gate dielectric 931 using lithography and etching processes in subsequent steps or the same step.

Method 1000 proceeds to operation 1010, as illustrated in FIG. 10, in which a recess gate electrode on the bent gate dielectric and a flat gate electrode on the flat gate dielectric are formed. In some implementations, to form the recess gate electrode and the flat gate electrode, a gate electrode layer is formed on the bent gate dielectric to fill the recess, the gate electrode layer is planarized, and the planarized gate electrode layer is patterned.

As illustrated in FIG. 9J, a recess gate electrode 920 is formed on bent gate dielectric 931, and a flat gate electrode 922 is formed on flat gate dielectric 925. To form recess gate electrode 920 and flat gate electrode 922, as shown in FIG. 9F, a gate electrode layer 918 is formed on gate dielectric layer 916. Recesses 914 (shown in FIG. 9E) can be filled by gate electrode layer 918. In some implementations, a layer of conductive materials, such as polysilicon, is deposited gate dielectric layer 916 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Depending on the surface flatness of gate electrode layer 918 affected by the depth of recess 914, a planarization process, such as chemical mechanical polishing (CMP) may be performed to planarize the top surface of gate electrode layer 918. As shown in FIG. 9G, recess gate electrode 920 and flat gate electrode 922 are formed by patterning gate electrode layer 918 using lithography and etching processes in the same step. In some implementations, recess gate electrode 920 and flat gate electrode 922 are doped to increase the conductivities thereof using ion implantation.

Method 1000 proceeds to operation 1012, as illustrated in FIG. 10, in which a first spacer structure is formed on a sidewall of the recess gate electrode above the substrate, and a second spacer structure on a sidewall of the flat gate electrode. The lateral dimension of the first spacer structure can be greater than the lateral dimension of the second spacer structure. In some implementations, to form to first and second spacer structures, a first inner spacer in contact with the sidewall of the first gate dielectric and a second inner spacer in contact with the sidewall of the second gate electrode are formed, a first outer spacer in contact with a sidewall of the first inner spacer and a second outer spacer in contact with a sidewall of the second inner spacer are formed, and the second outer spacer is removed.

As illustrated in FIG. 9H, inner spacers 924 are formed on the sidewalls of flat gate electrode 922 as well as on the sidewalls of part of recess gate electrode 920 that is above silicon substrate 900. Outer spacers 955 are then formed on the sidewalls of inner spacers 924. In some implementations, to form inner spacers 924, a layer of dielectric material (not shown) , such as silicon nitride or silicon oxide, is deposited on the sidewalls and the top surfaces of recess gate electrodes 920 and flat gate electrodes 922 as well as on gate dielectric layer 916 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The deposited layer of dielectric material can then be patterned using lithography and etching processes in the same step to remove parts on the top surfaces of recess gate electrodes 920, flat gate electrodes 922, and gate dielectric layer 916, leaving parts on the sidewalls of recess gate electrodes 920 and flat gate electrodes 922 to form inner spacers 924. In some implementations, to form outer spacers 955, another layer of a different dielectric material (not shown) , such as silicon oxide or silicon nitride, is deposited on the sidewalls of inner spacers 924 and the top surfaces of inner spacers 924 and recess gate electrodes 920 and flat gate electrodes 922 as well as on gate dielectric layer 916 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The deposited layer of another dielectric material can then be patterned using lithography and etching processes to form outer spacers 955.

As illustrated in FIG. 9I, a mask layer 951 is formed on silicon substrate 900 and then patterned to expose the regions of N-well 904 and P-well 906. Mask layer 951 can include a soft mask layer, such as a photoresist layer, and/or a hard mask layer, such as a silicon oxide layer. Mask layer 951 can be patterned using lithography and wet/dry etch. Outer spacers 955 that are not covered by mask layer 951 can then be selectively etched, leaving only inner spacers 924 on the sidewalls of flat gate electrodes 922. Depending on the dielectric materials used for forming inner and

outer spacers

924 and 955, wet etching using an etchant selective to outer spacers 955 against inner spacers 924 can be performed. As a result, the spacer structure with inner and

outer spacers

924 and 955 on the sidewall of recess gate electrode 920 has a larger lateral dimension than the spacer structure with only inner spacer 924 on the sidewall of flat gate electrode 922, according to some implementations.

Method 1000 proceeds to operation 1014, as illustrated in FIG. 10, in which an elevated portion is formed above the substrate and in contact with a sidewall of the first spacer structure. In some implementations, to form the elevated portion, single crystalline silicon is epitaxially grown from the substrate. In some implementations, the depth of the elevated portion is not less than 100 nm, such as between 100 nm and 150 nm.

As illustrated in FIG. 9J, elevated portions 952 are formed above N-well 910 in silicon substrate 900 and in contact with the sidewall of outer spacer 955. Similarly, as shown in FIG. 9K, elevated portions 954 are formed above P-well 912 in silicon substrate 900 and in contact with the sidewall of outer spacer 955. To form

elevated portions

952 and 954, single crystalline silicon can be selectively and epitaxially grown from the exposed areas of silicon substrate 900 between isolations 902 and outer spacers 925. The fabrication processes for epitaxially growing

elevated portions

952 and 954 can include, but not limited to, vapor-phase epitaxy (VPE) , liquid-phase epitaxy (LPE) , molecular-beam epitaxy (MBE) , or any combinations thereof. The depth of

elevated portions

952 and 954 can be controlled by controlling the growth rate and/or duration of the epitaxy process.

Method 1000 proceeds to operation 1016, as illustrated in FIG. 10, in which a first source and a first drain are formed in at least the elevated portion. In some implementations, to form the first source and drain, at least the elevated portion is doped. In some implementations, the first source and the first drain are formed in the elevated portion and the first well.

As illustrated in FIG. 9J, a P-type source 932 and a P-type drain 932 are formed in elevated portions 952 and N-well 910 and are spaced apart by

spacers

924 and 955 as well as bent gate dielectric 931 and recess gate electrode 920. To form P-type source and drain 932, in some implementations, a mask layer 930 is formed on silicon substrate 900 and then patterned to expose the region in which P-type source and drain 932 are to be formed. Mask layer 930 can include a soft mask layer, such as a photoresist layer, and/or a hard mask layer, such as a silicon oxide layer. Mask layer 930 can be patterned and aligned with N-well 910 using lithography and wet/dry etch. Ion implantation of P-type dopants, such as B or Ga, can be performed with mask layer 930 to form P-type source and drain 932 in at least elevated portions 952. In some implementations, P-type dopants are further diffused from elevated portions 952 into N-well 910, for example, by an annealing process, such that P-type source and drain 932 are formed in elevated portions 952 and N-well 910.

Similarly, as illustrated in FIG. 9K, an N-type source 934 and an N-type drain 934 are formed in elevated portions 954 and P-well 912 and are spaced apart by

spacers

924 and 955 as well as bent gate dielectric 931 and recess gate electrode 920. To form N-type source and drain 934, in some implementations, a mask layer 933 is formed on silicon substrate 900 and then patterned to expose the region in which N-type source and drain 934 are to be formed. Mask layer 933 can include a soft mask layer, such as a photoresist layer, and/or a hard mask layer, such as a silicon oxide layer. Mask layer 933 can be patterned and aligned with P-well 912 using lithography and wet/dry etch. Ion implantation of N-type dopants, such as P or As, can be performed with mask layer 933 to form N-type source and drain 934 in at least elevated portions 954. In some implementations, N-type dopants are further diffused from elevated portions 954 into P-well 912, for example, by an annealing process, such that N-type source and drain 934 are formed in elevated portions 954 and N-well 912.

Method 1000 proceeds to operation 1018, as illustrated in FIG. 10, in which a second source and a second drain are formed in the second well. As illustrated in FIG. 9J, P-type source and drain 926 and N-type source and drain 928 are subsequently formed in N-well 904 and P-well 906 of planar transistors, respectively, using lithography, followed by ion implantation of respective P-type dopants and N-type dopants. In some implementations, the conditions of ion implantation for P-type source and drain 926, N-type source and drain 928, P-type source and drain 932, and N-type source and drain 934 such doping concentration of P-type source and drain 932, and N-type source and drain 934 of recessed channel transistors are different from P-type source and drain 926, and N-type source and drain 928 of flat recessed channel transistors.

Referring to FIG. 11, method 1100 starts at operation 1102, in which a first well is formed in a substrate. The substrate can be a silicon substrate. As illustrated in FIG. 9A, a plurality of isolations 902, such as STIs, are formed in a silicon substrate 900, for example, using wet/dry etch and thin film deposition of silicon oxide. Isolations 902 can divide silicon substrates 900 into multiple regions in which multiple transistors can be formed, respectively. As illustrated in FIG. 9A, an N-well 904 and a P-well 906 are subsequently formed in silicon substrate 900. In some implementations, N-well 904 and P-well 906 are formed in regions for forming planar transistors. N-well 904 and P-well 906 can be patterned and aligned between isolation 902 using lithography, followed by ion implantation of respective N-type dopants and P-type dopants.

Method 1100 proceeds to operation 1104, as illustrated in FIG. 11, in which a second well is formed in the substrate. In some implementations, the depth of the second well is greater than the depth of the first well. As illustrated in FIG. 9B, an N-well 910 is formed in silicon substrate 900. N-well 910 may be part of a P-type recessed channel transistor and thus, may be formed in a region for forming the P-type recessed channel transistor. To form N-well 910, in some implementations, a mask layer 908 is formed on silicon substrate 900 and then patterned to expose the region in which N-well 910 is to be formed. Mask layer 908 can include a soft mask layer, such as a photoresist layer, and/or a hard mask layer, such as a silicon oxide layer. Mask layer 908 can be patterned and aligned between isolations 902 using lithography and wet/dry etch. Ion implantation of N-type dopants, such as P or As, can be performed with mask layer 908 to form N-well 910 into the desired region between isolations 902. In some implementations, the conditions of ion implantation for N-well 904, P-well 906, and N-well 910 are controlled, such that the depth of N-well 910 is greater than the depth of N-well 904 and P-well 906.

Method 1100 proceeds to operation 1106, as illustrated in FIG. 11, in which a recess is formed in the first well in the substrate, such that the recess is surrounded by the first well. In some implementations, the depth of the recess is between 50 nm and 100 nm. As illustrated in FIG. 9D, recesses 914 are formed in N-well 910 and P-well 912, respectively, for example, by the same etching process. In some implementations, a mask layer 911 is formed on silicon substrate 900 and then patterned to expose the regions in N-well 910 and P-well 912 in which recesses 914 are to be formed. Mask layer 911 can include a soft mask layer, such as a photoresist layer, and/or a hard mask layer, such as a silicon oxide layer. Mask layer 911 can be patterned using lithography and wet/dry etch. Etching of silicon substrate 900 can then be performed with mask layer 911 to form recesses 914 in

wells

910 and 912 of recessed channel transistors, but not in

wells

904 and 906 of planar transistors.

Method 1100 proceeds to operation 1108, as illustrated in FIG. 11, in which a bent gate dielectric on a sidewall and a bottom surface of the recess and a flat gate dielectric on the substrate are formed. In some implementations, to form the bent gate dielectric and the flat gate dielectric, a sacrificial dielectric layer is formed on the sidewall and the bottom surface of the recess, the sacrificial dielectric layer is removed, a gate dielectric layer is formed on the sidewall and the bottom surface of the recess, and the gate dielectric layer is patterned.

As illustrated in FIG. 9J, a bent gate dielectric 931 is formed on the sidewall and the bottom surface of each recess 914 (shown in FIG. 9D) , and a flat gate dielectric 925 is formed on silicon substrate 900. To form bent gate dielectric 931 and flat gate dielectric 925, as shown in FIG. 9E, a gate dielectric layer 916 can be formed on the sidewall and the bottom surface of each recess 914 as well as on the top surface of silicon substrate 900 (e.g., wells 904 and 906) by the same deposition process. In some implementations, a layer of dielectric materials, such as silicon oxide, is deposited using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. For example, a silicon oxide layer may be deposited using ISSG to form gate dielectric layer 916. In some implementations, before forming gate dielectric layer 916, a sacrificial dielectric layer (not shown) is formed on the sidewall and the bottom surface of recess 914, for example, using thermal oxidation to remove the defects on the sidewall and the bottom surface of recess 914 caused by the etching process. The sacrificial dielectric layer can then be removed, for example, using wet etching, before forming gate dielectric layer 916. As shown in FIGs. 9I and 9J, gate dielectric layer 916 can be patterned to form flat gate dielectric 925 and bent gate dielectric 931 using lithography and etching processes in subsequent steps or the same step.

Method 1100 proceeds to operation 1110, as illustrated in FIG. 11, in which a recess gate electrode on the bent gate dielectric and a flat gate electrode on the flat gate dielectric are formed. In some implementations, to form the recess gate electrode and the flat gate electrode, a gate electrode layer is formed on the bent gate dielectric to fill the recess, the gate electrode layer is planarized, and the planarized gate electrode layer is patterned.

Method 1100 proceeds to operation 1112, as illustrated in FIG. 11, in which a first source and a first drain spaced apart by the first gate dielectric and the first gate electrode are formed. At least one of the first source or the first drain can include a first region in contact with the first gate dielectric, and a second region at a top surface of the substrate and having a doping concentration higher than the first region. In some implementations, to form the first source and drain, dopants are doped into the second region, and the dopants are locally annealed to dope the first region, for example, using laser spike annealing. In some implementations, a source/drain contact is formed in contact with the second region.

As illustrated in FIG. 9J, a P-type source 932 and a P-type drain 932 are formed in N-well 910 and are spaced apart by bent gate dielectric 931 and recess gate electrode 920. To form P-type source and drain 932, in some implementations, a mask layer 930 is formed on silicon substrate 900 and then patterned to expose the region in which P-type source and drain 932 are to be formed. Mask layer 930 can include a soft mask layer, such as a photoresist layer, and/or a hard mask layer, such as a silicon oxide layer. Mask layer 930 can be patterned and aligned with N-well 910 using lithography and wet/dry etch. In some implementations, a high-low doping scheme is performed to form P-type source and drain 932 having a high-doping region and a low-doping region. For example, ion implantation of P-type dopants, such as B or Ga, may be first performed with mask layer 930 to form a shallow junction (as the high-doping region) at the top surface of N-well 910 in silicon substrate 900, for example, with a thickness of less than 100 nm. A local annealing process, such as laser spike annealing, then may be performed at the shallow junction to diffuse the P-type dopants into a deep junction (as the low-doping region) , for example, with a thickness of greater than 200 nm. After the local annealing, the doping concentration of the low-doping region may be between 10 ¹⁸/cm ³ and 10 ¹⁹/cm ³, and the doping concentration of the high-doping region may be at least 10 ²⁰/cm ³.

Similarly, as illustrated in FIG. 9K, an N-type source 934 and an N-type drain 934 are formed in P-well 912 and are spaced apart by bent gate dielectric 931 and recess gate electrode 920. To form N-type source and drain 934, in some implementations, a mask layer 933 is formed on silicon substrate 900 and then patterned to expose the region in which N-type source and drain 934 are to be formed. Mask layer 933 can include a soft mask layer, such as a photoresist layer, and/or a hard mask layer, such as a silicon oxide layer. Mask layer 933 can be patterned and aligned with P-well 912 using lithography and wet/dry etch. In some implementations, a high-low doping scheme is performed to form N-type source and drain 934 having a high-doping region and a low-doping region. For example, ion implantation of N-type dopants, such as P or As, may be first performed with mask layer 933 to form a shallow junction (as the high-doping region) at the top surface of P-well 912 in silicon substrate 900, for example, with a thickness of less than 100 nm. A local annealing process, such as laser spike annealing, then may be performed at the shallow junction to diffuse the N-type dopants into a deep junction (as the low-doping region) , for example, with a thickness of greater than 200 nm. After the local annealing, the doping concentration of the low-doping region may be between 10 ¹⁸/cm ³ and 10 ¹⁹/cm ³, and the doping concentration of the high-doping region may be at least 10 ²⁰/cm ³.

Method 1100 proceeds to operation 1114, as illustrated in FIG. 11, in which a second source and a second drain are formed in the second well. As illustrated in FIG. 9J, P-type source and drain 926 and N-type source and drain 928 are subsequently formed in N-well 904 and P-well 906 of planar transistors, respectively, using lithography, followed by ion implantation of respective P-type dopants and N-type dopants. In some implementations, the conditions of ion implantation for P-type source and drain 926, N-type source and drain 928, P-type source and drain 932, and N-type source and drain 934 such doping concentration of P-type source and drain 932, and N-type source and drain 934 of recessed channel transistors are different from P-type source and drain 926, and N-type source and drain 928 of flat recessed channel transistors.

The foregoing description of the specific implementations can be readily modified and/or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined only in accordance with the following claims and their equivalents.

Claims

A memory device, comprising:

an array of memory cells; and

a plurality of peripheral circuits coupled to the array of memory cells, the peripheral circuits comprising a first peripheral circuit comprising a recessed channel transistor, the recessed channel transistor comprising:

a well having a recess;

a recess gate structure protruding into the recess of the well and comprising a gate dielectric, and a gate electrode on the gate dielectric;

a spacer structure on a sidewall of the gate electrode; and

a source and a drain spaced apart by the spacer structure, wherein a top surface of the source and the drain is elevated from a bottom surface of the spacer structure.
The memory device of claim 1, wherein a depth between the top surface of the source and the drain and the bottom surface of the spacer structure is not less than 100 nm.
The memory device of claim 2, wherein the depth is between 100 nm and 150 nm.
The memory device of any one of claims 1-3, wherein each of the source and the drain comprises an elevated portion above the bottom surface of the spacer structure and in contact with the sidewall of the spacer structure.
The memory device of claim 4, wherein the elevated portion comprises single crystalline silicon.
The memory device of claim 4 or 5, wherein a first doping concentration of the elevated portion is higher than a second doping concentration of a reminder of the respective source or drain.
The memory device of claim 6, wherein a difference between the first and second doping concentrations is at least 10-fold.
The memory device of any one of claims 1-7, wherein the spacer structure comprises an inner spacer in contact with the sidewall of the gate electrode, and an outer spacer having a different material from the inner spacer.
The memory device of any one of claims 1-8, wherein the peripheral circuits further comprise a second peripheral circuit comprising a planar transistor, the planar transistor comprising:

a well;

a flat gate structure on the well and comprising a gate dielectric, and a gate electrode on the gate dielectric; and

a spacer structure on a sidewall of the gate electrode, wherein a lateral dimension of the spacer structure of the recessed channel transistor is greater than a lateral dimension of the spacer structure of the planar transistor.
The memory device of claim 9, wherein

the spacer structure of the planar transistor comprises an inner spacer having a same material as the inner spacer of the spacer structure of the recessed channel transistor; and

the spacer structure of the planar transistor does not comprise an outer spacer.
The memory device of claim 9 or 10, wherein

the planar transistor further comprises a source and a drain; and

a top surface of the source and the drain is coplanar with a bottom surface of the spacer structure.
The memory device of any one of claims 9-11, wherein a thickness of the gate dielectric of the recessed channel transistor is greater than a thickness of the gate dielectric of the planar transistor.
The memory device of any one of claims 1-12, wherein the first peripheral circuit comprises a driving circuit.
The memory device of any one of claims 1-13, wherein the first peripheral circuit is coupled to a voltage source of greater than 3.3 V.
The memory device of claim 14, wherein the voltage source is between 5 V and 30 V.
A semiconductor device, comprising:

a substrate;

a first transistor comprising:

a first well in the substrate and having a recess;

a recess gate structure protruding into the recess of the first well and comprising a first gate dielectric, and a first gate electrode on the first gate dielectric;

a first spacer structure on a sidewall of the first gate electrode; and

a first source and a first drain spaced apart by the first spacer structure and each comprising an elevated portion above a bottom surface of the first spacer structure and in contact with the sidewall of the first spacer structure; and

a second transistor comprising:

a second well in the substrate;

a flat gate structure on the second well and comprising a second gate dielectric, and a second gate electrode on the second gate dielectric; and

a second spacer structure on a sidewall of the second gate electrode, wherein a lateral dimension of the first spacer structure is greater than a lateral dimension of the second spacer structure.
The semiconductor device of claim 16, wherein a thickness of the first gate dielectric is greater than a thickness of the second gate dielectric.
The semiconductor device of claim 16 or 17, wherein a depth of the elevated portion is not less than 100 nm.
The semiconductor device of claim 18, wherein the depth is between 100 nm and 150 nm.
The semiconductor device of any one of claims 16-19, wherein the substrate and the elevated portion comprise single crystalline silicon.
The semiconductor device of any one of claims 16-20, wherein

the first spacer structure comprises a first inner spacer in contact with the sidewall of the first gate electrode, and an outer spacer having a different material from the first inner spacer; and

the second spacer structure comprises a second inner spacer having a same material as the first inner spacer, and does not comprise an outer spacer.
A method for forming a semiconductor device, comprising:

forming a recess in a substrate;

forming a first gate dielectric on a sidewall and a bottom surface of the recess, and a second gate dielectric on the substrate;

forming a first gate electrode on the first gate dielectric, and a second gate electrode on the second gate dielectric;

forming a first spacer structure on a sidewall of the first gate electrode above the substrate, and a second spacer structure on a sidewall of the second gate electrode, wherein a lateral dimension of the first spacer structure is greater than a lateral dimension of the second spacer structure;

forming an elevated portion above the substrate and in contact with a sidewall of the first spacer structure; and

forming a first source and a first drain in at least the elevated portion.
The method of claim 22, wherein forming the elevated portion comprises epitaxially growing single crystalline silicon from the substrate.
The method of claim 22 or 23, wherein a depth of the elevated portion is not less than 100 nm.
The method of claim 24, wherein the depth is between 100 nm and 150 nm.
The method of any one of claims 22-25, wherein forming the first spacer structure, and the second spacer structure comprises:

forming a first inner spacer in contact with the sidewall of the first gate dielectric, and a second inner spacer in contact with the sidewall of the second gate electrode;

forming a first outer spacer in contact with a sidewall of the first inner spacer, and a second outer spacer in contact with a sidewall of the second inner spacer; and

removing the second outer spacer.
The method of any one of claims 22-26, wherein forming the first source and the first drain comprises doping at least the elevated portion.
The method of claim 27, wherein doping at least the elevated portion comprises:

implanting dopants into the elevated portion; and

locally annealing the dopants.
The method of any one of claims 22-28, further comprising:

forming a first well, and a second well in the substrate, wherein the recess is in the first well, and the second gate dielectric is on the second well; and

forming a second source and a second drain in the second well.
The method of claim 29, wherein the first source and the first drain are formed in the elevated portion and the first well.