US20080001215A1 - Semiconductor device having recess gate and method of fabricating the same - Google Patents
Semiconductor device having recess gate and method of fabricating the same Download PDFInfo
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- US20080001215A1 US20080001215A1 US11/646,233 US64623306A US2008001215A1 US 20080001215 A1 US20080001215 A1 US 20080001215A1 US 64623306 A US64623306 A US 64623306A US 2008001215 A1 US2008001215 A1 US 2008001215A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 107
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 238000000034 method Methods 0.000 claims description 31
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 229910021332 silicide Inorganic materials 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 238000002955 isolation Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000001000 micrograph Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
Definitions
- the present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a recess gate and a method of fabricating the same.
- the devices shrink in size and patterns become fine.
- a gate channel length is also reduced so that an operational speed or input/output rate of information becomes slower due to a leakage current caused by short channel effect, hot carrier effect and so on.
- the bulb recess gate is configured with an upper portion with a vertical shape and a lower portion with a bulb shape.
- FIG. 1 illustrates a cross-sectional view showing a typical method of fabricating a recess gate in a semiconductor device.
- a device isolation structure 12 is formed in a predetermined region of a semiconductor substrate 11 to define an active region and a field region.
- the semiconductor substrate 11 of the active region is selectively etched to form a bulb recess 13 .
- the bulb recess 13 has an upper vertical portion 13 A and a lower bulb shaped portion 13 B.
- a gate insulating layer 14 is formed on the semiconductor substrate 11 where the bulb recess 13 is formed.
- a gate conductive layer is formed on the gate insulating layer 14 such that it is filled into the bulb recess 13 and protrudes higher than the top surface of the semiconductor substrate 11 .
- the gate conductive layer comprises a polysilicon layer 15 and a metal or metal silicide layer 16 , which are stacked in sequence.
- the bulb recess gate is used for widening the channel length.
- the upper vertical portion 13 A of the bulb recess 13 is narrow but the lower bulb shaped portion 13 B is rounded, the polysilicon layer 15 is not completely filled into the bulb shaped portion 13 B so that a seam A occurs in the polysilicon layer 15 .
- the lower bulb shaped portion 13 B of the bulb recess 13 is formed using an isotropic etch process, which leads to another limitation that there are sharp portions B where the upper vertical portion 13 A and the bulb shaped portion 13 B meet together.
- This sharp portion B has an adverse effect on device characteristics, e.g., deterioration of the gate insulating layer 14 .
- FIG. 2 illustrates a transmission electron microscope (TEM) micrograph showing the limitations according to the typical method.
- TEM transmission electron microscope
- Embodiments of the disclosure are directed to provide a semiconductor device having a recess gate and a method of fabricating the same, which can prevent the occurrence of a seam in depositing a conductive pattern for a gate electrode at least partially due to a shallow recess, and also can secure a sufficient channel length required for a high integrated device in spite of the shallow recess by using an epitaxial semiconductor layer.
- a semiconductor device having a recess gate including: a semiconductor substrate having a recess; a conductive pattern for a gate electrode filled into the recess, and having an extension portion protruding higher than a surface of the semiconductor substrate; an epitaxial semiconductor layer having a top surface and disposed over the semiconductor substrate; and a gate insulating layer disposed between the epitaxial semiconductor layer and the conductive pattern, and between the semiconductor substrate and the conductive pattern.
- a method of fabricating a semiconductor device having a recess gate comprising: forming a recess in a semiconductor substrate, wherein the semiconductor substrate has a top surface; forming a first gate insulating layer on a surface of the recess; forming a conductive pattern for a gate electrode, wherein the conductive pattern fills the recess, and has an extension portion protruding higher than the top surface of the semiconductor substrate; forming a second gate insulating layer on side surfaces of the extension portion of the conductive pattern; and epitaxially growing a semiconductor layer over the semiconductor substrate to a top surface of the conductive pattern.
- a method of fabricating a semiconductor device having a recess gate comprising: forming a recess in a semiconductor substrate, wherein the semiconductor substrate has a top surface; forming a first gate insulating layer on a surface of the recess; and forming a conductive pattern for a gate electrode, wherein the conductive pattern fills the recess, and has an extension portion protruding higher than the top surface of the semiconductor substrate.
- a semiconductor device having a recess gate comprising: a semiconductor substrate having a recess; and a conductive pattern for a gate electrode filled into the recess, and having an extension portion protruding higher than a surface of the semiconductor substrate.
- FIG. 1 illustrates a cross-sectional view showing a typical method of fabricating a recess gate in a semiconductor device.
- FIG. 2 illustrates a transmission electron microscope (TEM) micrograph showing limitations according to the typical method.
- FIG. 3 illustrates a cross-sectional view of a recess gate structure of a semiconductor device in accordance with some embodiments of the disclosure.
- FIGS. 4A to 4F illustrate cross-sectional views showing a method of fabricating a recess gate in a semiconductor device in accordance with some embodiments of the disclosure.
- FIG. 3 illustrates a cross-sectional view of a recess gate structure of a semiconductor device in accordance with some embodiments.
- a device isolation structure 22 is disposed in a semiconductor substrate 21 to define an active region.
- a recess 23 is formed in a semiconductor substrate 21 .
- a gate electrode conductive pattern 25 C is disposed over the semiconductor substrate 21 such that it fills the recess 23 , wherein the gate electrode conductive pattern 25 C has an extension portion that protrudes higher than the surface of the semiconductor substrate 21 .
- An epitaxial semiconductor layer 28 is disposed over the resultant structure including the gate electrode conductive pattern 25 C such that its top surface is as high as the top surface of the gate electrode conductive pattern 25 C.
- the epitaxial semiconductor layer 28 is formed to a thickness of at least approximately 100 ⁇ .
- a gate insulating layer is formed between the epitaxial semiconductor layer 28 and the gate electrode conductive pattern 25 C, and between the semiconductor substrate 21 and the gate electrode conductive pattern 25 C. More specifically, the gate insulating layer is configured with a first oxide layer 24 disposed between the semiconductor substrate 21 and the gate electrode conductive pattern 25 C, and a second oxide layer 27 disposed between the epitaxial layer 28 and the gate electrode conductive pattern 25 C.
- each of the semiconductor substrate 21 and the epitaxial semiconductor layer 28 may be formed of silicon, and the gate electrode conductive pattern 25 C may be formed of polysilicon.
- a metal or metal silicide 30 for a gate electrode may be additionally disposed on the gate electrode conductive pattern 25 C.
- the metal or metal silicide 30 may include a tungsten layer or a tungsten silicide layer.
- the recess gate structure in accordance with some embodiments has a shallower recess than that of the typical recess gate structure. Accordingly, there is no defect such as a seam when depositing the conductive pattern into the recess. Furthermore, some embodiments make use of the epitaxial semiconductor layer for securing the channel length. Thus, the epitaxial semiconductor layer 28 adjacent to the gate electrode conductive pattern 25 C is provided for a channel.
- FIGS. 4A to 4F illustrate cross-sectional views showing a method of fabricating a recess gate shown in FIG. 3 in accordance with some embodiments.
- a device isolation structure 22 is formed in a predetermined region of a semiconductor substrate 21 such as a silicon substrate using a shallow trench isolation (STI) process.
- the device isolation structure 22 defines an active region where transistors will be formed.
- a recess 23 is formed in the semiconductor substrate 21 using a typical recess mask and etching process.
- the recess 23 may be formed as a circle type recess, and a line width may be at least 35 nm or greater.
- an amorphous carbon may be used as a hard mask in the recess mask and etching process.
- the first gate insulating layer 24 is formed along the surface of the semiconductor substrate 21 where the recess 23 is formed.
- the first gate insulating layer 24 may be formed of an oxide using thermal oxidation, dry oxidation or wet oxidation, and it may have a thickness of approximately 100 ⁇ .
- a conductive layer such as a polysilicon layer is deposited on the first gate insulating layer 24 , and thereafter a gate mask and etching process is performed to form an angular conductive pattern 25 A of which top corners are angular and sharp.
- a defect such as a seam does not occur when depositing the polysilicon layer because the depth of the recess 23 is shallow.
- the gate mask and etching process may be performed using a typical photolithography process using exposure light such as KrF or ArF excimer laser on condition that the line width of the mask is at least 25 nm or greater and its thickness is at least 20 ⁇ or greater.
- a light etch treatment is performed to form a rounded conductive pattern 25 B of which top corners are somewhat rounded.
- the LET is performed using an isotropic etch process using CF 4 /O 2 gas.
- a second gate insulating layer 27 is formed on side surfaces of the rounded conductive pattern 25 B. More specifically, an oxide layer is formed on the resultant structure and it is then anisotropically etched to form the second gate insulating layer 27 on the side surfaces of the rounded conductive pattern 25 B in the shape of a spacer.
- a planarization process such as a chemical mechanical polishing (CMP) or the like is performed so as to expose the top surface of the rounded conductive pattern 25 B.
- CMP chemical mechanical polishing
- the rounded conductive pattern 25 B is also etched partially so that the top surface becomes more rounded to thereby form a gate electrode conductive pattern 25 C.
- the CMP process is performed for at least approximately 3 seconds or longer so that the epitaxial semiconductor layer 28 may be polished by a thickness of approximately 20 ⁇ or greater.
- a conductive layer 30 such as a metal layer or a metal silicide layer may be formed on the gate electrode conductive pattern 25 C.
- the conductive layer 30 may include a tungsten layer or a tungsten silicide layer.
- the conductive layer 30 may be omitted according to circumstances.
- the final line width of the recess gate may be at least approximately 35 nm.
- the recess gate structure has a shallow recess so that defects such as seams will not form while depositing the conductive layer in the recess for the gate electrode. Further, despite the shallow recess, the use of the epitaxial semiconductor layer provides a sufficient channel length which is required for a highly integrated device Further, it is possible to prevent the gate electrode conductive pattern from having sharp edges.
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Abstract
A semiconductor device having a recess gate includes a semiconductor substrate having a recess, a conductive pattern for a gate electrode filled into the recess, and having an extension portion protruding higher than a surface of the semiconductor substrate, an epitaxial semiconductor layer having a top surface disposed over the semiconductor substrate, and a gate insulating layer disposed between the epitaxial semiconductor layer and the conductive pattern, and between the semiconductor substrate and the conductive pattern. Further, a method of fabricating the same is disclosed.
Description
- The present invention claims priority of Korean patent application numbers KR 10-2006-0060292 and KR 10-2006-0124735, filed on Jun. 30, 2006 and Dec. 8, 2006, respectively, being incorporated by reference in their entirety.
- The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a recess gate and a method of fabricating the same.
- Recently, with the high integration of semiconductor memory devices, the devices shrink in size and patterns become fine. As the size of the device becomes smaller, a gate channel length is also reduced so that an operational speed or input/output rate of information becomes slower due to a leakage current caused by short channel effect, hot carrier effect and so on.
- To prevent this phenomenon, there has been proposed various structured recess gates for securing a channel length. Among them, a bulb recess gate, which has been put to practical use in recent years, and is being actively researched because it has an advantage of securing the channel length effectively. The bulb recess gate is configured with an upper portion with a vertical shape and a lower portion with a bulb shape.
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FIG. 1 illustrates a cross-sectional view showing a typical method of fabricating a recess gate in a semiconductor device. Adevice isolation structure 12 is formed in a predetermined region of asemiconductor substrate 11 to define an active region and a field region. Thesemiconductor substrate 11 of the active region is selectively etched to form abulb recess 13. Thebulb recess 13 has an upper vertical portion 13A and a lower bulb shaped portion 13B. A gate insulating layer 14 is formed on thesemiconductor substrate 11 where thebulb recess 13 is formed. A gate conductive layer is formed on the gate insulating layer 14 such that it is filled into thebulb recess 13 and protrudes higher than the top surface of thesemiconductor substrate 11. Herein, the gate conductive layer comprises a polysilicon layer 15 and a metal ormetal silicide layer 16, which are stacked in sequence. - As described above, the bulb recess gate is used for widening the channel length. However, since the upper vertical portion 13A of the
bulb recess 13 is narrow but the lower bulb shaped portion 13B is rounded, the polysilicon layer 15 is not completely filled into the bulb shaped portion 13B so that a seam A occurs in the polysilicon layer 15. - In addition, the lower bulb shaped portion 13B of the
bulb recess 13 is formed using an isotropic etch process, which leads to another limitation that there are sharp portions B where the upper vertical portion 13A and the bulb shaped portion 13B meet together. This sharp portion B has an adverse effect on device characteristics, e.g., deterioration of the gate insulating layer 14. -
FIG. 2 illustrates a transmission electron microscope (TEM) micrograph showing the limitations according to the typical method. A polysilicon layer may not be completely filled into a recess and thus a seam occurs in the polysilicon layer. - Embodiments of the disclosure are directed to provide a semiconductor device having a recess gate and a method of fabricating the same, which can prevent the occurrence of a seam in depositing a conductive pattern for a gate electrode at least partially due to a shallow recess, and also can secure a sufficient channel length required for a high integrated device in spite of the shallow recess by using an epitaxial semiconductor layer.
- In accordance with an some aspects of the disclosure, there is provided a semiconductor device having a recess gate, including: a semiconductor substrate having a recess; a conductive pattern for a gate electrode filled into the recess, and having an extension portion protruding higher than a surface of the semiconductor substrate; an epitaxial semiconductor layer having a top surface and disposed over the semiconductor substrate; and a gate insulating layer disposed between the epitaxial semiconductor layer and the conductive pattern, and between the semiconductor substrate and the conductive pattern.
- In accordance with other embodiments, there is provided a method of fabricating a semiconductor device having a recess gate, the method comprising: forming a recess in a semiconductor substrate, wherein the semiconductor substrate has a top surface; forming a first gate insulating layer on a surface of the recess; forming a conductive pattern for a gate electrode, wherein the conductive pattern fills the recess, and has an extension portion protruding higher than the top surface of the semiconductor substrate; forming a second gate insulating layer on side surfaces of the extension portion of the conductive pattern; and epitaxially growing a semiconductor layer over the semiconductor substrate to a top surface of the conductive pattern.
- In accordance with other embodiments, there is provided a method of fabricating a semiconductor device having a recess gate, the method comprising: forming a recess in a semiconductor substrate, wherein the semiconductor substrate has a top surface; forming a first gate insulating layer on a surface of the recess; and forming a conductive pattern for a gate electrode, wherein the conductive pattern fills the recess, and has an extension portion protruding higher than the top surface of the semiconductor substrate.
- In accordance with other embodiments, there is provided a semiconductor device having a recess gate, comprising: a semiconductor substrate having a recess; and a conductive pattern for a gate electrode filled into the recess, and having an extension portion protruding higher than a surface of the semiconductor substrate.
-
FIG. 1 illustrates a cross-sectional view showing a typical method of fabricating a recess gate in a semiconductor device. -
FIG. 2 illustrates a transmission electron microscope (TEM) micrograph showing limitations according to the typical method. -
FIG. 3 illustrates a cross-sectional view of a recess gate structure of a semiconductor device in accordance with some embodiments of the disclosure. -
FIGS. 4A to 4F illustrate cross-sectional views showing a method of fabricating a recess gate in a semiconductor device in accordance with some embodiments of the disclosure. -
FIG. 3 illustrates a cross-sectional view of a recess gate structure of a semiconductor device in accordance with some embodiments. Adevice isolation structure 22 is disposed in asemiconductor substrate 21 to define an active region. Arecess 23 is formed in asemiconductor substrate 21. A gate electrodeconductive pattern 25C is disposed over thesemiconductor substrate 21 such that it fills therecess 23, wherein the gate electrodeconductive pattern 25C has an extension portion that protrudes higher than the surface of thesemiconductor substrate 21. Anepitaxial semiconductor layer 28 is disposed over the resultant structure including the gate electrodeconductive pattern 25C such that its top surface is as high as the top surface of the gate electrodeconductive pattern 25C. Theepitaxial semiconductor layer 28 is formed to a thickness of at least approximately 100 Å. A gate insulating layer is formed between theepitaxial semiconductor layer 28 and the gate electrodeconductive pattern 25C, and between thesemiconductor substrate 21 and the gate electrodeconductive pattern 25C. More specifically, the gate insulating layer is configured with afirst oxide layer 24 disposed between thesemiconductor substrate 21 and the gate electrodeconductive pattern 25C, and asecond oxide layer 27 disposed between theepitaxial layer 28 and the gate electrodeconductive pattern 25C. - Preferably, each of the
semiconductor substrate 21 and theepitaxial semiconductor layer 28 may be formed of silicon, and the gate electrodeconductive pattern 25C may be formed of polysilicon. In addition, a metal ormetal silicide 30 for a gate electrode may be additionally disposed on the gate electrodeconductive pattern 25C. For example, the metal ormetal silicide 30 may include a tungsten layer or a tungsten silicide layer. - As described above, the recess gate structure in accordance with some embodiments has a shallower recess than that of the typical recess gate structure. Accordingly, there is no defect such as a seam when depositing the conductive pattern into the recess. Furthermore, some embodiments make use of the epitaxial semiconductor layer for securing the channel length. Thus, the
epitaxial semiconductor layer 28 adjacent to the gate electrodeconductive pattern 25C is provided for a channel. -
FIGS. 4A to 4F illustrate cross-sectional views showing a method of fabricating a recess gate shown inFIG. 3 in accordance with some embodiments. - Referring to
FIG. 4A , adevice isolation structure 22 is formed in a predetermined region of asemiconductor substrate 21 such as a silicon substrate using a shallow trench isolation (STI) process. Thedevice isolation structure 22 defines an active region where transistors will be formed. Subsequently, arecess 23 is formed in thesemiconductor substrate 21 using a typical recess mask and etching process. In some embodiments, therecess 23 may be formed as a circle type recess, and a line width may be at least 35 nm or greater. In addition, an amorphous carbon may be used as a hard mask in the recess mask and etching process. Thereafter, a firstgate insulating layer 24 is formed along the surface of thesemiconductor substrate 21 where therecess 23 is formed. The firstgate insulating layer 24 may be formed of an oxide using thermal oxidation, dry oxidation or wet oxidation, and it may have a thickness of approximately 100 Å. - Referring to
FIG. 4B , a conductive layer such as a polysilicon layer is deposited on the firstgate insulating layer 24, and thereafter a gate mask and etching process is performed to form an angularconductive pattern 25A of which top corners are angular and sharp. In this case, a defect such as a seam does not occur when depositing the polysilicon layer because the depth of therecess 23 is shallow. The gate mask and etching process may be performed using a typical photolithography process using exposure light such as KrF or ArF excimer laser on condition that the line width of the mask is at least 25 nm or greater and its thickness is at least 20 Å or greater. - Referring to
FIG. 4C , a light etch treatment (LET) is performed to form a roundedconductive pattern 25B of which top corners are somewhat rounded. The LET is performed using an isotropic etch process using CF4/O2 gas. - Referring to
FIG. 4D , a secondgate insulating layer 27 is formed on side surfaces of the roundedconductive pattern 25B. More specifically, an oxide layer is formed on the resultant structure and it is then anisotropically etched to form the secondgate insulating layer 27 on the side surfaces of the roundedconductive pattern 25B in the shape of a spacer. - Afterward, an
epitaxial semiconductor layer 28 formed of, e.g., silicon, is formed using an epitaxial growth process such that it covers the resultant structure where the roundedconductive pattern 25B is formed. Afterwards, the roundedconductive pattern 25B is embedded within thesemiconductor substrate 21 and theepitaxial semiconductor layer 28. As a result, it is possible to secure a channel required for a highly integrated device. - Referring to
FIG. 4E , a planarization process such as a chemical mechanical polishing (CMP) or the like is performed so as to expose the top surface of the roundedconductive pattern 25B. During the planarization process, the roundedconductive pattern 25B is also etched partially so that the top surface becomes more rounded to thereby form a gate electrodeconductive pattern 25C. For instance, the CMP process is performed for at least approximately 3 seconds or longer so that theepitaxial semiconductor layer 28 may be polished by a thickness of approximately 20 Å or greater. - Referring to
FIG. 4F , aconductive layer 30 such as a metal layer or a metal silicide layer may be formed on the gate electrodeconductive pattern 25C. For example, theconductive layer 30 may include a tungsten layer or a tungsten silicide layer. In some embodiments, theconductive layer 30 may be omitted according to circumstances. The final line width of the recess gate may be at least approximately 35 nm. - In some embodiments, the recess gate structure has a shallow recess so that defects such as seams will not form while depositing the conductive layer in the recess for the gate electrode. Further, despite the shallow recess, the use of the epitaxial semiconductor layer provides a sufficient channel length which is required for a highly integrated device Further, it is possible to prevent the gate electrode conductive pattern from having sharp edges.
- While the present invention has been described with respect to the some embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.
Claims (23)
1. A semiconductor device having a recess gate, comprising:
a semiconductor substrate having a recess;
a conductive pattern for a gate electrode filled into the recess, and having an extension portion protruding higher than a surface of the semiconductor substrate;
an epitaxial semiconductor layer having a top surface disposed over the semiconductor substrate; and
a gate insulating layer disposed between the epitaxial semiconductor layer and the conductive pattern, and between the semiconductor substrate and the conductive pattern.
2. The semiconductor device of claim 1 , wherein the semiconductor substrate and the epitaxial semiconductor layers comprise silicon.
3. The semiconductor device of claim 1 , wherein the recess is shallow so that the conductive pattern can be formed in a single step to avoid forming a seam in the conductive pattern.
4. The semiconductor device of claim 1 , wherein the conductive pattern comprises polysilicon.
5. The semiconductor device of claim 1 , wherein the thickness of the epitaxial semiconductor layer is at least approximately 100 Å.
6. The semiconductor device of claim 1 , further comprising a gate electrode over the conductive pattern, wherein the gate electrode comprises at least one of a metal pattern and a metal silicide pattern.
7. The semiconductor device of claim 1 , further comprising a gate electrode over the conductive pattern, wherein the gate electrode comprises at least one of a tungsten pattern and a tungsten silicide pattern.
8. The semiconductor device of claim 1 , wherein the gate insulating layer further comprises:
a first oxide layer disposed between the semiconductor substrate and the conductive pattern; and
a second oxide layer disposed between the epitaxial semiconductor layer and the conductive pattern.
9. A method of fabricating a semiconductor device having a recess gate, the method comprising:
forming a recess in a semiconductor substrate, wherein the semiconductor substrate has a top surface;
forming a first gate insulating layer on a surface of the recess;
forming a conductive pattern for a gate electrode, wherein the conductive pattern fills the recess, and has an extension portion protruding higher than the top surface of the semiconductor substrate;
forming a second gate insulating layer on side surfaces of the extension portion of the conductive pattern; and
epitaxially growing a semiconductor layer over the semiconductor substrate to a top surface of the conductive pattern.
10. The method of claim 9 , wherein forming the conductive pattern for the gate electrode further comprises:
depositing a conductive layer over the resultant structure where the first gate insulating layer is formed;
pattering the conductive layer using a gate mask and etching process to form the conductive pattern; and
performing a light etch treatment for rounding corners of the conductive pattern.
11. The method of claim 9 , further comprising, after epitaxially growing the semiconductor layer, planarizing the semiconductor layer.
12. The method of claim 9 , wherein forming the conductive pattern further comprises forming the conductive pattern in a single step to avoid a seam forming in the conductive pattern.
13. The method of claim 11 , wherein forming the second gate insulating layer on the side surfaces of the extension portion further comprises:
forming an oxide layer over the resultant structure including the conductive pattern; and
anisotropically etching the oxide layer.
14. The method of claim 9 , wherein forming the conductive pattern further comprising forming the conductive pattern comprising polysilicon.
15. The method of claim 11 , wherein planarizing the semiconductor layer further comprises planarizing the semiconductor layer using a chemical mechanical polishing (CMP) process.
16. The method of claim 9 , wherein forming a recess in a semiconductor substrate further comprises forming a recess in a semiconductor substrate, wherein the semiconductor substrate comprises silicon; and wherein epitaxially growing a semiconductor layer further comprises epitaxially growing a semiconductor layer, wherein the semiconductor layer comprises silicon.
17. The method of claim 9 , further comprising forming a pattern over the conductive pattern, wherein the pattern comprises at least one of a metal pattern and a metal silicide pattern.
18. A method of fabricating a semiconductor device having a recess gate, the method comprising:
forming a recess in a semiconductor substrate, wherein the semiconductor substrate has a top surface;
forming a first gate insulating layer on a surface of the recess; and
forming a conductive pattern for a gate electrode, wherein the conductive pattern fills the recess, and has an extension portion protruding higher than the top surface of the semiconductor substrate.
19. The method of claim 18 , wherein forming the conductive pattern further comprising depositing a conductive layer in a single step to avoid a seam forming in the conductive layer, wherein the conductive pattern is formed by etching the conductive layer.
20. The method of claim 18 , wherein forming the conductive pattern for the gate electrode further comprises:
depositing a conductive layer over the resultant structure where the first gate insulating layer is formed;
pattering the conductive layer using a gate mask and etching process to form the conductive pattern; and
performing a light etch treatment for rounding corners of the conductive pattern.
21. A semiconductor device having a recess gate, comprising:
a semiconductor substrate having a recess; and
a conductive pattern for a gate electrode filled into the recess, and having an extension portion protruding higher than a surface of the semiconductor substrate.
22. The semiconductor device of claim 21 , wherein the recess is shallow so that the conductive pattern can be formed in a single step to avoid forming a seam in the conductive pattern.
23. The semiconductor device of claim 21 , wherein the conductive pattern has rounded corners.
Priority Applications (1)
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US12/553,581 US7898025B2 (en) | 2006-06-30 | 2009-09-03 | Semiconductor device having recess gate |
Applications Claiming Priority (4)
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KR10-2006-0060292 | 2006-06-30 | ||
KR20060060292 | 2006-06-30 | ||
KR10-2006-0124735 | 2006-12-08 | ||
KR1020060124735A KR100780620B1 (en) | 2006-06-30 | 2006-12-08 | Semiconductor device with recess gate and method for fabricating the same |
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US12/553,581 Division US7898025B2 (en) | 2006-06-30 | 2009-09-03 | Semiconductor device having recess gate |
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US20080001215A1 true US20080001215A1 (en) | 2008-01-03 |
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US11/646,233 Abandoned US20080001215A1 (en) | 2006-06-30 | 2006-12-28 | Semiconductor device having recess gate and method of fabricating the same |
US12/553,581 Expired - Fee Related US7898025B2 (en) | 2006-06-30 | 2009-09-03 | Semiconductor device having recess gate |
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US12/553,581 Expired - Fee Related US7898025B2 (en) | 2006-06-30 | 2009-09-03 | Semiconductor device having recess gate |
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US20080227281A1 (en) * | 2007-03-15 | 2008-09-18 | Hynix Semiconductor Inc. | Method for fabricating semiconductor device with recess gate |
US20210343528A1 (en) * | 2018-11-08 | 2021-11-04 | Stratio | Methods for forming a germanium island using selective epitaxial growth and a sacrificial filling layer |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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KR101087918B1 (en) * | 2009-12-21 | 2011-11-30 | 주식회사 하이닉스반도체 | Semiconductor device and method for fabricating the same |
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Also Published As
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US20090321821A1 (en) | 2009-12-31 |
US7898025B2 (en) | 2011-03-01 |
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