536746 五、發明說明（1) 發明領域： 本發明係有關一種新的快閃記憶體（F 1 ash )的製作 方法，特別是關於一種利用多晶矽懸浮閘極間隙物 (Spacer )製程，建立雙位元快閃記憶體的方法，不謹無 須再多光罩製程即可自動對準而完成懸浮閘極的製程，以 製造出具有雙位元（2Bit/cel 1 )的快閃記憶體元件。 發明背景： 在電腦產品資訊發達的今天，可電除且可程式化唯讀 記憶體（Electrically Erasable Programmable Read Only Memory ’EEPROM)，為現今資訊電子產品所廣泛採 用的記憶元件，但是在習知的可電除且可程式化唯讀記憶 體（E E P R 0 Μ )中，有存取速度較慢的缺點，然而隨製程技 術的進步，近年已開發出存取速度較快的EEPR〇M，一般稱 之為快閃記憶體（F 1 ash )，這種新型的非揮發性記憶 體，可改進以往習知記憶體之缺點。 基本上，典型的快閃記憶體係以懸浮閘極電晶體為基 ，之非揮發性記憶體，如第1圖所示，在快閃記憶體中的^ 每一個記憶胞都是在一半導體基材1〇中利用離子佈植法分 別形成一源極（source ) 12與一汲極（drain ) 14，接續7 在源極1 2與汲極1 4之間的半導體基材丨〇表面，由下而上焉依 序形成有一氧化介電層（dielectric layer ) u、一作^ 儲存電荷之用的懸浮閘極丨8、一絕緣介電層2 〇以及一: 控制貧料存取的控制閘極（contr〇1 gate ) 22。且該快閃536746 V. Description of the Invention (1) Field of the Invention: The present invention relates to a method for manufacturing a new flash memory (F 1 ash), in particular to a process of using a polycrystalline silicon suspension gate spacer (Spacer) process to establish a dual-bit In the method of flash memory, the process of suspending the gate can be automatically aligned without the need for multiple photomask manufacturing processes, so as to manufacture a flash memory device with double bits (2Bit / cel 1). Background of the Invention: With the advancement of computer product information, electrically erasable and programmable read only memory (EEPROM) is a widely used memory element in today's information electronics products. In the erasable and programmable read-only memory (EEPR 0 Μ), there is a disadvantage of slow access speed. However, with the advancement of process technology, EEPROM, which has a faster access speed, has been developed in recent years. It is flash memory (F 1 ash), this new type of non-volatile memory can improve the disadvantages of conventional memory. Basically, a typical flash memory system is based on a suspended gate transistor. Non-volatile memory, as shown in Figure 1, in the flash memory, each memory cell is a semiconductor-based A source electrode 12 and a drain electrode 14 are respectively formed in the material 10 by an ion implantation method, followed by 7 on the surface of the semiconductor substrate between the source electrode 12 and the drain electrode 14 by From bottom to top, an oxide dielectric layer (u), a floating gate for storing electric charges, (8), an insulating dielectric layer (20), and a control gate for controlling lean material access are sequentially formed. (Contr〇1 gate) 22. And the flash
第5頁 536746 五、發明說明（2) ί = 態取決於懸浮閘極18的電荷濃度，而其操 作方：π自懸浮閉極18注入或移除電荷的技術。 閘極22，使得熱電子從 同電i於技制 浮閘極18中，据古1 /贸 牙虱化介電層16而注入懸 ^ ΓψΊ f r知鬲其臨界電壓；當進行資枓姑咚栌0ί 加一高電壓於源極丨2，#尸，、f、、± 丁貝枓抹除呀，則施 可由所古胃的福 、于月· ’L /入到懸浮閘極1 8的電子 J猎田所口月的知勒―諾得漢（F〇wl 稱F-N隧穿）技術之随穿 隨穿（簡 源極12, U回德/丄田穿過乳化介電層16而流入 κ，、U设原有的臨界電壓。 然而’在上述的非揮發性 個記f音胞σ萨找产 凡件快閃記憶體中，一 似X U肊/、此儲存一個位元（Bi τ 憶體之記憶容量未能達到理想。因故種自知的快閃記 憶體之記憶容量太小 為解决習知快閃記 懸浮閘極間隙物製程建立雔位：明提j共一種利用多晶矽 在控制閘下方努雙位70快閃記憶體的方法，使龙 ;;憶體，以增加快閃記憶體元 S又：元的快閃 問題。 己合里，解決上述之 务明之目的與概述： 間隙物Ϊ ‘ ： = : f目係在提供-種利用多晶妙縣、孕 ":衣建立雙位元快閃記憶體之方法二予閘極 ~ +母一记憶胞係具有二懸浮閘極，以祚A餡、4 C憶體 儲=二將快閃記憶體容量增加至；！；；：式的電荷 —電何儲存區域可經由元件的源極、汲極；：：：“ 536746 五、發明說明（3) 別控制之。 制、本發明之另一目的係在提供一種雙位元伊開命檢，之 衣造方法，其係利用多晶石夕間隙物（p〇ly〜Si、A。思; 程制，須再經過多光罩製程，即可自動對準的間 極製程，省略習知黃光製程及其對不準的缺二'于 根據本發明，其係利用已定義氮 基底進行離子植入，再形成一發 將亂切層及墊氧化層去除；接著，在沈積ς ^ 第一…層，之後對第」多=進行 非等向性餘刻，以形成多晶石夕間隙物； 介電層及形成-已定義之第一多曼再沈積一、、、巴緣 快閃記憶體結構。 夕曰日矽層，以形成-雙位元 攻有Kit:ϊί員，對本發明之結構特徵及達成之功 以配合詳細之說明，說明如後。竿又佳之““列圖式 圖號說明： 10 半導體基材 12 14 汲極 16 18 懸浮閘極 20 22 控制閘極 30 矽基底 32 34 氮化石夕層 36 38 離子摻雜區 40 42 隧穿介電層 44 t總甘上丄 源極 氧化介電層 絕緣介電層 墊氧化層 光阻 氧化層 第一多晶矽層 第7頁 536746 五、發明說明（4) 48 絕緣介電層 46 多晶矽間隙物 5 0 第二多晶矽層 詳細說明： 本發明係在非揮發性記憶體元件製程中，利用多曰 目么、> ’日日巧/ ⑷洋閘極間隙物製程來建立雙位元快閃記憶體的方法，以 增加非揮發性快閃記憶體之記憶容量。本方法是利用在控 ，閑了方，使用内凹式多晶矽間隙物（Poly Spacer )在工 單=記憶胞元件中製作不連續的懸浮閘極，作為雙點式的 Ϊ ^ Ϊ存單元，以建立雙位元的快閃記憶體，使其記憶容 里為f知之兩倍的非揮發性快閃記憶體元件。 “ 快門=圖至第9圖係為本發明之較佳實施例在製作雙位元 驟2 體過程時之各步驟構造剖視圖。本發明之主要步 —下·，先，如第2圖所示，先在半導體矽基底3〇上沈 ‘著：ί氧化層（Pad 〇Xide) 32，其厚度大約為200A， 為1 9 0 0人 方沈積一層氮化石夕層（SiN) 34，其厚度約 習知的於氮化矽層34上方形成一圖案化光阻36，以 行之氮刻製程定義該氮化卿，形成複數條平 之先3 圖:/，在對氮切層34钱刻後，將上述 利用離子植：去ί : Ϊ該已定義之氮化矽層34為硬罩幕， 相鄰的氮化石夕體石夕基底30進行離子植入，使其在 乳化石夕層34之間㈣基細中形成離子摻Page 5 536746 V. Description of the invention (2) The state of ί = depends on the charge concentration of the floating gate 18, and its operator: π technology for injecting or removing charge from the floating closed electrode 18. The gate electrode 22 enables the hot electrons to be injected from the same floating gate electrode 18 into the floating gate electrode 18, and is injected into the suspension layer ^ Γψ / fr to know the threshold voltage;栌 0ί Add a high voltage to the source 丨 2, ## ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, and to the Ding Beibei. The Knowle-Nordhan (F0wl, FN tunneling) technology of the electronic J hunting field, and the wear-and-peer (Jane source 12, U Huide / Putian through the emulsified dielectric layer 16 and flows into κ , U sets the original threshold voltage. However, in the above non-volatile memory cell σSa to find all flash memory, XU 肊 /, this stores a bit (Bi τ memory The memory capacity of the body fails to reach the ideal. For this reason, the memory capacity of the self-known flash memory is too small to solve the problem of the conventional flash memory suspension gate gap manufacturing process: Mingti j is a type of polycrystalline silicon used in the control gate The following method of double-bit 70 flash memory makes the dragon; memory to increase the flash memory element S: The flash problem of the element. The purpose and overview of the Ming: Interstitial Ϊ '： =: f is providing-a method to create a dual-bit flash memory by using polycrystalline Miao County, pregnant: quoting the gate ~ + mother-memory The cell line has two suspension gates, with 祚 A stuffing and 4 C memory storage = two to increase the flash memory capacity to;! ;;: the type of charge-the storage area can pass through the source and drain of the element ; :: "536746 V. Description of the invention (3) Don't control it. Another purpose of the present invention is to provide a two-bit Yikai life test, a method of making clothes, which uses polycrystalline stone gaps. (P〇ly ~ Si, A. Thinking; process system, you need to go through the multi-mask process, you can automatically align the pole process, omitting the conventional yellow light process and its inaccurate missing two. In the present invention, a defined nitrogen substrate is used for ion implantation, and then a chaotic layer and a pad oxide layer are removed in a single shot; and then, the first layer is deposited on the deposit, and then the "multiple" layer is anisotropic. In the rest of the time, to form polycrystalline stone interstitial spaces; the dielectric layer and the formation-the first defined Doman redeposition Flash memory structure. Evening silicon layer to form-double bit attack Kit: ϊ members, with detailed description of the structural features and achievements of the present invention, as explained later. Illustration of drawing number: 10 semiconductor substrate 12 14 drain 16 18 suspension gate 20 22 control gate 30 silicon substrate 32 34 nitride layer 36 38 ion-doped region 40 42 tunneling dielectric layer 44 t Upper Source Oxidation Dielectric Layer Insulation Dielectric Layer Pad Oxide Photoresistive Oxide Layer First Polycrystalline Silicon Layer Page 7 536746 V. Description of the Invention (4) 48 Insulating Dielectric Layer 46 Polycrystalline Silicon Interstitial 5 0 Second Most Crystalline silicon layer detailed description: The present invention is a method for establishing a dual-bit flash memory by using a multi-process, > 'Ri-Ri-Ki / Yang-Yang gate-gap spacer process in a non-volatile memory device process. To increase the memory capacity of non-volatile flash memory. In this method, a discontinuous floating gate is made in a work order = memory cell element using a recessed polysilicon spacer (Poly Spacer) as a two-point 式 Ϊ storage unit. Create a two-bit flash memory with a non-volatile flash memory device with twice the memory capacity. "Shutter = Figure to Figure 9 is a sectional view of the steps of the preferred embodiment of the present invention when making a two-bit step 2 body process. The main steps of the present invention-down, first, as shown in Figure 2 First, deposited on a semiconductor silicon substrate 30: a layer of oxide (Pad OXide) 32, which has a thickness of about 200A, and a layer of nitrided silicon nitride (SiN) 34 is deposited for 1900 people, with a thickness of about A conventional patterned photoresist 36 is formed on the silicon nitride layer 34, and the nitride film is defined by a nitrogen etch process to form a plurality of flat layers. Figure 3 /: After the nitrogen cut layer 34 is etched The above-mentioned use of ion implantation: to go to:: The defined silicon nitride layer 34 is a hard mask, and the adjacent nitrided stone body 30 is subjected to ion implantation so that it is in the emulsified stone layer 34. Ionic dopant
ηn
第8頁 536746 五、發明說明（5) 以作為源極及沒極。 在上述之離子摻雜區38完成 高密度電衆化學氣相沈積法二之^ 3〇上沈積一層厚度為3〇0〇A之氧化層a γ 層，以覆蓋在該氮化矽声34声而*话# 、带為乳化石夕 間的空隙。再以化與機=m =亚真滿相鄰氮化矽層34之 工I糸丹以化子機械研磨法進行平扫制 、 多餘部份之氧化層40直至暴露出氮化矽^ 以一除 圖所示，經過化學機械研磨後 _ S ，、、、，如第5 14〇〇A。 研磨後之鼠化石夕層34的厚度約為 請J閱第6圖所示，在利用化學 表面研磨平滑後，再將該氮化石夕層 乳化層4〇 矽層34下方之墊氧化層32 一併去：：门日:亦將亂化 義出懸汙閘極兀件區之位置。此時， 疋 1 0 00A 〇 虱化層4〇之厚度約為 f著’先將矽基底30表面清洗乾淨之後，開始在矽 :3〇表面形成一隧穿介電層42，此随穿介電層 土 物層’其厚度約為7GA，如第7圖所示，而後再進乳曰化 :沉積，在該石夕基底30上方沈積第一多晶石夕層44 : ㈣及隨穿介電層42，此第—多⑼層44之厚度約 再參閱第8圖所示，對上述第一多晶矽層“進行非 向性之蝕刻，使其在該氧化層4〇之二側形成有内凹且對 之多晶矽間隙物（Poly-Sl Spacer )46 ,該間隙物“之長Page 8 536746 V. Description of the invention (5) As the source and immortal. An oxide layer a γ having a thickness of 3000 A is deposited on the ion-doped region 38 to complete the high-density chemical vapor deposition method No. 2 30 to cover the sound of the silicon nitride. And * 话 #, the band is the space between the emulsified stone. Then, the machine and the machine = m = Yazhenman's adjacent silicon nitride layer 34. I. Dandan by chemical mechanical polishing method for horizontal scanning, the excess portion of the oxide layer 40 until the silicon nitride is exposed. Except as shown in the figure, after chemical mechanical polishing_S ,,,,, as in No. 51400A. The thickness of the polished rat fossil layer 34 is approximately as shown in Figure 6. After using chemical surface polishing to smooth, the nitrided layer emulsified layer 40 and the pad oxide layer 32 under the silicon layer 34 And go :: Month: The position of the pole part area of the suspended gate will also be distorted. At this time, the thickness of the 虱 100A 〇 lice formation layer 40 is about f '. After the surface of the silicon substrate 30 is cleaned, a tunnel dielectric layer 42 is formed on the surface of the silicon: 30. The thickness of the electric layer soil layer is about 7 GA, as shown in FIG. 7, and then the milk layer is deposited: deposition, and the first polycrystalline stone layer 44 is deposited over the stone substrate 30: The thickness of the electric layer 42 and the first-multilayer layer 44 is about as shown in FIG. 8 again. The first polycrystalline silicon layer is “etched non-directionally so that it is formed on the two sides of the oxide layer 40”. Poly-Sl Spacer 46 with recessed and opposite, the "length of the spacer"
536746 五、發明說明（6) 度約為800A lt ^ a 為儲存電荷/田曰sa你隙物46即作為懸浮閘極’以作 用該隧穿介t厗42盥作2懸沣閘極之多晶矽間隙物46係利 電性隔Γ。電層42與作為詩及源極之離子摻雜㈣开^ 最後，如第9圖所示，在矽基底3〇 層48結構，其厚度約為1〇〇A 於之積-絕緣介電 -層第二多晶轉，厚度約為=〇:緣介電層48上沈積 刻製程，完成一已定義化：利用微影及蝕 與矽基底之間的通道區域中間右不f取，使控制閑極 如此便即可％ : 子在恣浮閘極的區域。 ^】凡成一雙位兀快閃記憶體的構造。 、 上述之絶緣介電層4 8通當在气yfU *LL· =層、-氮化…常；亦可由 (〇nde NltHde_GxidefUmi 麵 ^化層 ‘上所述，本發明係兔一 日」所構成者。 物製程，來製作雙位元快閃記憶體的：：矽f浮閘極間隙 光罩製程，即可自動對準的完：署：：…、須再經過多 黃光製程申對不準的缺失· ^ 3極製程，省略習知 連續的懸浮間#，以作為雔記憶體元件中建立不 之快閃記憶體具有二電荷；存ί = ，使完成 憶體容量增加至習知快閃記憶體容量:：：極’以便將記 以上所述實施例僅係為說明 σ。 ’其目的在使熟習此項技】：：：術思想及特點 士此夠瞭解本創作之内容 第〗0頁 536746 五、發明說明（7) 並據以實施，當不能以之限定本創作之專利範圍，即大凡 依本創作所揭示之精神所作之均等變化或修飾，仍應涵蓋 在本創作之專利範圍内。536746 V. Description of the invention (6) Degree is about 800A lt ^ a is for storing charge / field gap 46 is used as suspension gate 'to act as the tunneling agent t 厗 42 as polycrystalline silicon with 2 suspension gates The spacer 46 is a galvanic spacer Γ. The electrical layer 42 is separated from the ion doping which is the poem and source. Finally, as shown in FIG. 9, the layer 30 structure on the silicon substrate 30 has a thickness of about 100 Å. The second layer is polycrystalline with a thickness of about 〇: the deposition and etch process on the edge dielectric layer 48 completes a defined process: using lithography and etching, the channel area between the silicon substrate and the silicon substrate is not f, so as to control The idle pole is so easy.%: The sub is in the area of the floating gate. ^] The structure of a pair of flash memory. The above-mentioned insulating dielectric layer 48 is connected to the gas yfU * LL · = layer, -nitriding, etc .; it can also be composed of (Onn NltHde_GxidefUmi surface layer, the present invention is a rabbit day ". For the production of dual-bit flash memory :: silicon f floating gate gap mask process, you can automatically align it: Department: ..., need to go through multiple yellow light process Quasi-missing ^ 3 pole process, omitting the conventional continuous suspension room #, as the flash memory in the memory element has two charges; storing ί =, so that the completed memory capacity is increased to the known fast Flash memory capacity ::: pole 'so that the above-mentioned embodiment is only used to explain σ.' The purpose is to familiarize yourself with this technique] ::: Technical ideas and characteristics are enough to understand the content of this creation 0Page 536746 V. Description of Invention (7) and implement it according to this. When the scope of the patent of this creation cannot be limited, that is, all equal changes or modifications made in accordance with the spirit revealed by this creation shall still be covered by the patent of this creation. Within range.
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