CN100477141C - 半导体封装器件及其制造和测试方法 - Google Patents

半导体封装器件及其制造和测试方法 Download PDF

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Publication number
CN100477141C
CN100477141C CNB028245296A CN02824529A CN100477141C CN 100477141 C CN100477141 C CN 100477141C CN B028245296 A CNB028245296 A CN B028245296A CN 02824529 A CN02824529 A CN 02824529A CN 100477141 C CN100477141 C CN 100477141C
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China
Prior art keywords
integrated circuit
pad
chip
substrate
packaged device
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Expired - Fee Related
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CNB028245296A
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Chinese (zh)
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CN1602548A (zh
Inventor
马克·A.·吉伯
肖恩·M.·奥＇康纳
特兰特·A.·汤普森
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NXP USA Inc
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Freescale Semiconductor Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07502—Connecting or disconnecting of bond wires using an auxiliary member
    • H10W72/07504—Connecting or disconnecting of bond wires using an auxiliary member the auxiliary member being temporary, e.g. a sacrificial coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/865—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/142—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/284—Configurations of stacked chips characterised by structural arrangements for measuring or testing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/291—Configurations of stacked chips characterised by containers, encapsulations, or other housings for the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/752—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Wire Bonding (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
CNB028245296A 2001-11-08 2002-10-16 半导体封装器件及其制造和测试方法 Expired - Fee Related CN100477141C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/008,800 2001-11-08
US10/008,800 US6916682B2 (en) 2001-11-08 2001-11-08 Semiconductor package device for use with multiple integrated circuits in a stacked configuration and method of formation and testing

Publications (2)

Publication Number Publication Date
CN1602548A CN1602548A (zh) 2005-03-30
CN100477141C true CN100477141C (zh) 2009-04-08

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CNB028245296A Expired - Fee Related CN100477141C (zh) 2001-11-08 2002-10-16 半导体封装器件及其制造和测试方法

Country Status (8)

Country Link
US (1) US6916682B2 (https=)
EP (1) EP1481421A2 (https=)
JP (1) JP2005535103A (https=)
KR (1) KR100926002B1 (https=)
CN (1) CN100477141C (https=)
AU (1) AU2002337875A1 (https=)
TW (1) TWI260076B (https=)
WO (1) WO2003041158A2 (https=)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG108245A1 (en) 2001-03-30 2005-01-28 Micron Technology Inc Ball grid array interposer, packages and methods
JP2003243604A (ja) * 2002-02-13 2003-08-29 Sony Corp 電子部品及び電子部品の製造方法
US6906415B2 (en) * 2002-06-27 2005-06-14 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor devices and methods
US7573136B2 (en) * 2002-06-27 2009-08-11 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor device components
US6964881B2 (en) * 2002-08-27 2005-11-15 Micron Technology, Inc. Multi-chip wafer level system packages and methods of forming same
US7071545B1 (en) * 2002-12-20 2006-07-04 Asat Ltd. Shielded integrated circuit package
JP3867796B2 (ja) * 2003-10-09 2007-01-10 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
JP4556023B2 (ja) * 2004-04-22 2010-10-06 独立行政法人産業技術総合研究所 システムインパッケージ試験検査装置および試験検査方法
TWI270953B (en) * 2005-08-17 2007-01-11 Advanced Semiconductor Eng Substrate and testing method thereof
KR100690246B1 (ko) * 2006-01-10 2007-03-12 삼성전자주식회사 플립 칩 시스템 인 패키지 제조 방법
US8410594B2 (en) * 2006-01-11 2013-04-02 Stats Chippac Ltd. Inter-stacking module system
US20080251901A1 (en) * 2006-01-24 2008-10-16 Zigmund Ramirez Camacho Stacked integrated circuit package system
DE102006017059B4 (de) * 2006-04-11 2008-04-17 Infineon Technologies Ag Halbleiter-Bauelement-System, sowie Verfahren zum Modifizieren eines Halbleiterbauelements
JP3942190B1 (ja) * 2006-04-25 2007-07-11 国立大学法人九州工業大学 両面電極構造の半導体装置及びその製造方法
KR100782774B1 (ko) * 2006-05-25 2007-12-05 삼성전기주식회사 Ｓｉｐ 모듈
JP4930699B2 (ja) * 2006-12-06 2012-05-16 凸版印刷株式会社 半導体装置
US7973310B2 (en) * 2008-07-11 2011-07-05 Chipmos Technologies Inc. Semiconductor package structure and method for manufacturing the same
SG10201505279RA (en) 2008-07-18 2015-10-29 Utac Headquarters Pte Ltd Packaging structural member
US8742603B2 (en) * 2010-05-20 2014-06-03 Qualcomm Incorporated Process for improving package warpage and connection reliability through use of a backside mold configuration (BSMC)
US8664540B2 (en) * 2011-05-27 2014-03-04 Taiwan Semiconductor Manufacturing Company, Ltd. Interposer testing using dummy connections
US9472533B2 (en) * 2013-11-20 2016-10-18 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming wire bondable fan-out EWLB package
DE112015007224B4 (de) * 2015-12-23 2022-06-30 Intel Corporation Umgekehrt montiertes Gull-Wing Elektronikgehäuse
US9721881B1 (en) 2016-04-29 2017-08-01 Nxp Usa, Inc. Apparatus and methods for multi-die packaging
US20180190776A1 (en) * 2016-12-30 2018-07-05 Sireesha Gogineni Semiconductor chip package with cavity
KR102886060B1 (ko) * 2022-11-22 2025-11-12 앱솔릭스 인코포레이티드 패키징 기판 및 이를 포함하는 반도체 패키지

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5239198A (en) * 1989-09-06 1993-08-24 Motorola, Inc. Overmolded semiconductor device having solder ball and edge lead connective structure
US5795799A (en) * 1995-05-31 1998-08-18 Nec Corporation Method for manufacturing electronic apparatus sealed by concave molded resin enveloper
US5821762A (en) * 1994-02-28 1998-10-13 Mitsubishi Denki Kabushiki Kaisha Semiconductor device, production method therefor, method for testing semiconductor elements, test substrate for the method and method for producing the test substrate
US5973392A (en) * 1997-04-02 1999-10-26 Nec Corporation Stacked carrier three-dimensional memory module and semiconductor device using the same

Family Cites Families (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2439478A1 (fr) * 1978-10-19 1980-05-16 Cii Honeywell Bull Boitier plat pour dispositifs a circuits integres
US4729061A (en) * 1985-04-29 1988-03-01 Advanced Micro Devices, Inc. Chip on board package for integrated circuit devices using printed circuit boards and means for conveying the heat to the opposite side of the package from the chip mounting side to permit the heat to dissipate therefrom
JPH0821672B2 (ja) 1987-07-04 1996-03-04 株式会社堀場製作所 イオン濃度測定用シート型電極の製造方法
JP2585006B2 (ja) * 1987-07-22 1997-02-26 東レ・ダウコーニング・シリコーン株式会社 樹脂封止型半導体装置およびその製造方法
US5219795A (en) * 1989-02-07 1993-06-15 Fujitsu Limited Dual in-line packaging and method of producing the same
US5172303A (en) * 1990-11-23 1992-12-15 Motorola, Inc. Electronic component assembly
US5383269A (en) * 1991-09-03 1995-01-24 Microelectronics And Computer Technology Corporation Method of making three dimensional integrated circuit interconnect module
US5468994A (en) 1992-12-10 1995-11-21 Hewlett-Packard Company High pin count package for semiconductor device
US5291062A (en) * 1993-03-01 1994-03-01 Motorola, Inc. Area array semiconductor device having a lid with functional contacts
US5679978A (en) 1993-12-06 1997-10-21 Fujitsu Limited Semiconductor device having resin gate hole through substrate for resin encapsulation
US5747874A (en) * 1994-09-20 1998-05-05 Fujitsu Limited Semiconductor device, base member for semiconductor device and semiconductor device unit
US5998864A (en) 1995-05-26 1999-12-07 Formfactor, Inc. Stacking semiconductor devices, particularly memory chips
WO1996041378A1 (en) 1995-06-07 1996-12-19 The Panda Project Semiconductor die carrier having double-sided die attach plate
JPH0917919A (ja) 1995-06-29 1997-01-17 Fujitsu Ltd 半導体装置
US5798564A (en) * 1995-12-21 1998-08-25 Texas Instruments Incorporated Multiple chip module apparatus having dual sided substrate
US5843808A (en) 1996-01-11 1998-12-01 Asat, Limited Structure and method for automated assembly of a tab grid array package
KR0179921B1 (ko) * 1996-05-17 1999-03-20 문정환 적측형 반도체 패키지
US5723907A (en) * 1996-06-25 1998-03-03 Micron Technology, Inc. Loc simm
US6225688B1 (en) 1997-12-11 2001-05-01 Tessera, Inc. Stacked microelectronic assembly and method therefor
US5994166A (en) * 1997-03-10 1999-11-30 Micron Technology, Inc. Method of constructing stacked packages
US5815372A (en) * 1997-03-25 1998-09-29 Intel Corporation Packaging multiple dies on a ball grid array substrate
US5963429A (en) * 1997-08-20 1999-10-05 Sulzer Intermedics Inc. Printed circuit substrate with cavities for encapsulating integrated circuits
JPH11219984A (ja) 1997-11-06 1999-08-10 Sharp Corp 半導体装置パッケージおよびその製造方法ならびにそのための回路基板
US6133067A (en) * 1997-12-06 2000-10-17 Amic Technology Inc. Architecture for dual-chip integrated circuit package and method of manufacturing the same
FR2772516B1 (fr) * 1997-12-12 2003-07-04 Ela Medical Sa Circuit electronique, notamment pour un dispositif medical implantable actif tel qu'un stimulateur ou defibrillateur cardiaque, et son procede de realisation
JP2000208698A (ja) * 1999-01-18 2000-07-28 Toshiba Corp 半導体装置
JP3939429B2 (ja) * 1998-04-02 2007-07-04 沖電気工業株式会社 半導体装置
US6184463B1 (en) * 1998-04-13 2001-02-06 Harris Corporation Integrated circuit package for flip chip
US6329713B1 (en) * 1998-10-21 2001-12-11 International Business Machines Corporation Integrated circuit chip carrier assembly comprising a stiffener attached to a dielectric substrate
JP3512657B2 (ja) 1998-12-22 2004-03-31 シャープ株式会社 半導体装置
US6201302B1 (en) 1998-12-31 2001-03-13 Sampo Semiconductor Corporation Semiconductor package having multi-dies
JP3235589B2 (ja) 1999-03-16 2001-12-04 日本電気株式会社 半導体装置
TW409330B (en) 1999-03-20 2000-10-21 United Microelectronics Corp Repairable multi-chip module package
JP3576030B2 (ja) * 1999-03-26 2004-10-13 沖電気工業株式会社 半導体装置及びその製造方法
US6117704A (en) * 1999-03-31 2000-09-12 Irvine Sensors Corporation Stackable layers containing encapsulated chips
JP3575001B2 (ja) * 1999-05-07 2004-10-06 アムコー テクノロジー コリア インコーポレーティド 半導体パッケージ及びその製造方法
JP2001077301A (ja) * 1999-08-24 2001-03-23 Amkor Technology Korea Inc 半導体パッケージ及びその製造方法
JP3418759B2 (ja) * 1999-08-24 2003-06-23 アムコー テクノロジー コリア インコーポレーティド 半導体パッケージ
JP2001077293A (ja) * 1999-09-02 2001-03-23 Nec Corp 半導体装置
JP2001094045A (ja) * 1999-09-22 2001-04-06 Seiko Epson Corp 半導体装置
JP3485507B2 (ja) * 1999-10-25 2004-01-13 沖電気工業株式会社 半導体装置
US6344687B1 (en) * 1999-12-22 2002-02-05 Chih-Kung Huang Dual-chip packaging
SG100635A1 (en) * 2001-03-09 2003-12-26 Micron Technology Inc Die support structure
SG108245A1 (en) * 2001-03-30 2005-01-28 Micron Technology Inc Ball grid array interposer, packages and methods
US6787916B2 (en) * 2001-09-13 2004-09-07 Tru-Si Technologies, Inc. Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5239198A (en) * 1989-09-06 1993-08-24 Motorola, Inc. Overmolded semiconductor device having solder ball and edge lead connective structure
US5821762A (en) * 1994-02-28 1998-10-13 Mitsubishi Denki Kabushiki Kaisha Semiconductor device, production method therefor, method for testing semiconductor elements, test substrate for the method and method for producing the test substrate
US5795799A (en) * 1995-05-31 1998-08-18 Nec Corporation Method for manufacturing electronic apparatus sealed by concave molded resin enveloper
US5973392A (en) * 1997-04-02 1999-10-26 Nec Corporation Stacked carrier three-dimensional memory module and semiconductor device using the same

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KR100926002B1 (ko) 2009-11-09
CN1602548A (zh) 2005-03-30
EP1481421A2 (en) 2004-12-01
US20030085463A1 (en) 2003-05-08
TW200300283A (en) 2003-05-16
KR20050037430A (ko) 2005-04-21
AU2002337875A1 (en) 2003-05-19
JP2005535103A (ja) 2005-11-17
US6916682B2 (en) 2005-07-12
WO2003041158A2 (en) 2003-05-15
WO2003041158A3 (en) 2003-10-23
TWI260076B (en) 2006-08-11

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