TWI260076B - Semiconductor package device and method of formation and testing - Google Patents

Semiconductor package device and method of formation and testing Download PDF

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Publication number
TWI260076B
TWI260076B TW091132762A TW91132762A TWI260076B TW I260076 B TWI260076 B TW I260076B TW 091132762 A TW091132762 A TW 091132762A TW 91132762 A TW91132762 A TW 91132762A TW I260076 B TWI260076 B TW I260076B
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Taiwan
Prior art keywords
integrated circuit
pads
circuit
depositing
package substrate
Prior art date
Application number
TW091132762A
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English (en)
Other versions
TW200300283A (en
Inventor
Mark A Gerber
Connor Shawn M O'
Trent A Thompson
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Freescale Semiconductor Inc
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Publication of TW200300283A publication Critical patent/TW200300283A/zh
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Publication of TWI260076B publication Critical patent/TWI260076B/zh

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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Wire Bonding (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

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0) !26〇〇76 玖、發明說明 、内容、實施方式及圖式簡單說明) (發明說《敘明：發_叙技術領域、先前技術 請=::=°1年"…在美國”為專利_ 技術領1 而更特定言之，係 本發明通常係關於半導體封裝裝置， 關於形成與測試半導體封裝裝置的方法 先前拮術 在封裝積體電路中，於封裝巾提供允許多個晶粒的封裳 工爻付更加要。測試此等多晶粒封裝也隨著晶粒的複 雜度增加”得更加_。而且，對於某些多晶片封裳， :多晶片封裴中剩下的一個或更多晶粒中，電氣地屏蔽多 ，片封裝中的-個或更多晶粒是重要的。也希望在形成多 曰曰片封兢的製造過程期間允許修改。由於目前電路板技術 的限制，也希望有較低外形的多晶片封裝。 圖式簡單說明 本赉月藉由貝例的方式說明，並且不受限於附圖，其中 相似的麥考數字指示類似的元件，而其中·· 圖1〜12包含根據本發明之一具體實施例所形成之封裝妒 置的連續剖面圖說明；及 圖1 3〜23包含根據本發明之另一具體實施例所形成之 裝裝置的連續剖面圖說明。 、 熟諳此藝之士將了解附圖中的元件係為了簡單與清楚戈 明，並不需要按照大小繪製。舉例來說，附圖中的—此一 81469-941104.doc (2) 1260076
以幫助改善本發明之 件的尺寸相對於其他元件可以誇大， 各種具體實施例的了解。 使用基板中的空腔以承受至少複數個晶粒之 個晶粒的堆疊允許使用較低外形的封裝裝置。此外，万 二在超過封«置之-個側面上放置用於測試目的的補
墊。而且’在複數個晶粒之間的層，可以用來提供所造 擇之晶粒之間的電氣屏蔽。參照附圖，會對本發明有輕 佳的了解。
圖1說明具有-空腔20之封裳裝置10,其係根據本發明之 一具體實施例。封裝裝置1G包含—封裝基板12，其具有一 表面50與一表面52。注意表面5〇由第一平面所組成，而表 7 52則由第二平面所組成。在頂部，基板12包含一個或更 多個結合指14與一個或更多個襯墊16。在本發明之一具體 實施例中，襯墊16是導電的，並且可以用於多種目的。舉 例來說，襯墊16可以用來安裝不連續的裝置，可以用來接 党測試目的的探針，或是可以用來接受導電的互連（如焊接 球狀物）。圖1說明施加於基板12之表面52的膠帶層18。在 本發明之一具體實施例中，基板12包含電氣導體，如用來 互連一個或更多個晶粒到外部接觸（未顯示）的跡線與通道。 圖2說明封裝裝置1〇之一具體實施例，其中已經在膠帶18 上面放置晶粒附著材料24。接著將晶粒22放在晶粒附著材 料24的頂部。本發明之另一具體實施例可以不使用晶粒附 著材料24 ’而直接將晶粒22黏附於膠帶1 8。膠帶1 8係用作 81469-941104.doc !26〇〇76
(3) 支持晶粒22的支持組件，以及視情況作為晶粒附著材料24 。膠帶18可以延伸或不延伸基板12的整個表面52。 圖3說明封裝裝置10之一具體實施例，其中晶粒22已經 經由電線結合26,電氣地連接到結合指14。本發明之另一 具體實施例可以使用任何數目的電線結合26與結合指14
圖4說明封裝裝置10之一具體實施例，其中已經在晶粒22 電線…a 26，與結合指14上面，沈積封膠材料。注意 封膠材料28可以是適於積體電路之任何類型的材料，舉例 來說，如模塑塑膠或液體沈積球狀材料。 圖5說明封裝裝置1〇之一具體實施例，其中膠帶18已經從 基板12之底部表面52移除。 圖6說明封裝農置1〇之一具體實施例，其中已經放置晶粒 附著材料30以將晶粒32黏附於封裝裝置1〇。在一具體實施 例中，晶粒附著材料3〇係放置於晶粒附著材料24與晶粒32 之間。在另一具體實施例中，當沒有使用晶粒附著材剩 ntfc . R 山l a丄
時，晶粒附著材料30係放在晶粒22與晶粒32之間。注清 本發明之一具體實施例中，封裝裝置1〇可以在處理過浪 的此點上反轉，使得底部表面52現在變成頂部表面52， 頂7表面50現在變成底部表面50。可是，本發明之其制 體實施^在其形成期間，可以將封裝裝置1G轉向成任々 弋可疋為了簡單起見，在剩下的全部附圖中，封裝身 10將以相同的方向顯示。 圖7說明封裳裝置10之一具體實施例，其中晶粒32已衾 81469-941104.doc (4) (4)1260076
由電線結合34，電氣地連接到結合指14。本發明之其他具 紐只施例可以使用任何數目的電線結合“與結合指1 *。對 於使用浮動晶片技術之本發明的具體實施例，晶粒％可以 不具電線結合34,而經由表面52f氣地連接。 圖8次明封裝裝置丨〇之一具體實施例，其中已經放置晶粒 附著材料36以將晶粒38黏附於晶粒32。在一具體實施例中 曰曰粒附著材料36係放置於晶粒32與晶粒％之間。在使用 浮動曰曰技術的另—具體實施例中，沒有使用晶粒附著材 料36，而疋使用已知的浮動晶片技術，將晶粒”直接電氣 地連接於晶粒32。 圖9说明封裝裝置1〇之一具體實施例，其中晶粒列已經 經由電線結合42電氣地連接到結合指14，而晶粒38則經 由電線結合40連接到晶粒32。本發明之其他具體實施例 可以使用任何數目的電線結合4 〇與4 2，以及任何數目的 結合札14。對於使用浮動晶片技術之本發明的具體實施 例，晶粒38可以不具電線結合42，而直接電氣地連接到 晶粒3 2。 圖10說明封裝裝置1〇之一具體實施例，其中說明測試探 針4 4以顯示可以電氣地測試晶粒η，3 2，與3 8之一或更多 個的情況。ί主意在本發明之另一具體實施例中，測試探針 44可以僅使用位於基板12之頂部表面5〇，基板12之底部表 面52上之一個或更多個襯墊16，或基板12之頂部與底部表 面50，52兩者上面之一個或更多個襯墊16。注意在本發明 的一些具體實施例中，允許測試探針近接基板12之底部表 81469-941104.doc (5) 1260076 U部表面52是明„益的。舉㈣說，這允許測試 近接更多襯墊16’因而在測試過程中，允許使用更 夕。^。而且，允許測試探針料近接基板^之頂部與底部 表面5立〇, 52，能夠較容易近接每個單獨的晶粒22, 32與38 庄思在封裝中使用多晶粒時，測試所需之概塾b數目可 能明顯較高。 圖明封裝裝置咐—具體實施例，其中已經在晶粒 38日日粒32 ’與結合指14上面’沈積封膠材料料。注意在 本發明之其他具體實施例中，可以在基板12之較大部分上 沈積封裝材料46。舉例來說，在本發明之-些具體實施例 中’封夥材料46也可以沈積於襯塾16上面。無論概塾似 否被封夥材料46封裝’襯塾16可以用來電氣地麵合不連續 裝置到晶粒22,32，與38之一或更多個。注意封裝材㈣ 可以是適於積體電路之任何類型的材料’舉例來說，如模 塑塑膠或液體沈積球狀材料。 圖12说明封裝裝置1G之—具體實施例，其中已經在表面 5〇的襯塾16上面，放置導電互料。在本發明之一且體實 施例中’導電互連48可以是焊接球狀物。可是，在本發明 之其他具體實施例中’導電互連48可以是以任何方式形成 之任何類型的電氣導電材料。注意導電互連48的選擇性的 在本發明之—些具體實施例中，如果封膠材料28流溢於 基板12之頂部表面50 ’則可以不需要導電互連48,而可以 使電氣連接直接連到基板12之表面5〇上的襯塾…再次注 意基板12中的跡線與通道（未顯示）係用來選擇性地互連基 81469-941104.doc -10- 1260076
板12的各個部分。也注意晶粒附著材料24，30與36可以是 任何類型的適當材料，舉例來說，如膠帶或非固體黏膠（如 膠，％氧基樹脂）。晶粒22，32與3 8可以是任何類型的積體 電路，半導體裝置，或其他類型的電氣有源基板。本發明 之其他具體實施例可以使用封裝於封裝裝置1〇中任何數目 的晶粒22，32或38。舉例來說，其他具體實施例可以只將 兩個晶粒封裝於封裝裝置1〇中。注意晶粒22，32的大小與 縱橫比可以變化，而且可以在晶粒之間使用晶粒隔片（未顯 示）。注意晶粒22係位於空腔20中，而晶粒32與晶粒38則是 位於空腔20外面。 圖13說明具有一空腔120之封裝裝置1〇〇，其係根據本發 明之一具體實施例。封裝裝置丨〇〇包含一封裝基板丨丨2，其 具有一表面150與一表面152。注意表面15〇由第一平面所組 成而表面1 5 2則由弟一平面所組成。在頂部，基板112包 含一個或更多個結合指114與一個或更多個襯墊丨丨6。在本 發明之一具體實施例中，襯墊116是導電的，並且可以用於 多種目的。舉例來說，襯墊i 16可以用來安裝不連續的装置 ’可以用來接受測試目的的探針，或是可以用來接受導電 的互連（如焊接球狀物）。圖13說明層1〇1是基板112的一部份 ，其外表面是表面丨52。在本發明之一具體實施例中，層i 〇工 包含支持組件Π9，一個或更多個結合指114，與一個或更 多個襯墊11 6。本發明之另一具體實施例可以不需要結人指 114 (如’使用浮動晶片技術時），以及不要電氣地連接到著 面1 5 2日$，可以不需要襯塾11 6。在本發明之一具體實施例 81469-941104.doc -11 - 1260076
⑺ 中，基板112包含電氣導體，如用來互連一個或更多個晶粒 到外部接觸（未顯示）的跡線與通道。 圖14說明封裝裝置ι〇〇之一具體實施例，其中已經在支持 組件119上面放置晶粒附著材料124。接著將晶粒122放在晶 粒附著材料124的頂部。
圖15說明封裝裝置1〇〇之一具體實施例，其中晶粒122已 經經由電線結合126，電氣地連接到結合指114。本發明之 另一具體實施例可以使用任何數目的電線結合丨26與結合 指114 °對於使用浮動晶片技術之本發明的具體實施例，晶 Ψ 12 2 了以不具電線結合12 6，而經由層1 〇 1，直接電氣地連 接0 圖16說明封裝裝置1〇〇之一具體實施例，其中已經在晶 122，電線結合126，與結合指114上面，沈積封膠材料工 。注意封膠材料128可以是適於積體電路之任何類型的材 ，舉例來說，如模塑塑膠或液體沈積球狀材料。
圖1 7。兒明封裝裝置i 〇〇之一具體實施例，其中已經放置 =附著材料13〇以將晶粒132黏附於封裝裝置丨〇〇。在一具 貝鉍例中，晶粒附著材料1 3〇係放置於層101與晶粒1 32之 。注意在本發明之—具體實施例巾，封裝裝置1G0可以在; 理過程中的此點上反轉，使得底部表面152現在變成頂部: 面152❿頂部表面15〇現在變成底部表面bo。可是，本; 明之其他具體實施例在其形成期間，可以將封裝裝置1( 轉向成任何形式。為了簡單起見，在剩下的全部附圖中 封裝裝置HK)將以相同的方向顯示。 81469-941104.doc -12- 1260076 圖1 8說明m 、、羞置loo之一具體實施例，其中晶粒132已 經經由電綠4士人1 、σ δ 3 4 ’電氣地連接到結合指〗丨4。本發明之 其他呈, 一 μ⑦列可以使用任何數目的電線結合134與結合 指114。對於祛田、、心去 、， 令動晶片技術之本發明的具體實施例，晶 ； 可X不具電線結合134，而經由表面152電氣地連接。 、回“兒月封裝裝置i 00之一具體實施例，其中已經放置晶 ♦附著材料136以將晶粒138黏附於晶粒132。在—具體實施 中曰曰粒附著材料136係放置於晶粒132與晶粒138之間。 在，用浮動晶片技術的另—具體實施例中，沒有使用晶粒 附者材料136 ;而是使用已知的浮動晶片技術，將晶粒138 直接電氣地連接於晶粒13 2。 S 2 0 X»兒月封裝裝置j⑼之一具體實施例，其中晶粒13 $已 、、二紅由電線結合142電氣地連接到結合指丨14，而晶粒則 、’二由電線、纟σ合14〇連接到晶粒132。本發明之其他具體實施 例可以使用任何數目的電線結合14〇與142，以及任何數目 的結合指11 4。對於使用浮動晶片技術之本發明的具體實施 例，晶粒13 8可以不具電線結合142，而直接電氣地連接到 晶粒1 3 2。 圖2 1說明封裝裝置1 〇〇之一具體實施例，其中說明測試探 針144以顯示可以電氣地測試晶粒122，132，與138之一或 更多個的情況。注意在本發明之另一具體實施例中，測試 楝針144可以僅使用位於基板1丨2之頂部表面150，基板U2 之底部表面152之一個或更多個襯墊116，或基板112之頂部 與底部表面150，152兩者上面的襯墊116。注意在本發明的 81469-941104.doc -13 - (9) 1260076
一些具體實施例中，允許測試探針近接基板ιΐ2之底部表面 =0與底4表面152是明顯有益的。舉例來說，這允許測試 ^十144近接更多襯墊116，因而在測試過程中，允許使用 更f信號H，允許測試探針144近接基板112之頂部與 底口P表面150 ’ 152 ’能夠較容易近接每個單獨的晶粒122
，132與138。注意在封裝中使用多晶粒時，測試所需之槪 墊116數目可能明顯較高。 具體實施例，其中已經在晶粒 圖22說明封裝裝置1〇〇之一
138 θ曰粒132 ’與結合指114上面，沈積封膠材料146。注 意在本發明之其他具體實施例中，可以在基板u2之較大部 分上沈積封裝材料146。舉例來說’在本發明之一些具體實 施例中’封膠材料146也可以沈積於概墊116上面。無論概 塾116疋否被封膠材料146封裝，襯塾116可以用來電氣地耗 合不連績裝置到晶粒122, 132，與138之一或更多個。注意 封裝材料146可以是適於積體電路之任何類型的材料，舉例 來說，如模塑塑膠或液體沈積球狀材料。 圖23說明封裝裝置1〇〇之一具體實施例，其中已經在表面 150的襯墊116上面，放置導電互連148。在本發明之一具體 實施例中，導電互連148可以是焊接球狀物。可是，在本發 明之其他具體實施例中，導電互連148可以是以任何方式形 成之任何類型的電氣導電材料。注意導電互連148的選擇性 的。在本發明之一些具體實施例中，如果封膠材料128流溢 於基板112之頂部表面150,則可以不需要導電互連148,而 可以使電氣連接直接連到基板丨丨2之表面丨5 〇上的襯墊丨i 6 81469-941104.doc -14- 1260076
(1UJ 。再次注意基板i i2中的跡線與通道（未顯示）係用來選擇性 地互連基板1〗2的各個部分。也注意晶粒附著材料124，】刊 與136可以是任何類型的適當材料，舉例來說，如膠帶或非 固體黏膠（如膠，環氧基樹脂）。晶粒122 , 132與138可以是 任何類型的積體電路，半導體裝置，或其他類型的電氣： 源基板。本發明之其他具體實施例可以使用封裝於封裝裝 置1〇〇中任何數目的晶粒122, 132或138。舉例來說，其他 :體實施例可以只將兩個晶粒封裝於封裝裝置ι〇〇中。注意 曰曰粒122 ’ 132及138的大小與縱橫比可以變化，而且可以在 晶粒之間使用晶粒隔片（未顯示）。注意晶粒122係位於空腔 〇中而日日粒132與晶粒138則是位於空腔12〇外面。 在前述專㈣明書巾，已經參考特定具體實施例敘述本 發明。可是’原本熟諳此藝之士將了解可以做各種修改與 改Μ ’而不脫離如下列申請專利範圍所陳述之本發明的範 =舉例來說’在封震裝置1〇與1〇〇的形成中，可以使用技 2已知之任何適當的晶粒黏附過程，電線結合過程，與 膠帶層過程。因此，專利％ , 寻引次明書與附圖應當做說明，而不 2制之思’而傾向於在本發明之範圍内，包含所有此等 對於特定具體實施例’已經敛述對問題的好處，复 ’與解決方法’而可能造成任何好處，優點或解決 方法％生或變得更顯著的任何元件，並未當作任何申請專 ^ 次不可或缺的特點或元件。 圖式元件符號說明 1 051 00 封裝裝置 8l469-941104.doc > 15 - 1260076 οι) 20,120 空腔 12,112 封裝基板 50,52，150，152 表面 14，114，134 結合指 16,116 襯墊 18 膠帶層 24,30,36，124，130 晶粒附者材料 22,32,38，122，132，138 晶粒 26,40,54,126 電線結合 28?46?128?146 封膠材料 44，144 測試探針 48,148 導電互連 101 層 119 支持組件 81469-941104.doc -16-

Claims (1)

126001^091132762號專利申請案 5月） 史請寺科鹌圍替換夺(95年 ”!_'ϊ ,二7「’Ί.. 拾、申請專利範圍 1· 一種形成一封裝裝置之方法，包括： 提供一封裝基板，其具有一第一側及一第二側，且具 有位於該第一側之多個第一襯墊及位於該第二側之多 個第二襯墊； 將一第一積體電路放置在該第一側及將一第二積體 電路放置在一第二側，其中晶粒附著材料被插入該第一 積體電路與該第二積體電路之間； 將該第一積體電路電氣連接至該等第一襯墊且將該 第二積體電路電氣連接至該等第二襯墊；以及 藉由施加測試探針於該等第一襯墊及該等第二襯替 以測試該第一積體電路與該第二積體電路， 其中至少一第一襯墊電氣獨立於所有第二襯墊，及其 中封膠材料並非位於至少一觀塾上方。 2·如申請專利範圍第1項之方法，其中該附著步驟之進一 步特徵為： 在將該第二積體電路放置於該第二側前將該第一積 體電路放置於該第一側。 3·如申請專利範圍第2項之方法，其中該電氣連接步驟之 進一步特徵為： 在將該第二積體電路電氣連接至該等第二襯墊前將 該第一積體電路電連接至該等第一襯塾。 4. 一種形成一封裝裝置之方法，包括： 提供一封裝基板，其具有一沿著一第一平面之第一表
1260076 面及一沿著一第二平面之第二表面； 其中該封裝基板在該第一平面與該第二平面間具有 一空腔，且其中該封裝基板於該第_表面上具有多個第 一概塾且於該第二表面上具有多個第二襯墊； 將一第一積體電路放置於空腔中； 將一第一積體電路放置於鄰接空腔外面之第一積體 電路，使得晶粒附著材料被插入該第一積體電路與該第 二積體電路之間； 在該第一積體電路與該第二積體電路上沈積封膠材 料； ’ 將該第一積體電路電氣連接至該等第一襯墊且將該 第二積體電路電氣連接至該等第二襯墊；以及 藉由施加多個測試探針於該等第一襯墊及該等第二 襯墊以測試該第一積體電路與該第二積體電路， 其中至少一第一襯墊電氣獨立於所有第二襯墊，及其 中該封膠材料並非位於至少一襯墊上方。 5.如申請專利範圍第4項之方法，其中沈積步驟包含： 在放置该第二積體電路步驟前將該封膠材料之第一 部份沈積於該第一積體電路之上；以及 將該封膠材料之第二部份沈積於該第二積體電路之 上。 6 ·如申請專利範圍第5項之方法，進一步包含： 在沈積該封膠材料之第二部份之步驟前將一第三積 體電路放置於鄰接該第二積體電路處。 、 -2- 14. 15. 1260076 7.如申請專利範圍第6項之方法，其中該第三積體電路係 以至少部份位於該第一積體電路與該第二積體電路中 至少一者上方之方式堆疊。 8·=申^專利範圍第5項之方法，其中沈積該封膠材料之 第"卩份之步驟包括轉換模塑該封膠材料，且其中沈積 、>材料之第二部分的步驟包括轉換模塑該封膜 料。 ’ 9·如申明專利||圍第4項之方法，其中該封裝基板進一步 包括該第一表面上的多個第一結合指與第二表面上的 多個第二結合指。 10·如申明專利|已圍第9項之方法，其中該電氣連接該第一 積體電路步驟包括電線結合。 "·如申請專利範圍第4項之方法，其中該封裝基板進一步 包括一沿著該基板之第二平面的支持組件。 12·如：明專利範圍第11項之方法，其中該支持組件係位於 該第一積體電路與該第二積體電路之間。 13.如申請專利範圍第12項之方法，其中該支持組件可導 電。 月專利k圍第1 1項之方法，進一步包括在放置該第 -積體電路的步驟之前’移除該支持組件。 :申請專利範圍第14項之方法，其中該支持組件是膝 ^rjT 0 16. —種形成一封裝裝置之方法，包括： 提供—封襄基板，其具有—沿著一第一平面之第一表
-3 - 1260076 面及一沿者一第二平面之第二表面，苴中唁 該第-平面與該第二平面間具有—空腔基板在 將一第一積體電路放置於該空腔中； 將一第二積體電路放置於鄰接空腔外面之 電路，使得-支持組件被插入該第一積體電路二： 積體電路之間；以及 ^ μ $ — 在該第-積體電路與該第二積體電路上沈積封 料； ’
其中该封裝基板並非由封膠材料所形成，且其中該沈 積步驟包括： ' ~ ~ 在放置該第二積體電路步驟前將該封膠材料之第一 部份沈積於該第一積體電路之上；以及 將該封膠材料之第二部份沈積於該第二積體電路之 上， 其中該方法進一步包括在沈積該封膠材料之第二部 份的步驟前將一第三積體電路放置於鄰接該第二積體 電路處，
其中該方法進一步包括： 將該第一積體電路電氣連接至多個第一襯墊，其中該 等第一襯墊位於該第一表面； 將該第二積體電路電氣連接至多個第二襯墊，其中該 等第二襯墊位於該第二表面；以及 藉由施加多個測試探針於該等第一襯墊及該等第二 襯墊以測試該第一積體電路與該第二積體電路。 -4- 1260076 17. -種形成—封裝裝置之方法，包括. 提供一封裝基板，其具有-第一側及 在该第一側提供多個第—襯墊； 在該第二側提供多個第二襯墊； =供-安裝於該封裝基板之第一積體電路； ^共一*裝於該封裝基板之第二積體電路；以及 七供-鄰接於該第二積體電路之第三積 其中該第一積體電 、 ， M 路電氧連接至該等第一输孰 弟二積體電路電氣連接至該等第二襯墊， 且該 其中該等第—襯塾與該等第二襯墊之進— 於可用於容納測試探針以供測試，以及 、徵 其中該等第-襯藝與該等第 膠材料所覆蓋且祐具·〜 i之者不破 18如申-糞^ 谷納該等測試探針之-。 之方法，其t該基板之進 工腔且該第一積體電路之進一牛转： 位於該空腔内。 V特徵為 專利範圍第18項之方法，其”第二積 曰由黏附晶粒附著膠帶安裝於基板。 、電路係 20.如申請專利範圍第19項之方法， 鄰接於該第二積體電路。 ^㈣-積體電路係 μ 21·如申請專利範圍第綱之方法，進一 弟一積體電路與該第二積 乂已括於 22.如申請專利範圍第21項之方法，= 粒附著材料。 ^支持組件包括 第二側 修 在 封 該 -5-
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AU2002337875A1 (en) 2003-05-19
WO2003041158A3 (en) 2003-10-23
US6916682B2 (en) 2005-07-12
WO2003041158A2 (en) 2003-05-15
CN100477141C (zh) 2009-04-08
EP1481421A2 (en) 2004-12-01
TW200300283A (en) 2003-05-16
KR100926002B1 (ko) 2009-11-09
KR20050037430A (ko) 2005-04-21
JP2005535103A (ja) 2005-11-17
CN1602548A (zh) 2005-03-30

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