BR112021021424A2 - Dispositivo semicondutor - Google Patents

Dispositivo semicondutor

Info

Publication number
BR112021021424A2
BR112021021424A2 BR112021021424A BR112021021424A BR112021021424A2 BR 112021021424 A2 BR112021021424 A2 BR 112021021424A2 BR 112021021424 A BR112021021424 A BR 112021021424A BR 112021021424 A BR112021021424 A BR 112021021424A BR 112021021424 A2 BR112021021424 A2 BR 112021021424A2
Authority
BR
Brazil
Prior art keywords
semiconductor device
transistors
insulating layers
subchains
vertical direction
Prior art date
Application number
BR112021021424A
Other languages
English (en)
Inventor
Gonglian Wu
Qiguang Wang
Original Assignee
Yangtze Memory Tech Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yangtze Memory Tech Co Ltd filed Critical Yangtze Memory Tech Co Ltd
Publication of BR112021021424A2 publication Critical patent/BR112021021424A2/pt

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28238—Making the insulator with sacrificial oxide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)
  • Element Separation (AREA)

Abstract

dispositivo semicondutor. a presente invenção refere-se a um dispositivo semicondutor (100) e a um método para fabricar o dispositivo semicondutor (100). o dispositivo semicondutor (100) inclui uma cadeia de transistores (102) empilhada em uma direção vertical (103) sobre um substrato (101) do dispositivo semicondutor (100) tendo uma estrutura de canal (165) que se estende na direção vertical (103). a cadeia de transistores (102) inclui primeira, segunda, e terceira subcadeias (102(1), 102(2), 102(3)) de transistores que são dispostas ao longo de primeira, segunda, e terceira porções (165(1), 165(2), 165(3)) da estrutura de canal (165), respectivamente. estruturas de porta (153b-153q) de transistores nas primeira, segunda, e terceira subcadeias (102(1), 102(2), 102(3)) são separadas por respectivas primeira, segunda, e terceiras camadas isolantes (124, 224, 324) e as segundas camadas isolantes (224) têm uma taxa de corrosão mais elevada do que aquela das terceiras camadas isolantes (324).
BR112021021424A 2019-06-28 2019-06-28 Dispositivo semicondutor BR112021021424A2 (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2019/093603 WO2020258224A1 (en) 2019-06-28 2019-06-28 Methods of semiconductor device fabrication

Publications (1)

Publication Number Publication Date
BR112021021424A2 true BR112021021424A2 (pt) 2022-01-04

Family

ID=72007155

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112021021424A BR112021021424A2 (pt) 2019-06-28 2019-06-28 Dispositivo semicondutor

Country Status (10)

Country Link
US (3) US11183508B2 (pt)
EP (1) EP3909069A4 (pt)
JP (1) JP7422168B2 (pt)
KR (1) KR102611810B1 (pt)
CN (1) CN111557047B (pt)
AU (1) AU2019455154B2 (pt)
BR (1) BR112021021424A2 (pt)
SG (1) SG11202111703YA (pt)
TW (1) TWI700835B (pt)
WO (1) WO2020258224A1 (pt)

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Also Published As

Publication number Publication date
TWI700835B (zh) 2020-08-01
US11183508B2 (en) 2021-11-23
CN111557047A (zh) 2020-08-18
US20220020760A1 (en) 2022-01-20
WO2020258224A1 (en) 2020-12-30
TW202101770A (zh) 2021-01-01
AU2019455154B2 (en) 2022-11-17
AU2019455154A1 (en) 2021-11-18
JP2022534200A (ja) 2022-07-28
US20200411535A1 (en) 2020-12-31
EP3909069A4 (en) 2022-06-01
US11672115B2 (en) 2023-06-06
KR102611810B1 (ko) 2023-12-07
EP3909069A1 (en) 2021-11-17
US11871565B2 (en) 2024-01-09
SG11202111703YA (en) 2021-11-29
US20210399000A1 (en) 2021-12-23
KR20210121142A (ko) 2021-10-07
JP7422168B2 (ja) 2024-01-25
CN111557047B (zh) 2021-07-09

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