WO2021088670A1 - 一种刻蚀方法、空气隙型介电层及动态随机存取存储器 - Google Patents

一种刻蚀方法、空气隙型介电层及动态随机存取存储器 Download PDF

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WO2021088670A1
WO2021088670A1 PCT/CN2020/123648 CN2020123648W WO2021088670A1 WO 2021088670 A1 WO2021088670 A1 WO 2021088670A1 CN 2020123648 W CN2020123648 W CN 2020123648W WO 2021088670 A1 WO2021088670 A1 WO 2021088670A1
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etching
gas
wafer
purge
etching method
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PCT/CN2020/123648
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English (en)
French (fr)
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吴鑫
王春
郑波
马振国
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北京北方华创微电子装备有限公司
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Priority to KR1020227012177A priority Critical patent/KR102532136B1/ko
Priority to US17/769,841 priority patent/US11948805B2/en
Priority to JP2022523221A priority patent/JP7352732B2/ja
Publication of WO2021088670A1 publication Critical patent/WO2021088670A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment

Definitions

  • the present invention relates to the technical field of semiconductor manufacturing, in particular to an etching method for selectively etching a silicon oxide film, an air gap type dielectric layer and a dynamic random access memory.
  • the silicon oxide layer (SiO 2 ) in the deep trench structure with an aspect ratio of 20:1 needs to be completely removed , And can not etch the silicon nitride (SiN) on the sidewall of the trench. It is required that the etching selection ratio of (SiO 2 /SiN) should be above 100:1, preferably 500:1, or even 1000:1.
  • etching of silicon nitride For the etching of silicon nitride, one method is to use dry etching (Dry clean), which is separated from the traditional wet cleaning (Wet clean), which uses chemical reaction gases and catalysts to directly chemically react with the film The reaction, through process integration control, achieves precise and high-efficiency hole bottom removal without substrate damage (no plasma) and no re-oxidation.
  • Another method is to use hydrogen fluoride (HF) gas supplemented with alcohols (such as methanol) or alkaline gases (such as NH 3 ) for catalytic etching, commonly known as methanol catalytic process or ammonia catalytic process.
  • HF hydrogen fluoride
  • the etching selection ratio of SiO 2 /SiN is basically at the level of 30:1; when the existing ammonia catalytic process is used, the SiO 2 /SiN etching process The etching selection ratio will not be higher than 20:1. Neither of the existing two processes can meet the requirement of the etching selection ratio of SiO 2 /SiN.
  • embodiments of the present invention provide an etching method, an air gap type dielectric layer, and a dynamic random access memory, aiming to improve the etching selection of SiO 2 /SiN when the existing ammonia gas catalysis process is adopted. Than the problem of insufficient.
  • an etching method for selectively etching the silicon oxide film between the silicon nitride film and the silicon oxide film formed on the surface of the wafer includes:
  • Surface removal step etching the silicon oxide film at a first etching rate, and removing the surface degeneration layer covering the surface of the silicon nitride film;
  • Etching step etching the silicon oxide film at a second etching rate
  • the first etching rate is less than the second etching rate.
  • the surface removal step includes:
  • the first etching step etching the surface of the wafer with an etching gas under a first predetermined pressure and within the first etching time period, and
  • the first purge step purge the wafer with purge gas under the first purge pressure and within the first purge time, and
  • the first etching step and the first purging step are cyclically performed until the surface degeneration layer is removed.
  • the etching step includes:
  • the second etching step selectively etching the silicon oxide film with an etching gas under a second predetermined pressure and within a second etching time period, and
  • the second purge step Purging the wafer with the purge gas under the second purge pressure and within the second purge time, and
  • the second etching step and the second purging step are repeatedly cycled until the target etching amount of the silicon oxide film is reached.
  • the first predetermined pressure is less than the second predetermined pressure.
  • the range of the first predetermined pressure is 1 Torr-3 Torr; the range of the second predetermined pressure is 5 Torr-10 Torr.
  • the first etching duration is less than the second etching duration.
  • the range of the first etching duration is 1s-3s; the range of the second etching duration is 1s-5s.
  • the etching gas includes a first component gas and a second component gas, wherein the first component gas is hydrogen fluoride gas, and the second component gas is ammonia gas.
  • the second purging step further includes purging the wafer with the second component gas under the second purging pressure and within the second purging time period.
  • the purge gas includes at least one of nitrogen and inert gas.
  • the first component gas is supplied at a first flow rate; in the etching step, the first component gas is supplied at a second flow rate; wherein, the The first flow rate is greater than the second flow rate.
  • the process temperature of the surface removal step and the etching step are not less than 120°C.
  • the method further includes performing a heating sublimation treatment on the wafer, and cooling the wafer to room temperature after the sublimation treatment.
  • the temperature of the sublimation treatment is greater than or equal to 180°C.
  • the method further includes taking out the sublimated and cooled wafer and leaving it to stand for a preset time.
  • the method further includes detecting the thickness of the surface degeneration layer on the surface of the wafer to determine the first etching step and the first blowing step based on the thickness of the surface degeneration layer. The number of sweep cycles.
  • the total gas flow rate in the second etching step is the same as the total gas flow rate in the second purge step.
  • the surface modification layer is composed of at least three elements of silicon, nitrogen and oxygen.
  • an air gap type dielectric layer is provided, which is prepared by the above-mentioned etching method.
  • a dynamic random access memory including the above-mentioned air gap type dielectric layer.
  • the etching method provided by the embodiment of the present invention adopts a two-step etching method.
  • the etching selection ratio is greatly reduced.
  • by making the first etching rate smaller than the second etching rate excessive etching can be avoided during the surface removal step, which further guarantees a high selectivity ratio; afterwards, during the etching step, a higher etching rate The etching efficiency can be guaranteed.
  • the etching method provided by the embodiment of the present invention can also obtain an air gap type dielectric layer with a high SiO 2 /SiN etching selection ratio and a high-performance dynamic random access memory thereof.
  • Figure 1 is a schematic diagram of a deep trench etching structure
  • FIG. 2 is a comparison diagram of the etching effect of a wafer with a surface oxidation degeneration layer and a wafer without a surface oxidation degeneration layer under a certain etching process;
  • Figure 3 is a schematic diagram of the comparison of SiO 2 and SiN etching incubation time
  • FIG. 4 is a schematic diagram of the time sequence of the etching gas passage in an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of an etching process flow in an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of an etching process flow in another embodiment of the present invention.
  • FIG. 7 is a schematic diagram of the structure of an etching device used in the etching process of the present invention.
  • FIG. 8 is a comparison diagram of the measured etch incubation time of SiO 2 and SiN under the etching process conditions in an embodiment of the present invention.
  • W-wafer 11-silicon oxide film, 12-silicon nitride film, 13-oxidation denaturation layer, 210-etching process chamber, 220-uniform flow chamber, 230-gas distribution plate, 240-base, 311 -HF gas source, 312-N 2 gas source, 313-NH 3 gas source, 321-first mass flow controller, 322-second mass flow controller, 323-third mass flow controller, 324-fourth Mass flow controller, 331-first confluence point, 332-second confluence point, 333-third confluence point.
  • Etch the silicon oxide film For example, as shown in Figure 1, in the AirGap (Dynamic Random Access Memory, DRAM) chip manufacturing process, silicon oxide in a deep trench structure with an aspect ratio of 20:1 is required. The (SiO 2 ) film 11 is completely removed, and the silicon nitride (SiN) film 12 on the sidewall of the trench cannot be etched.
  • the surface layer of the silicon nitride film 12 exposed to the atmosphere has been oxidized and modified to form a surface denaturation layer 13 composed of at least three elements of silicon, nitrogen and oxygen.
  • the presence of the surface denaturation layer 13 will This has a negative impact on the etching process.
  • two wafer samples a and b are selected for comparison experiments. Among them, the silicon nitride film 12 of the wafer sample a has an oxidation denaturation layer 13 on the surface, and the wafer The surface of the silicon nitride film 12 of the sample b does not have the oxidation-denatured layer 13.
  • Table 1 is a comparison table of the etching parameters of the two wafer samples a and b
  • the etching method provided in the embodiment of the present invention divides the entire etching process into two steps, including:
  • Surface removal step etching the silicon oxide film at a first etching rate, and removing the surface degeneration layer covering the surface of the silicon nitride film;
  • Etching step etching the silicon oxide film at a second etching rate
  • the first etching rate is less than the second etching rate.
  • the SiO 2 /SiN etching selection ratio is greatly reduced due to the existence of the surface denaturation layer is avoided.
  • the first etching rate smaller than the second etching rate, excessive etching can be avoided during the surface removal step, which further guarantees a high selectivity ratio; at the same time, during the etching step, a higher etching rate The etching efficiency can be guaranteed.
  • the gas used for etching mainly includes a first component gas and a second component gas.
  • the first component gas includes hydrogen fluoride gas (HF)
  • the second component gas includes ammonia (NH 3 )
  • the etching gas combination has a higher etching efficiency.
  • the above-mentioned surface removal step specifically includes:
  • the first etching step etching the surface of the wafer with an etching gas under a first predetermined pressure and within the first etching time;
  • the first purge step under the first purge pressure and within the first purge time, purge the wafer with purge gas;
  • the first etching step and the first purging step are repeated until the surface degeneration layer is removed.
  • the etching gas mainly includes a first component gas and a second component gas.
  • the first component gas includes hydrogen fluoride gas (HF)
  • the second component gas includes ammonia gas (NH 3 )
  • the etching gas combination has higher etching efficiency.
  • the purge gas mainly includes at least one of N2 and an inert gas, where the inert gas includes but is not limited to helium, neon, argon, and the like.
  • the first etching step the first predetermined pressure is 2.2 Torr; the etching gas includes N 2 , HF and NH 3 , wherein the gas flow rate of N 2 is 450 sccm; the gas flow rate of HF is 300 sccm; the gas flow rate of NH 3 100sccm; the first etching time is 2s; the process temperature is 120°C;
  • the first purge step the first purge pressure is 6 Torr; the purge gas includes N 2 , and the gas flow rate of N 2 is 2700 sccm; the first purge time is 2 s; the process temperature is 120 °C;
  • the number of cycles is determined by the target etching amount of the SiN surface degeneration layer, for example, if the target etching amount is When, the number of cycles is about 30 times.
  • the setting of the above-mentioned target etching amount is related to the thickness of the surface degeneration layer of SiN, which is usually The thickness of the surface modified layer of SiN grown in different ways will vary.
  • the flow rate of HF is higher, and the gas flow rate of NH 3 is lower, so that the volume ratio of HF in the chamber is higher than that of NH 3 , which can be to a certain extent Suppress the etch rate of the combination of HF and NH 3 to avoid over-etching.
  • the first predetermined pressure range in the surface removal step is 1-3 Torr, and preferably 2 Torr. By setting the first predetermined pressure in a lower value range, it is beneficial to further suppress the etching rate.
  • the range of the first etching time in the surface removal step is 1-3s, and 2s is preferred. By setting the first etching time in a shorter numerical range, it is beneficial to accurately control the etching amount and slow down Etching rate,
  • the first purging time period is not less than the first etching time period to fully purify the etching reactants and products.
  • NH 3 gas was not passed in the first purge step to avoid the generation of presoak, thereby prolonging the time required for the etching gas to be chemically adsorbed on the wafer surface, thereby reducing
  • the purpose of the etching rate is to remove the surface degeneration layer on the silicon nitride film without over-etching the SiN.
  • the following ventilation methods can be used during the above surface removal step:
  • the first etching time of the first etching step is lower than the SiN etching incubation time under the process conditions.
  • the abscissa is the etching time (Etch Time); the ordinate is the etching amount (Etch Amount).
  • the etching reaction does not occur immediately when the etching gas reaches the wafer surface, but requires a period of incubation, that is, the incubation time. Exceeding the SiN's etching incubation time (incubation time) will cause the SiN to be etched and affect the improvement of the selection ratio.
  • the first purge duration of the first purge step is not less than the first etching duration, which can avoid over-etching and provide sufficient purge duration to quickly remove the etching gas and avoid the retention time of residual gas Too long.
  • the above etching step specifically includes:
  • the second etching step selectively etching the silicon oxide film with an etching gas under a second predetermined pressure and within the second etching time period;
  • the second purge step purging the wafer surface with purge gas under the second purge pressure and within the second purge time;
  • the second etching step and the second purging step are repeated until the target etching amount of the silicon oxide film is reached.
  • the etching gas mainly includes a first component gas and a second component gas.
  • the first component gas includes hydrogen fluoride gas (HF)
  • the second component gas includes ammonia gas (NH 3 )
  • the etching gas combination has higher etching efficiency.
  • the purge gas mainly includes at least one of N 2 and an inert gas, where the inert gas includes but is not limited to helium, neon, argon, and the like.
  • the second etching step the second predetermined pressure is 8 Torr; the etching gas includes N 2 , HF and NH 3 , wherein the gas flow rate of N 2 is 450 sccm; the gas flow rate of HF is 20 sccm; the gas flow rate of NH 3 is 100sccm; the second etching time is 3s; the process temperature is 120°C
  • the second purge step the second purge pressure is 8 Torr; the purge gas includes N 2 , the gas flow of N 2 is 470 sccm; the gas flow of NH 3 is 100 sccm; the second purge duration is 6 s; the process temperature is 120°C.
  • the flow rate of HF is lower, and the gas flow rate of NH 3 is higher, so that the volume ratio of HF in the chamber is lower than that of NH 3 , so as to improve the etching rate.
  • the flow rate of HF used in the second etching step is smaller than the first flow rate of HF used in the first etching step, so that the second etching rate is greater than the first etching rate.
  • the second predetermined pressure range is 5 Torr-10 Torr, and 8 Torr is preferred.
  • the second predetermined pressure is 5 Torr-10 Torr, and 8 Torr is preferred.
  • the second etching duration is in the range of 1s-5s.
  • the second etching duration is preferably 3s.
  • the second etching step basically does not etch SiN.
  • the second purge duration is not less than the second etching duration, so as to fully purge and remove the etching reactants and products.
  • NH 3 is still continuously supplied in the second purge step, that is, the purge gas in the second purge step also includes the same flow rate of NH 3 as in the second etching step, and the continuously supplied NH 3 gas can be Fully immerse the wafer surface to make the wafer surface adsorb a sufficient amount of NH 3 gas before the next etching step, so that when HF is introduced, the time for the gas to mix and adhere to the wafer surface to undergo an etching reaction is shortened. Furthermore, the reaction rate of the etching gas in the next etching step is accelerated, and the etching efficiency is improved.
  • the total air flow in the second etching step is the same as the total air flow in the second purge step, so that the flow does not change.
  • the butterfly valve used to control the flow of the chamber does not need to be opened and closed frequently, which simplifies the operation and improves The stability and accuracy of the system.
  • Example 1 provides an experimental comparison of the SiO 2 /SiN selection ratio for different etching process steps. It can be seen from the comparison table that the etching selection ratio is greatly improved after the surface removal step is added.
  • the single etching time cannot be too long, otherwise, once the etching amount of SiN rises, the selection ratio will be difficult to increase. For this reason, the entire etching step needs to be etched.
  • the time is split to form multiple cyclic etching steps.
  • the end point of each etching is the starting point of SiN just beginning to be etched, that is, the etching time of each etching step is the etching incubation time of SiN. time).
  • the etching reaction does not occur immediately when the etching gas reaches the surface of the wafer, but requires a period of incubation, that is, the incubation time. Generally speaking, the faster the etching rate, the shorter the incubation time required.
  • the above-mentioned etching step may adopt the following ventilation methods as shown in FIG. 4:
  • the second etching time Ta of the second etching step is less than the incubation time of SiN under the process conditions, and the second purge time Tb of the second purge step is not less than the second etching time.
  • the second etching time Ta of the etching step is to avoid over-etching and provide sufficient purge time to quickly remove the etching gas, and avoid the residual gas retention time being too long, exceeding the etching incubation time of SiN (incubation time ), resulting in the etching of SiN, affecting the improvement of the selection ratio.
  • NH 3 is still continuously supplied, so that the continuously supplied NH 3 gas can fully impregnate the surface of the wafer, so that the wafer surface can pre-adsorb sufficient NH 3 before the next etching step.
  • NH 3 When entering HF, it shortens the time for the gas to mix and adhere to the surface of the wafer for etching reaction, which can speed up the etching gas reaction rate of the next etching step and improve the etching efficiency.
  • the process window is maximized to maximize the etching of SiO 2. Then, through multiple cycles of etching, a higher SiO 2 /SiN etching selection ratio is finally achieved.
  • NH 3 is always in a vented state, and HF is pulsed air supply.
  • the two gases can also be exchanged, that is, HF is always in a ventilated state, and NH 3 is pulsed gas supply.
  • the adsorbed etching gas is difficult to purge off, which causes accelerated etching of the silicon nitride film, and reaction by-products deposited on the silicon oxide film Partially hinders the direct contact reaction of the etching gas with SiO 2 and reduces the etching rate of SiO 2 , thereby causing over-etching of SiN on the one hand, hindering the etching of SiO 2 on the other hand, and reducing the selectivity ratio.
  • the surface removal step and the etching step are completely separated, as shown in Figure 5, that is, after the surface removal step is completed, the wafer W is removed from the entire etching system and enters the front opening wafer transfer In the Front Opening Unified Pod (FOUP), and then restart, perform the etching process.
  • the etching process decides whether to perform multiple large-cycle etchings according to needs.
  • the main purpose of the large cycle is to fully sublime and discharge the reaction by-products. Since the inhibitory effect of the reaction by-products on the SiO 2 etching rate is eliminated, increasing the number of large cycles can increase the etching amount of SiO 2.
  • the temperature of the sublimation treatment is greater than or equal to 180° C. to ensure that the etching reactants and by-products remaining on the surface of the wafer W are fully discharged by sublimation.
  • the entire etching process includes:
  • the wafer W is placed in the wafer transfer box and left for a few minutes, and then the etching process S200 is performed, or it is left for a few minutes in a vacuum chamber.
  • the standing time does not exceed 5 minutes. Therefore, after leaving the cooling chamber and standing still, some reactants or etching gases that are free on the surface of the wafer W are further volatilized and separated from the surface of the wafer W, and free from the free component environment remaining in the cooling chamber, which is beneficial to the wafer W. Surface etching gas and residues are completely separated out and volatilized for purification.
  • Standing for a certain period of time can offset the stress of the chemical reaction between atoms on the SiN surface, make the atomic structure arrangement regular, improve the surface flatness, and reduce the adsorption and contact area of the SiN surface to the etching gas.
  • the standing environment can be in the FOUP or in a vacuum chamber. Since SiN is not easy to oxidize in a short time at room temperature, the cooled wafer W can be placed in the FOUP for a few minutes without re-oxidation. Degeneration layer.
  • S250 Repeat steps S220 to S240 until the silicon oxide film etched amount meets the target etched amount, and then put it into the wafer transfer box to finish.
  • repeating step S220 to step S240 can further fully sublimate and discharge the reaction by-products compared to directly sublimating and purging in the process chamber, so that the reaction by-products on the surface of the wafer W can be removed, and the deposition of reaction by-products can be avoided.
  • the above steps can be simplified.
  • the surface removal step S100' is performed in conjunction with the etching step S200': after step S120 is completed, after the sublimation and cooling processes of step S130 and step S140, directly
  • the etching step S200' is performed, the overall etching system is no longer exited, and the wafer transfer box is not entered.
  • Example 2 gives an experimental comparison of the SiO 2 /SiN selection ratio for different etching connection steps. It can be seen that the surface removal step and the etching step are carried out separately, that is, the wafer W after cooling in step S140 is taken out of the entire system and then Putting it into the wafer transfer box or leaving it in a vacuum chamber for several minutes, compared with directly putting the wafer W cooled in the cooling chamber in step S140 into the etching step S200 for etching, the selection ratio is significantly improved.
  • the wafer in order to accurately grasp the thickness of the surface denaturation layer on the surface of the wafer W, so as to precisely control the number of cycles and the single-step time step, in the preparation start stage of the surface removal step of step S110, the wafer is first inspected The thickness of the surface modification layer on the surface to determine the number of cycles of the surface removal step based on the thickness of the surface modification layer. Therefore, the surface removal step is implemented in a targeted manner to ensure that the surface denaturation layer is completely removed while avoiding excessive etching.
  • the number of cycles of the surface removal step is zero, that is, steps S120 to S150 in the surface removal step process are skipped, and step S200 is directly entered.
  • step S210 includes rechecking the thickness of the surface degeneration layer on the surface of the wafer W to ensure that there is no oxidative degeneration layer on the surface of the wafer W before entering step S220 to ensure the realization of a high selection ratio.
  • the etching reaction and the sublimation of the solid product are realized in the same chamber, that is, the increase in the etching amount is realized by increasing the number of cycles of etching and purging.
  • the increase in the etching amount is realized by increasing the number of cycles of etching and purging.
  • only the automatic process recipe is added.
  • the number of cycles in (recipe) is sufficient, and the wafer does not need to enter and exit the process chamber frequently.
  • the above two methods can also be combined.
  • the sub-chamber processing is beneficial for separating the wafer from the original reaction environment, avoiding the secondary sedimentation of the etching gas and reaction by-products in the original chamber on the wafer surface, and inhibiting the sublimation of the above-mentioned components on the wafer surface.
  • the etching gas supply pressure is reduced, the NH3 gas ratio is reduced, etc., after the initial etching rate of the etching step is reduced, it can also be used in the surface removal step process.
  • the single-step etching time of the etching step satisfies that the single-step etching time is not less than the SiO 2 film etching incubation time, and the single-step etching time is relative to the etching incubation time of the SiN film. It is closer to the etching incubation time of the SiO 2 film, thereby ensuring the realization of a high SiO 2 /SiN selection ratio. That is , the etching incubation time of the SiO 2 film ⁇ the first etching duration ⁇ the second etching duration ⁇ the etching incubation time of the SiN film.
  • the single-step etching time is much shorter than the etching incubation time of the SiN film, which can further avoid the delay of the purge.
  • the time for the etching gas and etching reaction product to adhere to the surface of the wafer W sufficiently caused to be prolonged to approach or even exceed the etching incubation time of the SiN film, so that the shorter the single-step etching time, the more response time can be provided for purge Therefore, before the SiN film etching incubation time is approached or even exceeded, the etching gas and the etching reaction products are removed to avoid the etching of the SiN film.
  • the single-step etching time is closer to the etching incubation time of the SiO 2 film than the etching incubation time of the SiN film, which can ensure the realization of a high SiO 2 /SiN etching selection ratio.
  • the embodiment of the present invention proposes an etching device for selectively etching between the silicon nitride film and the silicon oxide film formed on the surface of the wafer W.
  • the etching device includes a process chamber 210 including a gas supply unit and a base 240.
  • the gas supply unit sequentially includes a gas supply path, a uniform flow chamber 220, and a susceptor 240.
  • the gas supply path includes a gas source section and a premixing section in sequence.
  • the gas source sections respectively output and supply a single gas source and are premixed in the premixing section when they meet.
  • the gas source section includes an HF gas source 311, a N 2 gas source 312, and an NH 3 gas source 313, and a first mass flow controller 321, a second mass flow controller 322, and a third mass flow controller that control the above gas sources respectively.
  • the first mass flow controller 321 controls the gas supply volume of the HF gas source 311, and the fourth mass flow controller 324 controls the gas supply volume of the NH 3 gas source 313.
  • the N 2 gas source 312 has two gas outlets, respectively The second mass flow controller 322 and the third mass flow controller 323 control.
  • the gas controlled by the first mass flow controller 321 and the second mass flow controller 322 converge at the first confluence point 331, and the gas controlled by the third mass flow controller 323 and the fourth mass flow controller 324 converge at the second confluence point 332 Confluence, the gas path where the first confluence point 331 is located and the gas path where the second confluence point 332 is located pass into the uniform flow cavity 220 through the third confluence point 333, and then are fully mixed in the uniform flow cavity 220. After that, the mixed gas is sprayed from a single gas distribution plate 230 onto the surface of the wafer W to be processed.
  • the uniform flow chamber 220 can make the incoming gas fully mixed in the uniform flow chamber 220 before being sprayed out through the gas distribution plate 230.
  • the etching efficiency can be effectively improved. After the confluence point is advanced, it can be ensured that the gas flowing out of the surface of the gas distribution plate 230 has a higher concentration of NH 4 F. Since HN 4 F is solid at low temperatures, it is necessary to heat the gas distribution plate 230 to above 120 degrees.
  • the susceptor 240 is equipped with a high-temperature heating device, and the temperature of the susceptor 240 is increased to 120 degrees or even higher, to ensure that the solid products generated by the reaction can be quickly sublimated and separated from the surface of the wafer W, preventing them The adsorption of the etchant on the surface of the wafer W is hindered.
  • the susceptor 240 is set as a liftable susceptor, and the process chamber 210 is reduced to remove the adapter in the chamber. Through the lifting cooperation of the chamber 210 and the susceptor 240, the surface of the wafer W and the gas are minimized as much as possible. Distribute the volume of space between the trays 230. This helps to quickly remove the etching gas, and avoid the excessive retention time of the residual gas, which exceeds the etching incubation time of SiN, which causes the etching of SiN and affects the improvement of the selection ratio.
  • the gas supply path includes a gas source section and a pre-mixing section in sequence, and the gas source sections respectively output and supply a single gas source and are premixed in the pre-mixing section at the intersection. Pre-mixing in the pre-mixing section further improves the pre-mixing effect of the etching reaction gas and improves the etching efficiency.
  • the gas supply unit and the susceptor are provided with heating devices, so that the etching process temperature is not less than 120°C.
  • the etching process temperature is not less than 120°C.
  • it prevents the premixed NH 4 F from condensing and blocking the air supply channel due to low temperature.
  • it can accelerate the sublimation rate of reaction products on the wafer surface, increase the etching rate, and avoid the deposition of reaction products. The choice is down.
  • an air gap type dielectric layer which is prepared by the above etching method, so that the obtained air gap type dielectric layer has a high selectivity ratio.
  • a dynamic random access memory including the above-mentioned air gap type dielectric layer, so as to improve the performance of the dynamic random access memory.
  • the disclosed device and method may also be implemented in other ways.
  • the device embodiments described above are only illustrative. If the above etching method is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer readable storage medium.
  • the technical solution of the present invention essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present invention.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disks or optical disks and other media that can store program codes. .
  • the present invention compares the two etching methods for samples c and d respectively, where c is the surface removal step + the etching step, and d is only the etching step. .
  • the etching amount of SiO 2 of the two samples is basically the same, and the etching amount of SiN is obviously different. This shows that the surface removal step process can significantly improve the overall etching selection ratio.
  • Table 3 shows the comparison of the connection steps between the surface removal step and the etching step.
  • the surface removal step is performed separately from the etching step. That is, after the surface removal step process is completed, the wafer needs to be fully heated to remove the reaction byproducts generated on the surface before the subsequent etching process can be performed.
  • the usual method is that after the surface removal step process is completed, the wafer is transferred to the sublimation chamber for sufficient sublimation, and then transferred to the process chamber for the etching process. Instead of completing the surface removal step and the etching process at one time in the process chamber.
  • the comparative test in Table 3 shows that the surface removal step and the etching step are performed separately, which can avoid a substantial increase in the amount of SiN etching, thereby increasing the selection ratio.
  • the present invention draws a curve of the etching amount of SiO 2 and SiN with the etching time at a process temperature of 120 °C under certain process conditions, as shown in Figure 8 Shown.
  • SiO 2 and SiN etch significantly increased the amount of etching start time point were 1-> 2s and 5-> 6s, infer this condition, SiN incubation time of about 5s-6s, SiO 2 The incubation time is about 1s-2s.
  • Fig. 8 is experimental data obtained under the conditions of 120°C, 8 torr, HF with a flow rate of 20 sccm, NH 3 with a flow rate of 100 sccm, and N 2 with a flow rate of 450 sccm.
  • the etching amount of SiO 2 is higher than Under the circumstance, a selection ratio of not less than 500:1 was obtained, and the selection ratio data of some processes even reached 1000:1, which was significantly higher than that of the conventional ammonia catalytic process.
  • the shorter the single-step etching time the more response time can be provided for the purge, so that when it is close to or even longer than the SiN film Before the etching incubation time, the etching gas and the etching reaction products are removed to avoid the etching of the SiN film.
  • a long single-step etching time will cause excessive deposition of the etching reaction products on the surface of the wafer W, which will cause difficulty in sublimation purging, which will result in further adsorption of etching gas and etching of the SiN film.
  • the single-step etching time is closer to the SiO 2 film etching incubation time than the SiN film etching incubation time, thereby ensuring the realization of a high SiO 2 /SiN selection ratio.

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Abstract

一种刻蚀方法、空气隙型介电层及动态随机存取存储器，该刻蚀方法用于在晶圆表面上分布的氮化硅膜和氧化硅膜之间选择性地刻蚀氧化硅膜，包括，表面去除步骤：以第一刻蚀速率刻蚀氧化硅膜，并清除覆于氮化硅膜表面上的表面变性层；以及刻蚀步骤：以第二刻蚀速率刻蚀氧化硅膜，其中，第一刻蚀速率小于第二刻蚀速率。该方法避免了由于晶圆表面上氮化硅表面的氧化变性层的存在导致的刻蚀选择比大大降低的问题。特别的，第一刻蚀速率小于第二刻蚀速率可以在保证刻蚀步骤高效刻蚀的同时，避免在表面去除步骤中的过度刻蚀，进一步保障了高刻蚀选择比。

Description

一种刻蚀方法、空气隙型介电层及动态随机存取存储器 技术领域
本发明涉及半导体制造技术领域，尤其涉及一种用于选择性地刻蚀氧化硅膜的刻蚀方法、空气隙型介电层及动态随机存取存储器。
背景技术
随着集成电路的特征尺寸的不断缩小，工艺复杂程度急剧增加。另外，由于线宽尺寸的微缩，需要开发更精准、更高选择比的薄膜去除工艺。如在动态随机存取存储器(Dynamic Random Access Memory，DRAM)芯片制程的空气隙(AirGap)工艺中，需要将深宽比为20：1的深槽结构内的氧化硅层(SiO 2)完全去除，且不能对槽侧壁的氮化硅(SiN)造成刻蚀，要求(SiO 2/SiN的刻蚀选择比在100：1以上，最好能达到500：1，甚至1000：1的水平。
对于氮化硅的刻蚀，一种方法是采用干法刻蚀(Dry clean)，其是从传统的湿法清洗(Wet clean)分离出来的，其使用化学反应气体和催化剂直接与薄膜发生化学反应，通过工艺集成控制达到精确、高效率的孔洞底部去除，且无衬底损伤(无等离子体)、无再氧化。还有一种方法是采用氟化氢(HF)气体辅以醇类(如甲醇)或碱性气体(如NH 3)进行催化刻蚀，俗称甲醇催化工艺或氨气催化工艺。上述两种工艺通常也用来刻蚀氮化硅。
但是，经过大量的工艺实验发现：在采用现有的甲醇催化工艺时，SiO 2/SiN的刻蚀选择比基本处于30：1的水平；采用现有的氨气催化工艺时，SiO 2/SiN的刻蚀选择比也不会高于20：1。现有两种工艺均无法满足SiO 2/SiN的刻蚀选择比的需求。
发明内容
为解决上述问题，本发明实施例提供一种刻蚀方法、空气隙型介电层及动态随机存取存储器，旨在改善采用现有的氨气催化工艺时，SiO 2/SiN的刻蚀选择比不足的问题。
根据本发明实施例的一个方面，提供一种刻蚀方法，用于在形成于晶圆表面上分布的氮化硅膜和氧化硅膜之间选择性地刻蚀所述氧化硅膜，其特征在于，包括：
表面去除步骤：以第一刻蚀速率刻蚀所述氧化硅膜，并清除覆于所述氮化硅膜的表面上的表面变性层；以及
刻蚀步骤：以第二刻蚀速率刻蚀所述氧化硅膜，
其中，所述第一刻蚀速率小于所述第二刻蚀速率。
可选的，所述表面去除步骤包括：
第一刻蚀步：在第一预定压力下以及第一刻蚀时长内，以刻蚀气体刻蚀所述晶圆表面，以及
第一吹扫步：在第一吹扫压力下以及第一吹扫时长内，以吹扫气体吹扫所述晶圆，并且
循环进行所述第一刻蚀步和所述第一吹扫步，直至清除所述表面变性层为止。
可选的，所述刻蚀步骤包括：
第二刻蚀步：在第二预定压力下以及第二刻蚀时长内，以刻蚀气体选择性地刻蚀所述氧化硅膜，以及
第二吹扫步：在第二吹扫压力下以及第二吹扫时长内，以所述吹扫气体吹扫所述晶圆，并且
重复循环所述第二刻蚀步和第二吹扫步，直至达到所述氧化硅膜的目标刻蚀量。
可选的，所述第一预定压力小于所述第二预定压力。
可选的，所述第一预定压力的范围为1Torr-3Torr；所述第二预定压力的范围为5Torr-10Torr。
可选的，所述第一刻蚀时长小于所述第二刻蚀时长。
可选的，所述第一刻蚀时长的范围为1s-3s；所述第二刻蚀时长的范围为1s-5s。
可选的，所述刻蚀气体包括第一组分气体和第二组分气体，其中，所述第一组分气体为氟化氢气体，所述第二组分气体为氨气。
可选的，所述第二吹扫步，还包括，在所述第二吹扫压力下以及所述第二吹扫时长内，以所述第二组分气体吹扫所述晶圆。
可选的，所述吹扫气体包括氮气和惰性气体中的至少一种。
可选的，在所述表面去除步骤中，所述第一组分气体以第一流量供应；在所述刻蚀步骤中，所述第一组分气体以第二流量供应；其中，所述第一流量大于所述第二流量。
可选的，所述表面去除步骤和所述刻蚀步骤的工艺温度均不小于120℃。
可选的，在所述表面去除步骤和所述刻蚀步骤之间还包括，对所述晶圆进行加热升华处理，并在所述升华处理之后，对所述晶圆冷却至室温。
可选的，所述升华处理的温度大于等于180℃。
可选的，在所述刻蚀步骤之前还包括，将升华冷却后的所述晶圆取出并静置预设时间。
可选的，在所述表面去除步骤之前，还包括，检测所述晶圆表面上的表面变性层厚度，以基于所述表面变性层厚度确定所述第一刻蚀步和所述第一吹扫步的循环次数。
可选的，所述第二刻蚀步中的总气流量与所述第二吹扫步中的总气流量相同。
可选的，所述表面变性层至少由硅、氮和氧三种元素组成。
根据本发明实施例的另一个方面，提供一种空气隙型介电层，采用上述刻蚀方法制备。
根据本发明实施例的另一个方面，提供一种动态随机存取存储器，包括上述空气隙型介电层。
本发明实施例的技术效果：
本发明实施例提供的刻蚀方法，其采用两步法刻蚀，首先通过清除覆于氮化硅膜的表面上的表面变性层，避免了由于该表面变性层的存在导致的SiO 2/SiN的刻蚀选择比大大降低的问题。并且，通过使第一刻蚀速率小于第二刻蚀速率，可以在进行表面去除步骤时避免过度刻蚀，进一步保障了高选择比；之后，在进行刻蚀步骤时，较高的刻蚀速率可以保证刻蚀效率。本发明实施例提供的刻蚀方法还可以获得高SiO 2/SiN刻蚀选择比的空气隙型介电层及其高性能动态随机存取存储器。
附图说明
为了更清楚地说明本发明的实施方式或现有技术中的技术方案，下面将对实施方式或现有技术描述中所需要使用的附图作简单地介绍。显而易见地，下面描述中的附图仅仅是示例性的，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图引伸获得其它的实施附图。
本说明书所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供熟悉此技术的人士了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。
图1为深槽刻蚀结构示意图；
图2为具有表面氧化变性层的晶圆和没有表面氧化变性层的晶圆在某相同刻蚀工艺下的刻蚀效果对比图；
图3为SiO 2与SiN刻蚀孕育时间比较示意图；
图4为本发明一种实施例中的刻蚀气体通入时序示意图；
图5为本发明一种实施例中的刻蚀工艺流程示意图；
图6为本发明另一种实施例中的刻蚀工艺流程示意图；
图7为本发明刻蚀工艺所用的一种刻蚀装置结构示意图；
图8为本发明一种实施例中的刻蚀工艺条件下的SiO 2与SiN刻蚀孕育时间实测比对图。
附图标记说明：
W-晶圆，11-氧化硅膜，12-氮化硅膜，13-氧化变性层，210-刻蚀工艺腔体，220-匀流腔，230-气体分配盘，240-基座，311-HF气源，312-N 2气源，313-NH 3气源，321-第一质量流量控制器，322-第二质量流量控制器，323-第三质量流量控制器，324-第四质量流量控制器，331-第一汇合点，332-第二汇合点，333-第三汇合点。
具体实施方式
以下由特定的具体实施例说明本发明的实施方式，熟悉此技术的人士可由本说明书所揭露的内容轻易地了解本发明的其他优点及功效，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本发明的描述中，术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性。在不冲突的情况下，本发明中的实施例及实施例中的特征可以相互组合。为使本发明的上述目的、特征和优点能够 更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
本发明实施例的一个方面，提供一种刻蚀方法，用于在形成于待处理晶圆的表面上分布的氮化硅膜(SiN)和氧化硅膜(SiO 2)之间选择性地刻蚀氧化硅膜。例如，如图1所示，在动态随机存取存储器(Dynamic Random Access Memory，DRAM)芯片制程的空气隙(AirGap)工艺中，需要将深宽比为20：1的深槽结构内的氧化硅(SiO 2)膜11完全去除，且不能对槽侧壁的氮化硅(SiN)膜12造成刻蚀。
在实际制程中，暴露在大气中的氮化硅膜12，其表层已被氧化改性，形成至少由硅、氮和氧三种元素组成的表面变性层13，该表面变性层13的存在会对刻蚀过程造成负面影响，如图2所示，选用两片晶圆样品a、b进行对比实验，其中，晶圆样品a的氮化硅膜12的表面存在氧化变性层13，而晶圆样品b的氮化硅膜12的表面不存在氧化变性层13。经过对两片晶圆样品a、b采用相同的刻蚀工艺进行刻蚀后，测量每片晶圆样品上SiO 2和SiN的刻蚀量，发现晶圆样品a的氮化硅膜12的刻蚀量明显高于晶圆样品b的氮化硅膜12的刻蚀量。具体对比数值如下述表1所示。
表1，为两片晶圆样品a、b的刻蚀参数的对比表
Figure PCTCN2020123648-appb-000001
由上述表1可以看出，表面变性层13的存在，会影响刻蚀气体的吸附，导致SiN刻蚀量骤增。此外，表面变性层13在被刻蚀时，产生的固态生成物对其下方的SiN造成了进一步的刻蚀。
基于上述发现，为了避免表面变性层13对SiO 2/SiN的刻蚀选择比的影响，本发明实施例提供的刻蚀方法，将整个刻蚀过程分成两步实现，包括：
表面去除步骤：以第一刻蚀速率刻蚀氧化硅膜，并清除覆于该氮化硅膜的表面上的表面变性层；以及，
刻蚀步骤：以第二刻蚀速率刻蚀氧化硅膜；
其中，第一刻蚀速率小于第二刻蚀速率。
通过清除覆于氮化硅膜的表面上的表面变性层，避免了由于该表面变性层的存在导致的SiO 2/SiN的刻蚀选择比大大降低的问题。并且，通过使第一刻蚀速率小于第二刻蚀速率，可以在进行表面去除步骤时避免过度刻蚀，进一步保障了高选择比；同时，在进行刻蚀步骤时，较高的刻蚀速率可以保证刻蚀效率。
其中，刻蚀所用的气体主要包括第一组分气体和第二组分气体，在一些实施例中，第一组分气体包括氟化氢气体(HF)，第二组分气体包括氨气(NH 3)，该刻蚀气体组合具有更高的刻蚀效率。
具体的，在一个实施例中，上述表面去除步骤，具体包括：
第一刻蚀步：在第一预定压力下以及第一刻蚀时长内，以刻蚀气体刻蚀晶圆表面；以及
第一吹扫步：在第一吹扫压力下以及第一吹扫时长内，以吹扫气体吹扫晶圆；
循环进行上述第一刻蚀步和第一吹扫步，直至清除表面变性层为止。
其中，刻蚀气体主要包括第一组分气体和第二组分气体，在一些实施例中，第一组分气体包括氟化氢气体(HF)，第二组分气体包括氨气(NH 3)，该刻蚀气体组合具有更高的刻蚀效率。
吹扫气体主要包含N2和惰性气体中的至少一种，其中，惰性气体包括而不限于氦、氖、氩等。
上述表面去除步骤采用的典型的工艺参数如下：
a.第一刻蚀步：第一预定压力为2.2Torr；刻蚀气体包括N 2、HF和NH 3， 其中，N 2的气体流量为450sccm；HF的气体流量为300sccm；NH 3的气体流量为100sccm；第一刻蚀时长为2s；工艺温度为120℃；
b.第一吹扫步：第一吹扫压力为6Torr；吹扫气体包括N 2，N 2的气体流量为2700sccm；第一吹扫时长为2s；工艺温度为120℃；
c.小循环：循环进行第一刻蚀步与第一吹扫步，循环次数根据SiN的表面变性层的目标刻蚀量而定，例如，若该目标刻蚀量为
Figure PCTCN2020123648-appb-000002
时，循环次数约30次。上述目标刻蚀量的设定与SiN的表面变性层的厚度有关，通常为
Figure PCTCN2020123648-appb-000003
不同方式生长的SiN的表面变性层的厚度会存在差异。
可选的，在第一刻蚀步中，HF的流量较高，而NH 3的气体流量较低，从而使HF在腔室内的体积占比相对于NH 3较高，这可以在一定程度上抑制HF与NH 3结合的刻蚀速率，从而避免过度刻蚀。表面去除步骤中的第一预定压力范围为1-3Torr，且以2Torr为优，通过将该第一预定压力设定在较低的数值范围内，有利于进一步抑制刻蚀速率。表面去除步骤中的第一刻蚀时长范围为1-3s，且以2s为优，通过将该第一刻蚀时长设定在较短的数值范围内，有利于刻蚀量的精准控制并减缓刻蚀速率，
在第一吹扫步中，第一吹扫时长不小于第一刻蚀时长，以充分吹扫排净刻蚀反应物和生成物。并且，为了降低刻蚀速率，在第一吹扫步中没有通NH 3气体，避免预吸附(presoak)的产生，从而延长了刻蚀气体化合吸附于晶圆表面所需要的时间，从而达到降低刻蚀速率的目的，进而可以在避免对SiN的过度刻蚀的前提下清除氮化硅膜上的表面变性层。
在一些实施例中，上述表面去除步骤过程中可以采用如下通气方式：
1)在第一时刻，向腔室内通入一定量的N 2(如450sccm)，以使腔室内压力达到第一预定压力(如2.2Torr)；
2)在第二时刻，保持腔室压力不变，开始通入NH 3(如100sccm)，同时通入HF(如300sccm)，反应开始，即第一刻蚀步。
3)在第三时刻，停止通HF和NH 3，第一刻蚀步结束，进入第一吹扫步(purge)，此时N2仍持续供应，以利于反应生成物的及时排除。
4)以此类推，通过脉冲式通入HF和NH 3，让整个表面去除过程在刻蚀与吹扫步骤间多次循环进行，以清除表面变性层。
5)第一刻蚀步的第一刻蚀时长低于该工艺条件下的SiN的刻蚀孕育时间(incubation time)。
如图3所示，横坐标为刻蚀时长(Etch Time)；纵坐标为刻蚀量(Etch Amount)。刻蚀气体并不是一抵达至晶圆表面就会立刻发生刻蚀反应，而是需要孕育孵化一段时间，即孕育时间(incubation time)。超出SiN的刻蚀孕育时间(incubation time)，会造成对SiN的刻蚀，影响选择比的提升。同时，第一吹扫步的第一吹扫时长不低于第一刻蚀时长，这可以避免过度刻蚀并提供充分的吹扫时长以使刻蚀气体的快速排除，避免因残气滞留时间过长。
在一个实施例中，上述刻蚀步骤，具体包括：
第二刻蚀步：在第二预定压力下以及第二刻蚀时长内，以刻蚀气体选择性地刻蚀氧化硅膜；以及
第二吹扫步：在第二吹扫压力下以及第二吹扫时长内，以吹扫气体吹扫晶圆表面；
循环进行上述第二刻蚀步和第二吹扫步，直至达到氧化硅膜的目标刻蚀量。
其中，刻蚀气体主要包括第一组分气体和第二组分气体，在一些实施例中，第一组分气体包括氟化氢气体(HF)，第二组分气体包括氨气(NH 3)，该刻蚀气体组合具有更高的刻蚀效率。
吹扫气体主要包含N 2和惰性气体中的至少一种，其中，惰性气体包括而不限于氦、氖、氩等。
上述刻蚀步骤采用的典型的工艺参数如下：
a.第二刻蚀步：第二预定压力为8Torr；刻蚀气体包括N 2、HF和NH 3，其中，N 2的气体流量为450sccm；HF的气体流量为20sccm；NH 3的气体流量为100sccm；第二刻蚀时长为3s；工艺温度为120℃
b.第二吹扫步：第二吹扫压力为8Torr；吹扫气体包括N 2，N 2的气体流量为470sccm；NH 3的气体流量为100sccm；第二吹扫时长为6s；工艺温度为120℃。
c.小循环：循环进行第二刻蚀步与第二吹扫步，循环次数根据SiO 2的目标刻蚀量而定。
可选的，在第二刻蚀步中，HF的流量较低，而NH 3的气体流量较高，从而使HF在腔室内的体积占比相对于NH 3较低，以利于提高刻蚀速率。特别的，第二刻蚀步采用的HF的流量小于上述第一刻蚀步采用的HF的第一流量，以使第二刻蚀速率大于第一刻蚀速率。
在第二刻蚀步中，第二预定压力范围为5Torr-10Torr，且以8Torr为优，通过将该第二预定压力设定在较高的数值范围内，有利于加速刻蚀速率。
在第二刻蚀步中，第二刻蚀时长范围为1s-5s，通过将该第二刻蚀时长设定在较长的数值范围内，有利于刻蚀气体在晶圆表面的充分浸渍反应，而为了避免刻蚀单步时长接近SiN的刻蚀孕育时间造成对SiN的刻蚀，第二刻蚀时长以3s为优。在SiN刻蚀孕育时间内，第二刻蚀步对SiN基本无刻蚀。
在第二吹扫步中，第二吹扫时长不小于第二刻蚀时长，以充分吹扫排净刻蚀反应物和生成物。可选的，在第二吹扫步中NH 3仍持续供应，即第二吹扫步中的吹扫气体还包括与第二刻蚀步中相同流量的NH 3，连续供应的NH 3气体可以充分浸渍晶圆表面，以使晶圆表面在下一次刻蚀步之前预先吸附足量的NH 3气体，从而当通入HF时，缩短了气体混合和附着于晶圆表面发生刻蚀反应的时间，进而加快了下一次刻蚀步的刻蚀气体反应速率，提高刻蚀效率。
可选的，第二刻蚀步中的总气流量与第二吹扫步中的总气流量相同，从而流量不变，腔室的用于控制流量的蝶阀无需频繁开关，简化操作并提高了系统的稳定性和精确度。
示例1给出了不同刻蚀工艺步骤的SiO 2/SiN选择比实验对照，由对照表可看出，在增加表面去除步骤后，刻蚀选择比大幅度提升。
进一步的，在进行刻蚀步骤时，单次刻蚀时间不能过长，否则SiN的刻蚀量一旦上涨起来，选择比就很难提高，为此，就需要要把整个刻蚀步骤的刻蚀时长拆分，形成多次循环刻蚀步骤，每次刻蚀的结束点为SiN刚开始要被刻蚀的起始点，即每次刻蚀步骤的刻蚀时长为SiN的刻蚀孕育时间(incubation time)。刻蚀气体并不是一抵达至晶圆表面就会立刻发生刻蚀反应，而是需要孕育孵化一段时间，即孕育时间(incubation time)。通常讲，刻蚀速率越快，所需的孵化时间越短。如图3所示，由于SiO 2的刻蚀速率比SiN的刻蚀速率快，两者存在孕育时间(incubation time)的时间差，在该时间差内进行刻蚀，可以获得较高的刻蚀选择比。
由此，在一些实施例中，上述刻蚀步骤可以采用如图4所示的如下通气方式：
1)在t0时刻，向腔室内通入一定量的N 2(如450sccm)，使腔室内压力达到预定压力(如8Torr)；
2)在t1时刻，保持腔室压力不变，开始通入一定量的NH 3(如100sccm)，使晶圆表面预先吸附足量的NH 3，即NH 3预吸附(presoak)；
3)在t2时刻，保持腔室压力不变，开始通气HF，反应开始，即第二刻蚀步(Etch)。在t3时间，停止通HF，刻蚀步结束，进入第二吹扫步(purge)，此时NH 3和N 2仍持续供应，以利于反应生成物的及时排除，同时，NH 3持续供应利于晶圆表面的预吸附效应。
4)以此类推，通过脉冲式通入HF，让整个刻蚀过程在刻蚀与吹扫步骤 间多次循环进行，以实现SiO 2的持续性刻蚀。
5)第二刻蚀步的第二刻蚀时长Ta低于该工艺条件下的SiN的刻蚀孕育时间(incubation time)，第二吹扫步的第二吹扫时长Tb不低于第二刻蚀步的第二刻蚀时长Ta，从而避免过度刻蚀并提供充分的吹扫时间以使刻蚀气体的快速排除，避免因残气滞留时间过长，超出SiN的刻蚀孕育时间(incubation time)，造成对SiN的刻蚀，影响选择比的提升。
在第二吹扫步中，NH 3仍持续供应，可以使连续供应的NH 3气体充分浸渍晶圆表面，以使晶圆表面在下一次刻蚀步之前预先吸附足量的NH 3，从而当通入HF时，缩短了气体混合和附着于晶圆表面发生刻蚀反应的时间，可加快下一次刻蚀步的刻蚀气体反应速率，提高刻蚀效率。
从而，在确保单次工艺不刻蚀SiN的情况下，最大限度拓展工艺窗口，以最大限度的提升SiO 2的刻蚀。然后通过多次循环刻蚀，最终实现较高的SiO 2/SiN刻蚀选择比。
上述通气顺序中，在第二刻蚀步与第二吹扫步中，NH 3是一直保持通气状态，而HF是脉冲式供气。在一些实施例中，也可以将两种气体对换，即HF是一直保持通气状态，而NH 3是脉冲式供气。通过优化工艺参数，同样可以获得较好的刻蚀孕育时间(incubation time)，实现高选择比。其原因在于，在无NH 3催化剂存在的情况下，HF气体不会刻蚀SiO 2及SiN。
在一些实施例中，考虑到刻蚀反应生成物沉积于晶圆表面，吸附刻蚀气体难以吹扫除尽而造成对氮化硅膜的加速刻蚀，且沉积于氧化硅膜上的反应副产物部分地阻碍了刻蚀气体与SiO 2的直接接触反应，降低了SiO 2的刻蚀速率，从而一方面造成SiN的过度刻蚀，一方面阻碍了SiO 2的刻蚀，使选择比降低。因此在整个刻蚀工艺周期中，将表面去除步骤与刻蚀步骤完全分开，如图5所示，即表面去除步骤结束后，晶圆W移出整机刻蚀系统，进入前开式晶圆传送盒(Front Opening Unified Pod，FOUP)中，然后再重新开始， 进行刻蚀工艺。其中，刻蚀工艺根据需要决定是否需要进行多次大循环刻蚀。大循环的主要目的是充分升华排出反应副产物，由于排除了反应副产物对SiO 2刻蚀速率的抑制作用，增加大循环次数可以提升SiO 2的刻蚀量。其中，升华处理的温度大于等于180℃，以保证充分升华排出晶圆W表面残留的刻蚀反应物和副产物。
具体的，如图5所示，整个刻蚀工艺包括：
S100，表面去除工艺，其依次包括：
S110，表面去除步骤准备开始阶段；
S120，将晶圆W送入刻蚀工艺腔进行表面去除步骤；
S130，将晶圆W取出放入升华腔加热充分升华排出晶圆W表面上的表面去除步骤产物；
S140，将除尽表面去除步骤产物的晶圆W取出放入冷却腔冷却；
S150，将晶圆W放入晶圆传送盒中静置几分钟，再进行刻蚀工艺S200，或者在真空腔中静置几分钟。
静置时长不超过5分钟。从而，脱离冷却腔室静置后使一些游离于晶圆W表面的反应物或刻蚀气体进一步挥发脱离晶圆W表面，并且，脱离了冷却腔室内残存的游离成分环境，利于使晶圆W表面刻蚀气体和残留物完全析出挥发净化。静置一定时间可使SiN表面原子间化学反应应力抵消，使原子结构排布规律，提高了表面平整度，减少了SiN表面对刻蚀气体的吸附和接触面积。同时，静置所处环境可以是FOUP内或真空腔室中，由于SiN在常温下短时间内不易氧化，因此，冷却后的晶圆W可于FOUP内静置几分钟而不会再次生成氧化变性层。
S200，刻蚀工艺，其依次包括：
S210，刻蚀准备阶段；
S220，将晶圆W送入刻蚀工艺腔进行刻蚀；
S230，将晶圆W取出放入升华腔加热充分升华排出晶圆表面上的刻蚀产物；
S240，将除尽刻蚀产物的晶圆W取出放入冷却腔冷却。
S250，重复步骤S220至步骤S240，直至氧化硅膜刻蚀量满足目标刻蚀量，然后放入晶圆传送盒中结束。
其中，重复步骤S220至步骤S240相比于直接在工艺腔中升华吹扫可以进一步充分升华排出反应副产物，使晶圆W表面的反应副产物得以除尽，避免因反应副产物的沉积导致可是速率的下降以及刻蚀SiO 2/SiN的刻蚀选择比的降低。
在一些实施例中，可以简化上述步骤，如图6所示，表面去除步骤S100’与刻蚀步骤S200’衔接进行：步骤S120结束后，经过步骤S130和步骤S140的升华和冷却处理后，直接进行刻蚀步骤S200’，不再出整体刻蚀系统，不进入晶圆传送盒。此时需要强化表面表面去除步骤S100’的步骤S130，保证表面去除步骤副产物处理干净，否则会影响SiN的刻蚀。
示例2给出了不同刻蚀衔接步骤的SiO 2/SiN选择比实验对照，从中可以看出，表面去除步骤与刻蚀步骤分开进行，即将经步骤S140冷却后的晶圆W取出脱离整个系统然后放入晶圆传送盒中或者在真空腔中静置几分钟，与直接将经步骤S140在冷却腔冷却后的晶圆W放入刻蚀步骤S200中刻蚀相比，选择比有明显提升。
在一些实施例中，为了精确掌握晶圆W表面上的表面变性层厚度，从而精准控制与可是循环次数和单步时间步长，在步骤S110的表面去除步骤准备开始阶段中，先检测晶圆表面上的表面变性层厚度，以基于表面变性层厚度确定表面去除步骤的循环次数。从而针对性的实施所述表面去除步骤，保证除尽表面变性层的同时，避免过度刻蚀。
特别的，当检测到表面变性层厚度为零时，表面去除步骤的循环次数为 零，即跳过表面去除步骤工艺中的步骤S120至步骤S150，直接进入步骤S200。从而在确保没有表面变性层影响高选择比刻蚀的同时，简化工艺，提升效率。
在一些实施例中，步骤S210包括对晶圆W表面上的表面变性层厚度的再次检测，以确保在进入步骤S220之前，晶圆W表面上没有氧化变性层，以确保高选择比的实现。
在一些实施例中，刻蚀反应与固态生成物的升华在同一个腔室中实现，即刻蚀量的提升通过增加刻蚀与吹扫的循环次数来实现，实际工艺时，仅增加自动化工艺配方(recipe)中的循环次数即可，晶圆不需要频繁进出工艺腔室。也可以将刻上述两个步骤在分别在刻蚀腔与升华腔中分开完成，实际工艺时，晶圆需要反复在两个腔室中循环。此外，还可以将上述两种方法结合起来。分腔处理有利于使晶圆脱离原反应环境氛围，避免原腔室游离的刻蚀气体和反应副产物在晶圆表面上二次沉降以及抑制晶圆表面的上述成分的升华排净。
在一些实施例中，对刻蚀工艺参数进行改进，降低刻蚀气体供气压力、降低NH3气体比例等方式将刻蚀步骤的初始刻蚀速率降低后，同样可以用于表面去除步骤工艺。
在一些实施例中，刻蚀步的单步刻蚀时间在满足单步刻蚀时间不小于SiO 2膜刻蚀孕育时间的情况下，该单步刻蚀时间相对于SiN膜的刻蚀孕育时间更接近SiO 2膜的刻蚀孕育时间，从而保障高SiO 2/SiN选择比的实现。即SiO 2膜的刻蚀孕育时间≤第一刻蚀时长＜第二刻蚀时长<<SiN膜的刻蚀孕育时间。
如示例3所示，在满足单步刻蚀时间不小于SiO 2膜的刻蚀孕育时间的情况下，单步刻蚀时间远小于SiN膜的刻蚀孕育时间可以进一步避免由吹扫不及时不充分导致的刻蚀气体和刻蚀反应产物附着在晶圆W表面的时间延长 至接近甚至超过SiN膜的刻蚀孕育时间，从而，单步刻蚀时间越小，越能够为吹扫提供响应时间，从而，在接近甚至超过SiN膜刻蚀孕育时间之前，除尽刻蚀气体和刻蚀反应产物，避免发生对SiN膜的刻蚀。且单步刻蚀时间较长会使刻蚀反应产物过多地附着沉积在晶圆W表面，造成升华吹扫除尽困难，从而导致进一步吸附刻蚀气体，对SiN膜造成刻蚀。由此，单步刻蚀时间相对于SiN膜的刻蚀孕育时间更接近SiO 2膜的刻蚀孕育时间，可以保障高SiO 2/SiN的刻蚀选择比的实现。
为满足上述刻蚀方法的实施例的工艺要求，本发明实施例提出了一种刻蚀装置，用于在形成于晶圆W表面上的氮化硅膜和氧化硅膜之间选择性地刻蚀氧化硅膜，如图7所示，该刻蚀装置包括：工艺腔210，该工艺腔210包括气体供应单元和基座240，该气体供应单元依次包括供气气路、匀流腔220和气体分配盘230，供气气路依次包括气源段和预混段，气源段分别输出供应单一气源并在交汇于预混段中预混。具体的，气源段包括HF气源311、N 2气源312和NH 3气源313，以及分别控制上述气源的第一质量流量控制器321、第二质量流量控制器322、第三质量流量控制器323和第四质量流量控制器324。第一质量流量控制器321控制HF气源311的供气量，第四质量流量控制器324控制NH 3气源313的供气量，N 2气源312具有两路气路出口，分别由第二质量流量控制器322和第三质量流量控制器323控制。第一质量流量控制器321和第二质量流量控制器322所控气路由第一汇合点331汇合，第三质量流量控制器323和第四质量流量控制器324所控气路由第二汇合点332汇合，第一汇合点331所在气路与第二汇合点332所在气路由第三汇合点333并通入匀流腔220中，然后在匀流腔220中充分混合。之后，混合后的气体由单一气体分配盘230喷到晶圆W待处理表面上，匀流腔220可使通入气体在匀流腔220中充分混合后再经由气体分配盘230喷出去，从而可有效提高刻蚀效率。汇合点提前后，可以确保流出气体分配盘230表面的气 体中具有较高浓度的NH 4F。由于HN 4F低温下为固态，故，需要将气体分配盘230的加热至120度以上。
在一些实施例中，本发明实施例将基座240设置高温加热装置，基座240温度提升至120度甚至更高，确保反应生成的固态产物会可快速升华而脱离晶圆W表面，防止其阻碍刻蚀剂在晶圆W表面的吸附。并且，将基座240设置为可升降基座，同时对工艺腔210进行缩小化处理，去除腔室中的适配器，通过腔室210与基座240的升降配合，尽量缩小晶圆W表面与气体分配盘230间的空间体积。这有助于刻蚀气体的快速排除，避免因残气滞留时间过长，超出SiN的刻蚀孕育时间(incubation time)，造成对SiN的刻蚀，影响选择比的提升。
在一些实施例中，供气气路依次包括气源段和预混段，该气源段分别输出供应单一气源并在交汇于预混段中预混。在预混段中进行预混进一步提高了刻蚀反应气体的预混效果，提高刻蚀效率。
在一些实施例中，气体供应单元和基座设有加热装置，以使刻蚀工艺温度不小于120℃。一方面防止预混生成的NH 4F因温度低而凝结堵塞供气道，另一方面，可以加速晶圆表面的反应产物的升华速率，提高刻蚀速率的同时，避免了反应产物的沉积导致的选择比的下降。
根据本发明实施例的另一个方面，提供一种空气隙型介电层，采用上述刻蚀方法制备，从而获得的空气隙型介电层具有高选择比。
根据本发明实施例的另一个方面，提供一种动态随机存取存储器，包括上述空气隙型介电层，以使动态随机存取存储器的性能提升。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置和方法，也可以通过其它的方式实现。以上所描述的装置实施例仅仅是示意性的。上述刻蚀方法如果以软件功能模块的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的 技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本发明各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
效果示例
现在，将描述各种示例以验证本发明公开的实施例的效果。
示例1：
针对于有表面氧化变性层的情况，如表2所示，本发明将样片c和d分别进行两种刻蚀方法的对比，其中c进行表面去除步骤+刻蚀步骤，d仅进行刻蚀步骤。两样品的SiO 2刻蚀量基本相当，SiN的刻蚀量存在明显差异。由此说明，表面去除步骤工艺可显著提升整体刻蚀选择比。
表2 不同刻蚀工艺步骤的SiO 2/SiN选择比实验对照表
Figure PCTCN2020123648-appb-000004
示例2：
对于表面去除步骤和刻蚀步骤之间的衔接步骤对比，如表3所示。
表3不同刻蚀衔接步骤的SiO 2/SiN选择比实验对照表
Figure PCTCN2020123648-appb-000005
Figure PCTCN2020123648-appb-000006
由此可以得出，可选的，表面去除步骤与刻蚀步骤分开进行。即表面去除步骤工艺完成后，晶圆需要进行充分的加热处理，将表面生成的反应副产物排除干净后，方可进行后续的刻蚀工艺。通常做法是表面去除步骤工艺结束后，晶圆传输至升华腔室进行充分的升华，然后再传输至工艺腔进行刻蚀工艺。而不在工艺腔室先后一次性的完成表面去除步骤和刻蚀工艺。表3的对比试验说明了表面去除步骤与刻蚀步骤分开进行，可避免SiN刻蚀量的大幅增加，从而提高选择比。
示例3：
针对于无表面氧化变性层的情况，采用上述方式，经过实验测试，本发明绘制出在120℃工艺温度下，某工艺条件SiO 2和SiN刻蚀量随刻蚀时间的变化曲线，如图8所示。由图可知，SiO 2和SiN刻蚀量开始明显增加的刻蚀时间点分别为1->2s和5->6s，由此推断该条件下，SiN的incubation time约为5s-6s，SiO 2的incubation time约为1s-2s。同时测试出，SiN未刻蚀前提下的SiO 2最大刻蚀量约为
Figure PCTCN2020123648-appb-000007
需要说明的是，不同的工艺参数(如压力、气体流量、温度等)，incubation time是不同的，以此方法能实现的SiO 2/SiN的选择比也是不同的。图8是在120℃、8torr、流量为20sccm的HF、流量为100sccm的NH 3、流量为450sccm的N 2条件下获得的实验数据。
鉴于以上实验结果，本发明实施例通过单步刻蚀时间与循环次数等参数的细化调试，在SiO 2刻蚀量高于
Figure PCTCN2020123648-appb-000008
的情况下，获得了不低于500：1的选择比，部分工艺的选择比数据甚至达1000:1，明显高于常规的氨气催化工 艺。
通过表4可得出，在满足单步刻蚀时间不小于SiO 2膜刻蚀孕育时间的情况下，单步刻蚀时间越小，SiO 2/SiN选择比越高，本发明分析得出，在满足单步刻蚀时间不小于SiO 2膜刻蚀孕育时间的情况下，单步刻蚀时间远小于SiN膜刻蚀孕育时间可以进一步避免由吹扫不及时不充分导致的刻蚀气体和刻蚀反应产物附着在晶圆W表面的时间延长至接近甚至超过SiN膜刻蚀孕育时间，从而，单步刻蚀时间越小，越能够为吹扫提供响应时间，从而，在接近甚至超过SiN膜刻蚀孕育时间之前，除尽刻蚀气体和刻蚀反应产物，避免发生对SiN膜的刻蚀。且单步刻蚀时间较长会使刻蚀反应产物过多地附着沉积在晶圆W表面，造成升华吹扫除尽困难，从而导致进一步吸附刻蚀气体，对SiN膜造成刻蚀。
因此，可选的，单步刻蚀时间相对于SiN膜刻蚀孕育时间更接近SiO 2膜刻蚀孕育时间，从而保障高SiO 2/SiN选择比的实现。
表4 不同单步刻蚀时间与循环次数的SiO 2/SiN选择比实验对照表
Figure PCTCN2020123648-appb-000009
虽然，上文中已经用一般性说明及具体实施例对本发明作了详尽的描述，在本发明基础上，可以对之作一些修改或改进，这对本领域技术人员而言是显而易见的。因此，在不偏离本发明精神的基础上所做的这些修改或改进，均属于本发明要求保护的范围。

Claims (20)

  1. 一种刻蚀方法，用于在形成于晶圆表面上分布的氮化硅膜和氧化硅膜之间选择性地刻蚀所述氧化硅膜，其特征在于，包括：
    表面去除步骤：以第一刻蚀速率刻蚀所述氧化硅膜，并清除覆于所述氮化硅膜的表面上的表面变性层；以及
    刻蚀步骤：以第二刻蚀速率刻蚀所述氧化硅膜，
    其中，所述第一刻蚀速率小于所述第二刻蚀速率。
  2. 如权利要求1所述的刻蚀方法，其特征在于，所述表面去除步骤包括：
    第一刻蚀步：在第一预定压力下以及第一刻蚀时长内，以刻蚀气体刻蚀所述晶圆表面，以及
    第一吹扫步：在第一吹扫压力下以及第一吹扫时长内，以吹扫气体吹扫所述晶圆，并且
    循环进行所述第一刻蚀步和所述第一吹扫步，直至清除所述表面变性层为止。
  3. 如权利要求2所述的刻蚀方法，其特征在于，所述刻蚀步骤包括：
    第二刻蚀步：在第二预定压力下以及第二刻蚀时长内，以刻蚀气体选择性地刻蚀所述氧化硅膜，以及
    第二吹扫步：在第二吹扫压力下以及第二吹扫时长内，以所述吹扫气体吹扫所述晶圆，并且
    重复循环所述第二刻蚀步和第二吹扫步，直至达到所述氧化硅膜的目标刻蚀量。
  4. 如权利要求3所述的刻蚀方法，其特征在于，所述第一预定压力小于所述第二预定压力。
  5. 如权利要求4所述的刻蚀方法，其特征在于，所述第一预定压力的范围为1Torr-3Torr；所述第二预定压力的范围为5Torr-10Torr。
  6. 如权利要求3所述的刻蚀方法，其特征在于，所述第一刻蚀时长小于 所述第二刻蚀时长。
  7. 如权利要求6所述的刻蚀方法，其特征在于，所述第一刻蚀时长的范围为1s-3s；所述第二刻蚀时长的范围为1s-5s。
  8. 如权利要求3所述的刻蚀方法，其特征在于，所述刻蚀气体包括第一组分气体和第二组分气体，其中，所述第一组分气体为氟化氢气体，所述第二组分气体为氨气。
  9. 如权利要求8所述的刻蚀方法，其特征在于，所述第二吹扫步，还包括，在所述第二吹扫压力下以及所述第二吹扫时长内，以所述第二组分气体吹扫所述晶圆。
  10. 如权利要求2所述的刻蚀方法，其特征在于，所述吹扫气体包括氮气和惰性气体中的至少一种。
  11. 如权利要求8所述的刻蚀方法，其特征在于，在所述表面去除步骤中，所述第一组分气体以第一流量供应；在所述刻蚀步骤中，所述第一组分气体以第二流量供应；其中，所述第一流量大于所述第二流量。
  12. 如权利要求1所述的刻蚀方法，其特征在于，所述表面去除步骤和所述刻蚀步骤的工艺温度均不小于120℃。
  13. 如权利要求1-12任一项所述的刻蚀方法，其特征在于，在所述表面去除步骤和所述刻蚀步骤之间还包括，对所述晶圆进行加热升华处理，并在所述升华处理之后，对所述晶圆冷却至室温。
  14. 如权利要求13所述的刻蚀方法，其特征在于，所述升华处理的温度大于等于180℃。
  15. 如权利要求13所述的刻蚀方法，其特征在于，在所述刻蚀步骤之前还包括，将升华冷却后的所述晶圆取出并静置预设时间。
  16. 如权利要求2-11任一项所述的刻蚀方法，其特征在于，在所述表面去除步骤之前，还包括，检测所述晶圆表面上的表面变性层厚度，以基于所述表面变性层厚度确定所述第一刻蚀步和所述第一吹扫步的循环次数。
  17. 如权利要求3所述的刻蚀方法，其特征在于，所述第二刻蚀步中的总气流量与所述第二吹扫步中的总气流量相同。
  18. 如权利要求1所述的刻蚀方法，其特征在于，所述表面变性层至少由硅、氮和氧三种元素组成。
  19. 一种空气隙型介电层，其特征在于，采用如权利要求1-18任一所述的刻蚀方法制备。
  20. 一种动态随机存取存储器，其特征在于包括如权利要求19所述的空气隙型介电层。
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