WO2017045598A1 - 一种将半导体衬底主体与其上功能层进行分离的方法 - Google Patents

一种将半导体衬底主体与其上功能层进行分离的方法 Download PDF

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WO2017045598A1
WO2017045598A1 PCT/CN2016/098943 CN2016098943W WO2017045598A1 WO 2017045598 A1 WO2017045598 A1 WO 2017045598A1 CN 2016098943 W CN2016098943 W CN 2016098943W WO 2017045598 A1 WO2017045598 A1 WO 2017045598A1
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layer
semiconductor substrate
semiconductor
functional layer
separating
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PCT/CN2016/098943
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English (en)
French (fr)
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胡兵
马亮
裴晓将
刘素绢
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胡兵
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Priority to CN201680053855.8A priority Critical patent/CN108140608B/zh
Priority to CN202210457276.7A priority patent/CN114743926A/zh
Priority to EP16845712.5A priority patent/EP3352207B1/en
Priority to EP23186634.4A priority patent/EP4250337A3/en
Priority to DE112016003716.3T priority patent/DE112016003716T5/de
Priority to JP2018524527A priority patent/JP6602976B2/ja
Priority to KR1020187006299A priority patent/KR102313428B1/ko
Priority to KR1020217032596A priority patent/KR20210127791A/ko
Publication of WO2017045598A1 publication Critical patent/WO2017045598A1/zh
Priority to US15/868,300 priority patent/US10734274B2/en
Priority to US16/904,516 priority patent/US20200321242A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B43/00—Operations specially adapted for layered products and not otherwise provided for, e.g. repairing; Apparatus therefor
    • B32B43/006—Delaminating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes

Definitions

  • the present invention relates to the field of manufacturing electronic devices, and in particular to a method of separating a semiconductor substrate body from its upper functional layer.
  • Semiconductor materials are widely used in the manufacture of electronic devices, and the application of semiconductor materials is closely related to people's daily life and cutting-edge technology.
  • Semiconductor materials have evolved from the first generation represented by silicon and germanium in the last century to the third generation represented by silicon carbide and gallium nitride.
  • the semiconductor substrate is indispensable, and the cost of the semiconductor substrate is directly related to the cost of the electronic device fabricated on the substrate.
  • the first and second generation semiconductor substrates are mostly grown by solution method, and the third generation semiconductor substrates are mainly prepared by vapor phase growth such as chemical vapor deposition (CVD), metal chemical vapor deposition (MOCVD), and physical vapor transmission (PVT).
  • CVD chemical vapor deposition
  • MOCVD metal chemical vapor deposition
  • PVT physical vapor transmission
  • the production cost of the third generation semiconductor substrate is significantly higher than the production cost of the first generation and second generation semiconductor substrates. Therefore, reducing the cost of the semiconductor substrate, particularly reducing the cost of the third generation semiconductor substrate, can bring great benefits to the popularization and application of the third generation semiconductor electronic device.
  • Ion-cut thin film transfer technology was used to fabricate SOI (silicon on insulator) substrates.
  • Ion-cut film transfer technology is a technique for separating substrate and substrate film layers based on ion implantation.
  • the SOI fabrication process is to first fabricate a layer of silicon dioxide on the surface of the donor silicon substrate, and then accelerate the hydrogen ions to the surface of the silicon substrate on which the oxide layer has been formed. The hydrogen ions are accelerated at high voltage.
  • the ion damage layer Under the action, passing through the silicon dioxide layer to the underlying silicon substrate and staying in the silicon substrate, causing ion damage, the ion damage layer is under the surface of the silicon substrate The depth depends on the level of the ion acceleration voltage; the higher the voltage, the deeper the ion damage layer is below the surface of the silicon substrate.
  • the ion damage layer is located under the silicon substrate at a distance of 1 micrometer to 20 micrometers from the silicon dioxide layer, and the donor silicon substrate after ion implantation is bonded to the acceptor silicon substrate on the surface of the silicon dioxide, and the bonded two
  • the silicon substrate is annealed at a temperature of 200 ° C to 500 ° C.
  • the annealing process hydrogen ions are polymerized in the damaged layer to form hydrogen molecules, so that the original micro damage is laterally extended along the damaged layer, causing the donor silicon substrate to be in the damaged layer.
  • the donor silicon substrate can be reused, and the separated acceptor silicon substrate is heat treated, and the surface silicon atoms are redistributed to eliminate the damage caused by ion implantation, and a silicon single crystal film having a thickness of micrometer is formed on the silicon oxide oxide layer.
  • the fabrication of the electronic device is performed on a silicon single crystal film, and the acceptor substrate only serves as a support, which is an SOI substrate.
  • the ion-cut film transfer technique is also used for the preparation of other semiconductor thin film substrates, such as transfering thin films of GaN, SiC, etc. onto a silicon or oxide substrate to reduce the substrate price, which is different from the SOI substrate.
  • GaN and SiC are usually transferred to an insulator, and it is not necessary to form an oxide layer on the GaN or SiC donor substrate.
  • ion implantation depth, ion implantation dose per unit area, surface bonding of the acceptor and donor substrate, and annealing after bonding are the main components of ion-cut film transfer technology.
  • the surface bonding of the acceptor and donor substrate is a key step in the success of ion-cut film transfer technology. If the surface of the acceptor and the donor substrate are not well bonded, the acceptor and the donor substrate may be separated during the annealing process, and the film on the damaged layer may not be effectively supported, and the film transfer fails or the film is damaged. In order to ensure the bonding of the donor and the acceptor substrate, the processing requirements of the substrate on the bonding surface are very high, which is a great challenge for the processing of a high hardness semiconductor substrate such as SiC. In addition, the surface of the successfully separated film due to surface flatness and ion bombardment damage also requires heat treatment or surface reworking.
  • Tear stripping method needs to be controlled by precise control
  • the stress of the force introduction layer controls the thickness of the separation of the substrate film, which causes difficulty for mass production.
  • the peeling peeling method has not been reported to successfully separate a hard substrate such as SiC.
  • the present invention can control the thickness of the separated film by controlling the ion implantation depth, and the stress in the stress introduction layer does not need to be precisely controlled in the tear stripping technique, which facilitates mass production.
  • it is not necessary to bond the tape on the stress-introducing layer, and a thick stress-introducing layer can be produced as a support for the separation film, a conductive layer, and the like.
  • the present invention can also separate a hard semiconductor substrate such as silicon carbide (SiC).
  • SiC silicon carbide
  • the technical problem to be solved by the present invention is that the existing ion-cut film transfer technology is complicated in process, and is greatly affected by the ion implantation depth, the ion implantation dose per unit area, and the bonding strength of the acceptor substrate and the donor substrate; especially the third generation.
  • semiconductors such as SiC
  • the bonding of the donor to the acceptor substrate is not well resolved.
  • the present invention is more suitable for mass production, can separate a hard semiconductor substrate such as SiC, and produces less separation defects, and has less influence on the device.
  • a method for separating a semiconductor substrate body from an upper functional layer thereof comprising the following steps:
  • Step 2) preparing a functional layer on the upper surface of the semiconductor substrate after the step 1);
  • Step 3 Separating the semiconductor substrate and the functional layer thereon at the ion damage layer.
  • the invention has the beneficial effects that the method of the invention first performs the preparation of the functional layer or the semiconductor electronic device on the substrate after the ion implantation, and then separates in the ion damage layer, and the invention directly functions on the original surface of the semiconductor substrate.
  • the fabrication of layers or semiconductor electronic devices avoids the drawbacks of conventional ion-cut film transfer techniques on the separation surface.
  • the depth of the ion is determined by the depth of the semiconductor substrate
  • the thickness of the film, the semiconductor substrate of the invention has the same effect as the SOI film, and does not require a bonding process, which reduces the production process and reduces the production cost;
  • the existing ion-cut film transfer substrate needs heat treatment or polishing
  • the present invention performs the preparation of a functional layer or a semiconductor electronic device on the surface of the original substrate, and has the same effect;
  • the ion implantation dose of the existing ion-cut film transfer substrate in the preparation process needs to be reached or Exceeding the dose capable of generating bubbles on the surface of the substrate, the ion implantation dose of the present invention only needs to ensure that no bubble damage is generated on the surface of the substrate.
  • the present invention can also be improved as follows.
  • the semiconductor substrate comprises: a semiconductor single wafer, or a semiconductor single wafer and a semiconductor epitaxial layer epitaxially grown on the semiconductor single wafer, or a semiconductor epitaxial layer epitaxially grown on the oxide single wafer.
  • the material of the semiconductor substrate is Si, Ge, Si x Ge 1-x , SiC, GaAs, lnP, ln x Ga 1-x P, ln x Ga 1-x As, CdTe, AN, GaN, InN Or any one of Al x ln y Ga 1-xy N, wherein x and y satisfy the condition that 0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1 , and 0 ⁇ x + y ⁇ 1.
  • the functional layer comprises: a semiconductor electronic device prepared directly on the upper surface of the semiconductor substrate, or a semiconductor epitaxial layer epitaxially grown on the surface of the semiconductor substrate, or a semiconductor epitaxial layer epitaxially grown on the surface of the semiconductor substrate And semiconductor electronic devices fabricated on a semiconductor epitaxial layer.
  • the semiconductor epitaxial layer contains Si, Ge, Si x Ge 1-x , SiC, GaAs, lnP, ln x Ga 1-x P, ln x Ga 1-x As, CdTe, AN, GaN, At least one of InN and Al x ln y Ga 1-xy N, wherein x and y satisfy the condition that 0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1 , and 0 ⁇ x + y ⁇ 1.
  • the semiconductor epitaxial layer includes Al x ln y Ga 1-xy N
  • x and y may be graded or abrupt in the epitaxial layer.
  • the epitaxial method of the semiconductor epitaxial layer includes chemical vapor deposition, plasma enhanced chemical vapor deposition, metal organic chemical vapor deposition, molecular beam epitaxy, hydride vapor phase epitaxy, Physical vapor transport and liquid phase epitaxy.
  • ions implanted on the surface of the semiconductor substrate include ions formed of at least one element of H, He, Ar, and Ne or ions generated by a gas formed of the element.
  • the step 2) further includes: forming a stress introduction layer on the functional layer, wherein a tensile stress exists in the stress introduction layer, and the stress introduction layer generates a compressive stress in the functional layer.
  • the stress introduction layer is made of a metal material, and the metal material is Ni, Au, Cu, Pd, Ag, Al, Sn, Cr, Ti, Mn, Co, Zn, Mo, W, Zr, V, Ir, At least one of Pt and Fe.
  • the stress introduction layer may be a non-metal polymer material.
  • the stress-introducing layer is a metal material
  • the stress-introducing layer is used as an ohmic contact layer or a Schottky contact layer of an electronic device on a functional layer.
  • a rigid or flexible support layer is formed on the stress-introducing layer.
  • a rigid or flexible support layer is formed on the functional layer.
  • FIG. 1 is a front elevational view showing the structure of a semiconductor substrate of the present invention
  • FIG. 2 is a schematic view showing the implantation of ions of the present invention into a semiconductor substrate via the upper surface of the semiconductor substrate;
  • FIG. 3 is a schematic structural view of an ion-damaged layer of a semiconductor substrate after ion implantation according to the present invention
  • FIG. 4 is a schematic structural view showing an epitaxial layer formed on the surface of the semiconductor substrate of FIG. 3;
  • FIG. 6 is a schematic structural view of preparing a stress introduction layer on the epitaxial layer of FIG. 4;
  • FIG. 7 is a schematic structural view of preparing an operation layer on the stress introduction layer of FIG. 6;
  • Figure 8 is a schematic view showing the structure in which a rigid substrate is directly bonded to the epitaxial layer of Figure 4 and separated.
  • FIG. 3 is an ion-implanted semiconductor substrate layer 1.
  • the semiconductor substrate layer is divided into a semiconductor substrate body layer 2, an ion damage layer 3, and an ion damage layer 3.
  • the semiconductor substrate may be a semiconductor single wafer, a semiconductor single wafer may be used, and a semiconductor epitaxial layer may be epitaxially grown on the semiconductor single wafer, or a semiconductor epitaxial layer may be epitaxially grown on the non-semiconductor and the oxide single wafer.
  • the surface of the substrate layer is implanted.
  • the ions implanted on the surface of the semiconductor substrate layer include ions formed of at least one element of H, He, Ar, and Ne or ions generated by a gas formed of the element.
  • Embodiment 1 ion implantation is performed on the upper surface of the semiconductor substrate layer 1 with an ion implantation depth of 0.1 ⁇ m to 100 ⁇ m, preferably 5 ⁇ m, 10 ⁇ m, 15 ⁇ m, and 20 ⁇ m; after the ion implantation, an ion damage layer 3 is formed under the surface of the semiconductor substrate layer 1
  • the functional layer can then be directly prepared on the substrate film layer 4.
  • the functional layer of this embodiment is a semiconductor electronic device such as a MOS, MOSFET device or the like.
  • the rigid substrate 8 can be directly bonded to the semiconductor electronic device.
  • the rigid substrate can be a semiconductor, an oxide crystal, a metal, a glass or a ceramic material, and the semiconductor substrate body layer and the substrate film layer are ionized by an outward pulling force.
  • the damage layer is separated, and at this time, the tensile force required for the separation is much larger than the tensile force required when the stress is introduced into the layer.
  • the functional layer may be a semiconductor electronic device that is not completed on the substrate film layer 4. After the semiconductor substrate is separated at the ion damage layer, the remaining semiconductor is completed on the substrate film layer 4. The production of electronic devices.
  • Embodiment 2 ion implantation is performed on the upper surface of the semiconductor substrate layer 1 with an ion implantation depth of 0.5 ⁇ m to 50 ⁇ m, preferably 5 ⁇ m, 10 ⁇ m, 15 ⁇ m, and 20 ⁇ m; after ion implantation in the semiconductor liner An ion damage layer 3 is formed under the surface of the bottom layer 1; a functional layer is prepared on the ion implantation surface of the substrate film layer 4.
  • the functional layer of this embodiment is a semiconductor epitaxial layer 5 epitaxially grown on the surface of the semiconductor substrate layer 1, also It may be a semiconductor epitaxial layer 5 epitaxially grown on the upper surface of the semiconductor substrate layer 1 and a semiconductor electronic device fabricated on the semiconductor epitaxial layer 5.
  • the epitaxial method of the semiconductor epitaxial layer 5 includes chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), physics. Gas phase transport (PVT) and liquid phase epitaxy (LPE).
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • MOCVD metal organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • HVPE hydride vapor phase epitaxy
  • PVPE hydride vapor phase epitaxy
  • physics Gas phase transport (PVT) and liquid phase epitaxy (LPE).
  • the semiconductor epitaxial layer 5 may be a single epitaxial layer structure or more than one epitaxial structure, and the epitaxial layer may change conductivity and conductivity type, such as p, n type, via doping. As shown in FIG. 5, the semiconductor epitaxial layer 5 may include a first epitaxial layer 51, a second epitaxial layer 52, a third epitaxial layer 53, and a fourth epitaxial layer 54.
  • the first epitaxial layer is AlN
  • the second epitaxial layer is n-type GaN
  • the third epitaxial layer is a multi-layer quantum well In x Ga (1-x) N and a barrier GaN
  • fourth The epitaxial layer is p-type GaN, where 0 ⁇ x ⁇ 1, and this embodiment only gives an application of the epitaxial layer, and the structure of the epitaxial layer is not limited thereto.
  • the stress introduction layer 6 is formed on the semiconductor epitaxial layer 5, and the stress introduction layer itself is subjected to tensile stress.
  • the stress-introducing layer 6 is formed by evaporation, sputtering, electroplating, coating, or spin coating; the stress-introducing layer may be made of a metal material, which is Ni, Au, Cu, Pd, Ag, Al, Sn, Cr, At least one of Ti, Mn, Co, Zn, Mo, W, Zr, V, Ir, Pt, and Fe; the role of the stress-introducing layer is to generate compressive stress in the functional layer to facilitate the semiconductor substrate main layer and the substrate film Peeling of the layers.
  • the stress-introducing layer may also be a non-metallic polymer material, which is an epoxy resin, and the epoxy resin is dried as a stress-introducing layer at 150 ° C, and the functional layer and the stress-introducing layer are used.
  • the stress separation functional layer due to the difference in thermal expansion coefficient during cooling.
  • the epoxy resin is dried as a stress-introducing layer at room temperature, and the temperature is lowered to a liquid nitrogen temperature separation.
  • the stress-introducing layer is a metal material, it can be used as an ohmic contact layer or a Schottky contact layer of the electronic device on the functional layer, such as a stress-introducing layer on the p-GaN of the epitaxial layer of the LED structure.
  • the stress-introducing layer on the n-type epitaxial layer of the SiC diode can be used as a Schottky contact layer.
  • an operation layer 7 is prepared on the stress-introducing layer 6, and the operation layer 7 is easy to handle for separation, and a tape, a polymer or the like can be used.
  • the handling layer can also be a rigid operating layer such as a semiconductor, oxide, metal, glass or ceramic material.
  • the operation layer is not necessary, and when the stress introduction layer is sufficiently thick, it is not necessary to make an operation layer.
  • the rigid substrate 8 can be directly bonded to the functional layer and separated by an outward pulling force, and the direction of the arrow in Fig. 8 is the pulling direction.
  • the semiconductor substrate material of this embodiment adopts silicon carbide, and takes a 2 ⁇ (0001) crystal to a 6H crystal silicon carbide substrate as an example, and implants hydrogen ions at a tilt angle of 7° on the surface of the silicon carbide semiconductor substrate, and hydrogen ion implantation.
  • the energy is 400 keV, and the implantation dose of hydrogen ions is 5 ⁇ 10 16 cm -2 .
  • an ion damage layer is formed on the lower surface of the semiconductor substrate, as shown in Fig. 3; after ion implantation is completed, an appropriate temperature annealing process can be performed.
  • the damage effect of the enhanced ions in the damaged layer is different.
  • the annealing temperature is different.
  • the annealing temperature needs to be above 218 °C.
  • the annealing temperature needs to be 650. Above °C; the annealing process can also occur in the process of making the functional layer.
  • the dose of ion implantation needs to be combined with the energy of the implanted ions.
  • the surface damage caused by the ion-free bubbles and the spontaneous separation of the film-free layer ensure the successful implementation of this patented technology.
  • the ion-implanted silicon carbide semiconductor material substrate is epitaxially grown in an MOCVD reactor to epitaxially grow a semiconductor epitaxial layer (functional layer). As shown in FIG.
  • the semiconductor epitaxial layer includes an AlN buffer layer, Si-doped n in order from bottom to top.
  • a 10 ⁇ m thick Ni metal stress-introducing layer is sputtered on the epitaxial layer, and 200 ⁇ m-300 ⁇ m copper is electrolessly plated on the Ni metal stress-introducing layer as a further supporting layer and a stress-introducing layer, thereby making the semiconductor substrate main layer 2 Separation from the underlying film layer 4 and its functional layer, the separated semiconductor substrate body layer can be reused after polishing.
  • the semiconductor substrate material of this embodiment adopts silicon carbide, and takes a 2 ⁇ (0001) crystal to a 6H crystal silicon carbide substrate as an example, and implants hydrogen ions at a tilt angle of 7° on the surface of the silicon carbide semiconductor substrate, and hydrogen ion implantation.
  • the energy is 500 keV
  • the implantation dose of hydrogen ions is 7 ⁇ 10 16 cm -2 .
  • an ion damage layer is formed on the lower surface of the semiconductor substrate layer, as shown in FIG. 3 .
  • the ion-implanted silicon carbide semiconductor material substrate is epitaxially grown in an MOCVD reactor to epitaxially grow a semiconductor epitaxial layer (functional layer). As shown in FIG.
  • the semiconductor epitaxial layer includes an AlN buffer layer, Si-doped n in order from bottom to top.
  • a GaN layer, a multilayer quantum well In x Ga (1-x) N and a barrier GaN, Mg-doped p-type GaN layer, and the entire semiconductor epitaxial layer has a thickness of 4 ⁇ m.
  • the silicon substrate is directly bonded on the semiconductor epitaxial layer, and the silicon carbide substrate and the silicon substrate are respectively adsorbed on the two vacuum chucks, and the outward mechanical force is applied on the two vacuum chucks, and the functional layer and the semiconductor substrate layer are The semiconductor substrate body layer is separated at the ion damage layer.

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Abstract

一种将半导体衬底主体（2）与其上功能层进行分离的方法，包括以下步骤：在半导体衬底（1）上表面进行离子注入，离子注入深度为0.1μm-100μm，离子注入后在半导体衬底（1）表面下产生一层离子损伤层（3）；在半导体衬底（1）上表面制备功能层；将半导体衬底（1）和其上功能层进行分离。该方法在离子注入后的衬底（1）上先进行功能层的制备，然后在离子损伤层（3）进行分离，且直接在半导体衬底（1）表面进行电子器件的制备，由于离子的注入深度决定了半导体衬底（1）的厚度，半导体衬底（1）具有与SOI薄膜相同的作用效果，且不需要键合工艺，减少了生产工艺，降低了生产成本。

Description

一种将半导体衬底主体与其上功能层进行分离的方法 技术领域
本发明涉及电子器件的制造技术领域，具体涉及一种将半导体衬底主体与其上功能层进行分离的方法。
背景技术
半导体材料被广泛应用于电子器件的制造，半导体材料的应用与人们的日常生活和尖端科技都息息相关。半导体材料已经从上世纪以硅、锗为代表的第一代，发展到以碳化硅、氮化镓等为代表的第三代。无论是基于第一代、第二代或第三代半导体材料的电子器件制造工艺，都离不开半导体衬底，半导体衬底的成本直接关系着衬底上制作的电子器件的成本。第一代和第二代半导体衬底大都由溶体法生长制备，第三代半导体衬底则主要由气相生长制备如化学气相沉积(CVD)，金属化学气相沉积(MOCVD)，物理气相传输(PVT)，和氢化物气相外延(HVPE)，等。第三代半导体衬底的生产成本要明显高于第一代和第二代半导体衬底的生产成本。因此，降低半导体衬底的成本，特别是降低第三代半导体衬底的成本对于第三代半导体电子器件的普及应用会带来极大的好处。
上世纪90年代，离子切割薄膜转移技术(smart-cut)被用于制作SOI(silicon on insulator)衬底，离子切割薄膜转移技术是基于离子注入方法分离衬底与衬底薄膜层的技术。SOI制作工艺是首先在施主硅衬底表面制作一层微米量级厚度的二氧化硅层，然后将氢离子经高压加速打入表面已制作了氧化层的硅衬底，氢离子在高电压加速作用下，穿过二氧化硅层到达下面的硅衬底并停留在硅衬底中，产生离子损伤，离子损伤层在硅衬底表面下 的深度取决于离子加速电压的高低；电压越高，离子损伤层在硅衬底表面下的深度越深。通常离子损伤层位于硅衬底下距离二氧化硅层1微米到二十几微米处，离子注入后的施主硅衬底与受主硅衬底在二氧化硅表面进行键合，键合后的两片硅衬底经过一个200℃-500℃的温度退火，退火过程中，氢离子在损伤层内聚合形成氢气分子，使原来的微损伤沿着损伤层横向扩展，造成施主硅衬底在损伤层处分离。施主硅衬底可重新利用，而分离后的受主硅衬底经热处理，表面硅原子重新分布以消除离子注入造成的损伤，在二氧化硅氧化层上有一层微米厚度的硅单晶薄膜，其后电子器件的制作就在硅单晶薄膜上进行，受主衬底只是起到支撑作用，这就是SOI衬底。其后，离子切割薄膜转移技术也被用于其它半导体薄膜衬底制备，如转移GaN、SiC等薄膜到硅或氧化物衬底上，以降低衬底价格，与SOI衬底不同的是，因GaN和SiC通常转移到绝缘体上，GaN、SiC施主衬底上无需制作氧化层。在用离子切割薄膜转移技术制作薄膜衬底的过程中，离子注入深度，单位面积离子注入剂量，受主与施主衬底表面键合，以及键合后的退火是离子切割薄膜转移技术主要组成要素，而受主与施主衬底表面键合则是离子切割薄膜转移技术成败的关键一步。如果受主与施主衬底表面键合不好，在退火过程中，受主与施主衬底可能产生分离，损伤层上的薄膜得不到有效支撑，则薄膜转移失败、或损坏薄膜。为了保证施主与受主衬底的键合，对衬底在键合表面的加工要求非常高，这对SiC一类高硬度的半导体衬底的加工是一个很大的挑战。此外，成功分离后的薄膜表面因表面平整度和离子轰击造成的损伤，也需要热处理或表面再加工。
过去几年，Stephen,W.Bedell等用‘撕剥离(spalling)’法实现了硅,锗，砷化稼，氮化稼衬底上簿膜或簿膜器件的分离。撕剥离的工作原理是在半导体衬底上制作应力导入层，在应力导入层上粘连胶带，通过撕拉胶带造成衬底簿膜随应力导入层一起分离。撕剥离法需要通过精确控制应 力导入层的应力来控制衬底簿膜分离的厚度，为大规模生产造成困难。另外，尽管理论上可以,撕剥离法未见成功分离硬质衬底如SiC的报道。相较于撕剥离技术，本发明可通过控制离子注入深度控制分离的簿膜厚度，应力导入层中的应力无需像撕剥离技术中精确控制，为大规模生产带来便利。本发明无需在在应力导入层上粘连胶带，可制作厚应力导入层作为分离簿膜的支撑，及导电层等。此外，本发明还可分离硬质半导体衬底如碳化硅(SiC)。另一可能的优点是本发明分离的簿膜材料应比撕剥离技术分离的簿膜产生较少的分离缺陷，因本发明事先引入了损伤层。
发明内容
本发明所要解决的技术问题是现有的离子切割薄膜转移技术工艺复杂，受离子注入深度、单位面积离子注入剂量以及受主衬底和施主衬底键合强度影响很大；尤其是第三代半导体如SiC，施主与受主衬底的键合没有得到很好的解决。相较于撕剥离技术，本发明更适合大规模生产，可分离硬质半导体衬底如SiC，及产生较少的分离缺陷，对器件的影响小。
本发明解决上述技术问题的技术方案如下：一种将半导体衬底主体与其上功能层进行分离的方法，包括以下步骤：
步骤1)：在半导体衬底上表面进行离子注入，离子注入深度为0.1μm-100μm，离子注入后在半导体衬底表面下产生一层离子损伤层；
步骤2)：在经步骤1)处理后的半导体衬底上表面制备功能层；
步骤3)：将半导体衬底及其上的功能层在离子损伤层处进行分离。
本发明的有益效果是：本发明的方法在离子注入后的衬底上先进行功能层或半导体电子器件的制备，然后在离子损伤层进行分离，且本发明直接在半导体衬底原表面进行功能层或半导体电子器件的制备，避免了通常离子切割薄膜转移技术在分离面的缺陷。由于离子的注入深度决定了半导体衬底 薄膜的厚度，本发明的半导体衬底具有与SOI薄膜相同的作用效果，且不需要键合工艺，减少了生产工艺，降低了生产成本；现有的离子切割薄膜转移的衬底需要热处理或抛光才能制备电子器件，而本发明则是在原衬底表面进行功能层或半导体电子器件的制备，且具有相同的效果；现有的离子切割薄膜转移衬底在制备过程中的离子注入剂量需要达到或超过能够在衬底表面产生气泡的剂量，而本发明的离子注入剂量则只需保证不会在衬底表面产生气泡损伤即可。
在上述技术方案的基础上，本发明还可以做如下改进。
进一步，所述半导体衬底包括：半导体单晶片，或半导体单晶片以及在半导体单晶片上外延生长出的半导体外延层，或在氧化物单晶片上外延生长出的半导体外延层。
进一步，所述半导体衬底的材料为Si、Ge、SixGe1-x、SiC、GaAs、lnP、lnxGa1-xP、lnxGa1-xAs、CdTe、AN、GaN、InN或AlxlnyGa1-x-yN的任一种，其中x和y满足的条件为：0≤x≤1，0≤y≤1，0≤x+y≤1。
进一步，所述功能层包括：直接在半导体衬底上表面制备的半导体电子器件，或在半导体衬底上表面外延生长出的半导体外延层，或在半导体衬底上表面外延生长出的半导体外延层以及在半导体外延层上制备的半导体电子器件。
进一步，所述半导体外延层所含成分包括Si、Ge、SixGe1-x、SiC、GaAs、lnP、lnxGa1-xP、lnxGa1-xAs、CdTe、AN、GaN、InN和AlxlnyGa1-x-yN的至少一种，其中x和y满足的条件为：0≤x≤1，0≤y≤1，0≤x+y≤1。
进一步，所述半导体外延层包括AlxlnyGa1-x-yN时，x和y可以在外延层中渐变或突变。
进一步，所述半导体外延层的外延方法包括化学气相沉积、等离子体增强化学气相沉积、金属有机化学气相沉积、分子束外延、氢化物气相外延、 物理气相传输和液相外延。
进一步，在半导体衬底表面注入的离子包括由H、He、Ar和Ne的至少一种元素形成的离子或由该元素形成的气体产生的离子。
进一步，所述步骤2)还包括：在所述功能层上制作应力导入层，应力导入层中存在张应力,应力导入层在功能层中产生压应力。
进一步，所述应力导入层采用金属材料，所述金属材料为Ni、Au、Cu、Pd、Ag、Al、Sn、Cr、Ti、Mn、Co、Zn、Mo、W、Zr、V、Ir、Pt和Fe的至少一种。
进一步，所述应力导入层可以采用非金属高分子材料。
进一步，当所述应力导入层为金属材料时，所述应力导入层作为功能层上电子器件的欧姆接触层或肖特基接触层使用。
进一步，在所述应力导入层上制作刚性或柔性的支撑层。
进一步，在所述功能层上制作刚性或柔性的支撑层。
附图说明
图1为本发明的半导体衬底结构的主视示意图；
图2为本发明的离子经半导体衬底上表面注入半导体衬底的示意图；
图3为本发明半导体衬底经离子注入后产生离子损伤层的结构示意图；
图4为在图3的半导体衬底表面产生外延层的结构示意图；
图5为一外延层的结构示意图；
图6为在图4的外延层上制备应力导入层的结构示意图；
图7为在图6的应力导入层上制备操作层的结构示意图；
图8为在图4的外延层上直接粘接刚性衬底并产生分离的结构示意图。
附图中，各标号所代表的部件列表如下：
1、半导体衬底层；2、半导体衬底主体层；3、离子损伤层；4、衬底薄 膜层；5、半导体外延层；51、第一外延层；52、第二外延层；53、第三外延层；54、第四外延层；6、应力导入层；7、操作层；8、刚性衬底。
具体实施方式
以下结合附图对本发明的原理和特征进行描述，所举实例只用于解释本发明，并非用于限定本发明的范围。
图1和图2显示的是半导体衬底层1，图3是经离子注入后的半导体衬底层1，半导体衬底层被分成半导体衬底主体层2、离子损伤层3、以及位于离子损伤层3上的衬底薄膜层4。半导体衬底可以采用半导体单晶片、也可采用半导体单晶片以及在半导体单晶片上外延生长出半导体外延层，也可以采用在非半导体以及在氧化物单晶片上外延出半导体外延层，离子从半导体衬底层的表面注入。在半导体衬底层表面注入的离子包括由H、He、Ar和Ne的至少一种元素形成的离子或由该元素形成的气体产生的离子。
实施方式一：在半导体衬底层1上表面进行离子注入，离子注入深度为0.1μm-100μm，优选5μm、10μm、15μm和20μm；离子注入后在半导体衬底层1表面下产生一层离子损伤层3；然后可在衬底薄膜层4上直接制备功能层，本实施例的功能层为半导体电子器件，如制备MOS、MOSFET器件等。可以在半导体电子器件上直接粘接刚性衬底8，刚性衬底可以是半导体、氧化物晶体、金属、玻璃或陶瓷材料，并用向外的拉力将半导体衬底主体层和衬底薄膜层在离子损伤层处分离，此时，分离所需拉力与有应力导入层时所需的拉力相比要大的多。本实施例在分离前，功能层可以是在衬底薄膜层4上未完成制备的半导体电子器件，将半导体衬底在离子损伤层处分离后，再在衬底薄膜层4上完成剩余的半导体电子器件的制作。
实施方式二：在半导体衬底层1上表面进行离子注入，离子注入深度为0.5μm-50μm，优选5μm、10μm、15μm和20μm；离子注入后在半导体衬 底层1表面下产生一层离子损伤层3；在衬底薄膜层4的离子注入表面制备功能层，本实施例的功能层为在半导体衬底层1上表面外延生长出的半导体外延层5，也可以是在半导体衬底层1上表面外延生长出的半导体外延层5以及在半导体外延层5上制备的半导体电子器件。半导体外延层5的外延方法包括化学气相沉积(CVD)、等离子体增强化学气相沉积(PECVD)、金属有机化学气相沉积(MOCVD)、分子束外延(MBE)、氢化物气相外延(HVPE)、物理气相传输(PVT)和液相外延(LPE)。
半导体外延层5可以是单一的外延层结构，也可以是一层以上的外延结构，外延层可经由掺杂改变电导率和导电类型，如p、n型。如图5所示，半导体外延层5可以包括第一外延层51、第二外延层52、第三外延层53和第四外延层54。以制作LED外延层结构为例，第一外延层为AlN，第二外延层为n型GaN，第三外延层为多层量子阱InxGa(1-x)N与势垒GaN，第四外延层为p型GaN，其中0≤x≤1，本实施例只是给出了外延层的一种应用，外延层的结构不限于此。
如图6所示，在半导体外延层5上制作应力导入层6，应力导入层本身受到张应力。应力导入层6由蒸镀、溅射、电镀、涂覆、旋涂方法制作；应力导入层可以采用金属材料，所述金属材料为Ni、Au、Cu、Pd、Ag、Al、Sn、Cr、Ti、Mn、Co、Zn、Mo、W、Zr、V、Ir、Pt和Fe的至少一种；应力导入层的作用是在功能层中产生压应力以利于半导体衬底主体层和衬底薄膜层的剥离。应力导入层也可以采用非金属高分子材料，所述非金属高分子材料为环氧基树脂(epoxy)，环氧树脂作为应力导入层在150℃时烘干，利用功能层与应力导入层在冷却时因热澎涨系数不同产生的应力分离功能层。或环氧树脂作为应力导入层在室温干糙后，降低温度至液氮温度分离。当应力导入层为金属材料时，可作为功能层上电子器件的欧姆接触层或肖特基(Schottky)接触层使用，如在LED结构外延层的p-GaN上的应力导入层可 作为欧姆电级使用，SiC二级管n型外延层上的应力导入层可作为肖特基(Schottky)接触层使用。
如图7所示，在应力导入层6上制备操作层7，操作层7是为了分离时操作方便，可以采用胶带、聚合物等。操作层也可以采用刚性操作层，刚性操作层如半导体、氧化物、金属、玻璃或陶瓷材料。操作层非必需，当应力导入层足够厚时，不需要制作操作层。如图8所示，可以在功能层上直接粘接刚性衬底8，并用向外的拉力分离，图8中的箭头方向为拉力方向。
本实施例的半导体衬底材料采用碳化硅，以2吋(0001)晶向6H晶型碳化硅衬底为例，在碳化硅半导体衬底表面以7°倾斜角度注入氢离子，氢离子的注入能量为400keV，氢离子的注入剂量为5×1016cm-2，氢离子注入后在半导体衬底下表面生成离子损伤层，如图3所示；离子注入完成后，一个适当的温度退火过程能够强化离子在损伤层内造成的损伤效果，对不同的衬底材料，退火温度不同，对Si衬底而言，其退火温度需要在218℃以上，对SiC衬底而言，退火温度需在650℃以上；退火过程也可以发生在制作功能层的过程中，离子注入的剂量需与注入离子的能量结合应用，无离子气泡造成的表面破坏和无薄膜层的自发分离是确保本专利技术成功实施的基本条件。经离子注入后的碳化硅半导体材料衬底置于MOCVD反应器中外延生长半导体外延层(功能层)，如图5所示，半导体外延层从下至上依次包括AlN缓冲层、Si掺杂的n型GaN层，多层量子阱InxGa(1-x)N与势垒GaN、Mg掺杂的p型GaN层，整个外延层的厚度为4μm。然后在外延层上溅射一层10μm厚的Ni金属应力导入层，再在Ni金属应力导入层上化学电镀了200μm-300μm铜作为进一步支撑层兼应力导入层，从而使半导体衬底主体层2与衬底薄膜层4及其上功能层产生分离，分离后的半导体衬底主体层经抛光后可重复使用。
本实施例的半导体衬底材料采用碳化硅，以2吋(0001)晶向6H晶型 碳化硅衬底为例，在碳化硅半导体衬底表面以7°倾斜角度注入氢离子，氢离子的注入能量为500keV，氢离子的注入剂量为7×1016cm-2，氢离子注入后在半导体衬底层下表面生成离子损伤层，如图3所示。经离子注入后的碳化硅半导体材料衬底置于MOCVD反应器中外延生长半导体外延层(功能层)，如图4所示，半导体外延层从下至上依次包括AlN缓冲层、Si掺杂的n型GaN层，多层量子阱InxGa(1-x)N与势垒GaN、Mg掺杂的p型GaN层，整个半导体外延层的厚度为4μm。在半导体外延层上直接粘接硅衬底，将碳化硅衬底和硅衬底分别吸附在两个真空吸盘上，在两个真空吸盘上施加向外的机械力，功能层和半导体衬底层与半导体衬底主体层在离子损伤层处分离。
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (14)

  1. 一种将半导体衬底主体与其上功能层进行分离的方法，其特征在于，包括以下步骤：
    步骤1)：在半导体衬底上表面进行离子注入，离子注入深度为0.1μm-100μm，离子注入后在半导体衬底表面下产生一层离子损伤层；
    步骤2)：在经步骤1)处理后的半导体衬底上表面制备功能层；
    步骤3)：将半导体衬底及其上的功能层在离子损伤层处进行分离。
  2. 根据权利要求1所述一种将半导体衬底主体与其上功能层进行分离的方法，其特征在于，所述半导体衬底包括：半导体单晶片，或半导体单晶片以及在半导体单晶片上外延生长出的半导体外延层，或在氧化物单晶片上外延生长出的半导体外延层。
  3. 根据权利要求1所述一种将半导体衬底主体与其上功能层进行分离的方法，其特征在于，所述半导体衬底的材料为Si、Ge、SixGe1-x、SiC、GaAs、lnP、lnxGa1-xP、lnxGa1-xAs、CdTe、AlN、GaN、InN或AlxlnyGa1-x-yN的任一种，其中x和y满足的条件为：0≤x≤1，0≤y≤1，0≤x+y≤1。
  4. 根据权利要求1所述一种将半导体衬底主体与其上功能层进行分离的方法，其特征在于，所述功能层包括：直接在半导体衬底上表面制备的半导体电子器件，或在半导体衬底上表面外延生长出的半导体外延层，或在半导体衬底上表面外延生长出的半导体外延层以及在半导体外延层上制备的半导体电子器件。
  5. 根据权利要求4所述一种将半导体衬底主体与其上功能层进行分离的方法，其特征在于，所述半导体外延层所含成分包括Si、Ge、SixGe1-x、SiC、GaAs、lnP、lnxGa1-xP、lnxGa1-xAs、CdTe、AlN、GaN、InN和AlxlnyGa1-x-yN的至少一种，其中x和y满足的条件为：0≤x≤1，0≤y≤1，0≤x+y≤1。
  6. 根据权利要求5所述一种将半导体衬底主体与其上功能层进行分离的方法，其特征在于，所述半导体外延层包括AlxlnyGa1-x-yN时，x和y可在外延层中渐变或突变。
  7. 根据权利要求2或4所述一种将半导体衬底主体与其上功能层进行分离的方法，其特征在于，所述半导体外延层的外延方法包括化学气相沉积、等离子体增强化学气相沉积、金属有机化学气相沉积、分子束外延、氢化物气相外延、物理气相传输和液相外延。
  8. 根据权利要求1所述一种将半导体衬底主体与其上功能层进行分离的方法，其特征在于，在半导体衬底表面注入的离子包括由H、He、Ar和Ne的至少一种元素形成的离子或由该元素形成的气体产生的离子。
  9. 根据权利要求1所述一种将半导体衬底主体与其上功能层进行分离的方法，其特征在于，所述步骤2)还包括：在所述功能层上制作应力导入层，应力导入层中存在张应力,应力导入层在功能层中产生压应力。
  10. 根据权利要求9所述一种将半导体衬底主体与其上功能层进行分离的方法，其特征在于，所述应力导入层采用金属材料，所述金属材料为Ni、Au、Cu、Pd、Ag、Al、Sn、Cr、Ti、Mn、Co、Zn、Mo、W、Zr、V、Ir、Pt和Fe的至少一种。
  11. 根据权利要求9所述一种将半导体衬底主体与其上功能层进行分离的方法，其特征在于，所述应力导入层采用非金属高分子材料。
  12. 根据权利要求9或10所述一种将半导体衬底主体与其上功能层进行分离的方法，其特征在于，当所述应力导入层为金属材料时，所述应力导入层作为功能层上电子器件的欧姆接触层或肖特基接触层使用。
  13. 根据权利要求9或10所述一种将半导体衬底主体与其上功能层进行分离的方法，其特征在于，在所述应力导入层上制作刚性或柔性的支撑层。
  14. 根据权利要求1所述一种将半导体衬底主体与其上功能层进行分离 的方法，其特征在于，在所述功能层上制作刚性或柔性的支撑层。
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KR20210127791A (ko) 2021-10-22
KR20180054591A (ko) 2018-05-24
KR102313428B1 (ko) 2021-10-15
JP2020074385A (ja) 2020-05-14
EP3352207C0 (en) 2023-08-30
US20180158720A1 (en) 2018-06-07
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CN108140608B (zh) 2022-06-03
EP3352207A4 (en) 2019-04-17
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US10734274B2 (en) 2020-08-04
DE112016003716T5 (de) 2018-05-03
CN106548972B (zh) 2019-02-26
EP3352207B1 (en) 2023-08-30
CN114743926A (zh) 2022-07-12
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CN108140608A (zh) 2018-06-08

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