WO2016052261A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2016052261A1 WO2016052261A1 PCT/JP2015/076698 JP2015076698W WO2016052261A1 WO 2016052261 A1 WO2016052261 A1 WO 2016052261A1 JP 2015076698 W JP2015076698 W JP 2015076698W WO 2016052261 A1 WO2016052261 A1 WO 2016052261A1
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- H01L29/861—Diodes
- H01L29/872—Schottky diodes
Definitions
- the present invention relates to a semiconductor device.
- Patent Document 1 proposes a method of using an SBD (Schottky Barrier Diode) as a freewheeling diode in a MOSFET unit cell.
- SBD Schottky Barrier Diode
- MOSFETs have a built-in pn diode. Therefore, when the pn diode operates in a state where a forward voltage is applied to the pn diode, minority carriers are injected into the drift layer.
- the injected minority carriers recombine with the majority carriers in the drift layer, and the generated energy (recombination energy) may disturb the periodic structure of some semiconductors, resulting in crystal defects.
- the recombination energy is large because the band gap is large, and the crystal structure is easily changed because it has various stable crystal structures. Therefore, crystal defects are easily generated due to the operation of the pn diode.
- the disordered crystal structure becomes electrically high resistance, when such a phenomenon occurs particularly in the active region of the MOSFET (that is, the region having the unit cell including the channel), the on-resistance, that is, the order between the source and the drain is increased.
- the element resistance with respect to the directional current increases, and the conduction loss increases when the same current density is applied.
- the SBD diffusion potential is designed to be lower than the pn junction diffusion potential, so that a unipolar current is generated in the built-in SBD until the pn diode in the active region operates during the reflux operation. Flows. Therefore, for a certain amount of current, the reflux current can be applied without the pn diode operating, and an increase in on-resistance can be avoided.
- the present invention has been made in order to solve the above-described problems, and increases the value of the current that flows through the entire chip until the pn diode in the unit cell near the termination operates, thereby reducing the chip size and thereby
- An object of the present invention is to provide a semiconductor device capable of reducing the chip cost.
- a semiconductor device includes a first conductivity type drift layer formed on a first conductivity type semiconductor substrate, and a plurality of second conductivity types provided separately from each other on the drift layer surface layer.
- a first well region and a second well of a second conductivity type formed on the surface of the drift layer with the plurality of first well regions sandwiched in plan view and having a larger formation area than each of the first well regions.
- each of the first well regions in each of the first well regions, in each first well region surface layer formed in a depth direction from each first well region surface layer, and in each first well region surface layer, A source region of a first conductivity type formed across the first separation region in plan view, a first Schottky electrode provided on the first separation region, each first well region, and each source In contact with the area, A first ohmic electrode provided on the first well region and each of the source regions; a second conductive region of a first conductivity type that separates the first well regions; and the second A second ohmic electrode provided on the well region and penetrating in a depth direction from the surface layer of the second well region at a position closer to the first well region than the second ohmic electrode in the second well region; A formed first separation region of the first conductivity type, a second Schottky electrode provided on the third separation region, the first and second Schottky electrodes, and the first and second ohmic electrodes A gate electrode provided on a part of the first and
- a semiconductor device includes a first conductivity type drift layer formed on a first conductivity type semiconductor substrate and a plurality of semiconductor devices provided apart from each other on the drift layer surface layer.
- the first well region of two conductivity type and the drift layer surface layer formed by sandwiching a part of the plurality of first well regions in plan view and having a larger formation area than each of the first well regions
- the second well region having two conductivity types and at least one of the plurality of first well regions, and the first well region is sandwiched between the second well regions in plan view.
- a first region of a first conductivity type formed penetrating in a depth direction from each surface layer of the first well region in at least the first well region in the sense region and separated from the well region;
- a first conductivity type source region formed across the first separation region in plan view, and at least on each first well region surface layer in the sense region, and on the first separation region.
- the first Schottky electrode, the first ohmic electrode provided on at least each of the first well region and the source region in the sense region, and the first well region are separated from each other.
- a second ohmic electrode provided on the second well region, a second separated region of the first conductivity type, and the second ohmic electrode
- a gate electrode provided on a part of the first and second well regions excluding a position where the first and second ohmic electrodes and the first and second ohmic electrodes are provided via a first insulating film And a second insulating film formed to cover the gate electrode, the first Schottky electrode, and a sense electrode provided to cover the first ohmic electrode.
- the third separation region of the first conductivity type formed penetrating in the depth direction from the surface layer of the second well region, and the second Schottky electrode provided on the third separation region In the reflux state, a voltage drop occurs in the drift layer around the second Schottky electrode, and the voltage applied to the pn diode in the first well region located in the active region is relaxed. Therefore, the operation of the pn diode can be suppressed, and more current can be circulated in the SBD. As a result, the return current that can flow through the entire chip with a unipolar current increases, and the chip size can be reduced.
- 1 is a schematic plan view of a semiconductor device according to an embodiment.
- 1 is a schematic plan view of a semiconductor device according to an embodiment.
- 1 is a schematic plan view of a semiconductor device according to an embodiment.
- 1 is a schematic plan view of a semiconductor device according to an embodiment.
- 1 is a schematic plan view of a semiconductor device according to an embodiment.
- 1 is a schematic plan view of a semiconductor device according to an embodiment.
- 1 is a schematic plan view of a semiconductor device according to an embodiment.
- 1 is a schematic plan view schematically showing an entire semiconductor device incorporating a current sense according to an embodiment.
- 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment. It is a cross-sectional schematic diagram when not using this invention.
- 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment. It is a cross-sectional schematic diagram of the unit cell of the SBD built-in MOSFET according to the embodiment.
- a silicon carbide (SiC) semiconductor device is used as an example of the semiconductor device, and in particular, an n-channel silicon carbide MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type is taken as an example. I will explain.
- FIG. 1 is a schematic cross-sectional view of a unit cell of an SBD built-in MOSFET disposed in an active region.
- FIG. 2 is a view of the unit cell of the SBD built-in MOSFET as viewed from above, and represents only a region (semiconductor region) where the electrode or the insulating film of FIG. 1 is transmitted and the semiconductor layer is formed.
- an n-type (first conductivity type) is formed on a first main surface of a substrate 10 having a polytype of 4H and made of n-type (first conductivity type) and low resistance silicon carbide.
- a drift layer 20 made of silicon carbide of one conductivity type is formed.
- the substrate 10 made of silicon carbide has a (0001) plane of the first principal surface and is inclined 4 ° with respect to the c-axis direction.
- the drift layer 20 is an n-type (first conductivity type) semiconductor layer having a first impurity concentration.
- a plurality of p-type (second conductivity type) well regions 30 containing aluminum (Al), which is a p-type (second conductivity type) impurity, are separated from each other on the surface layer of the drift layer 20.
- the p-type (second conductivity type) impurity concentration of the well region 30 is set to the second impurity concentration.
- the well regions 30 shown in FIG. 1 are formed at two positions apart from each other in a sectional view in the unit cell.
- a region that separates the well regions 30 is an n-type (first conductivity type) region called a second separation region 21.
- the second separation region 21 is a region formed in the surface layer portion of the drift layer 20, and is a region extending from the surface of the drift layer 20 to the same depth as the well region 30 in the depth direction.
- a first conductivity type first separation region 22 formed through the surface of each well region 30 in the depth direction is formed.
- the first separation region 22 is a region located immediately below a Schottky electrode 75 described later.
- n-type (first conductivity type) source region 40 containing nitrogen (N), which is an n-type (first conductivity type) impurity, is partially formed on the surface layer side of the well region 30.
- the source region 40 is formed shallower than the depth of the well region 30.
- the source region 40 is formed with the first separation region 22 sandwiched in plan view.
- Al which is a p-type (second conductivity type) impurity is preferably formed on the well region 30 sandwiched between the source region 40 and the first separation region 22.
- Al aluminum
- a p-type (second conductivity type) first well contact region 35 containing is formed.
- a gate insulating film 50 made of silicon oxide is formed across the surface of the second separation region 21, the surface of the well region 30, and a part of the surface of the source region 40.
- a gate electrode 60 is formed on the surface of the gate insulating film 50 so as to correspond to the second separation region 21, the well region 30, and the end portions of the source region 40.
- a region of the well region 30 that is sandwiched between the second separation region 21 and the source region 40 and corresponds to the gate electrode 60 through the gate insulating film 50 and in which an inversion layer is formed during the ON operation is referred to as a channel region.
- An interlayer insulating film 55 made of silicon oxide is formed on the gate insulating film 50 so as to cover the gate electrode 60.
- the surface of the source region 40 that is not covered with the gate insulating film 50 and the partial surface of the first well contact region 35 that is in contact with the source region 40 have contact resistance with silicon carbide.
- a source-side ohmic electrode 70 for reduction is formed.
- the well region 30 can easily exchange electrons with the source-side ohmic electrode 70 via the low-resistance first well contact region 35.
- a Schottky electrode 75 is formed on the surface of the first separation region 22, and the Schottky electrode 75 and the silicon carbide in the first separation region 22 are Schottky connected.
- the Schottky electrode 75 desirably includes at least the surface of the first separation region 22, but may not include it.
- the Schottky electrode 75 may be provided on the well region 30 at a position sandwiched between the ohmic electrodes 70 in plan view. Further, the Schottky electrode 75 may be provided so as to further extend onto the interlayer insulating film 55 as illustrated in FIG.
- a source electrode 80 is formed on the source-side ohmic electrode 70, the Schottky electrode 75, and the interlayer insulating film 55.
- the source electrode 80 electrically short-circuits the source-side ohmic electrode 70 and the Schottky electrode 75. That is, the source-side ohmic electrode 70 and the Schottky electrode 75 are electrically connected.
- a drain electrode 85 is formed on the second main surface opposite to the first main surface of the substrate 10, that is, on the back surface side via a back surface ohmic electrode 71.
- the gate electrode 60 is electrically short-circuited with the gate pad and the gate wiring through the gate contact hole opened in the interlayer insulating film 55 in a part of the region where the unit cell does not exist in the semiconductor device. ing.
- the second separation region 21 is a path through which an on-current flows when the MOSFET is turned on
- the first separation region 22 is a path through which a unipolar current, which is a SBD return current, flows.
- the shape of the unit cell may be not only a mesh shape as shown in FIG. 2, but also various shapes such as a stripe shape as shown in FIG.
- FIG. 3 is a top view of the unit cell of the SBD built-in MOSFET.
- FIG. 4 is a view of the semiconductor device as viewed from above, that is, from the first main surface side, and the planar position of the active region is represented by a broken line.
- the source electrode 80 is formed so as to encompass the planar position of the active region.
- a gate electrode 82 that is electrically insulated from the source electrode 80 is formed on the first main surface.
- a region other than the active region in which unit cells are periodically arranged in the entire semiconductor device will be referred to as an invalid region in the present application.
- FIG. 5A is a diagram for explaining the structure of a portion adjacent to the gate electrode 82 in the terminal portion of the active region, and is a schematic cross-sectional view corresponding to the position aa ′ in FIG.
- FIG. 5B is a schematic plan view of the portion of FIG. 5A, where only the semiconductor region is expressed through the electrode and the insulating film.
- FIG. 5C is a schematic cross-sectional view when the present invention is not used at the same place.
- FIG. 6A is a diagram for explaining the structure of a portion adjacent to the end portion of the chip where the gate electrode 82 does not exist in the end portion of the active region, and is located at the position bb ′ in FIG. It is a corresponding cross-sectional schematic diagram.
- FIG. 6B is a schematic plan view of the portion of FIG. 6A, where only the semiconductor region is expressed through the electrode or the insulating film.
- FIG. 6C is a schematic cross-sectional view when the present invention is not used at the same place.
- the gate electrode 82 is formed on the interlayer insulating film 55 and is electrically connected to the gate electrode 60 through the gate contact hole 95 opened in a part of the interlayer insulating film 55.
- a wide-area well region 31 having a larger area than the well region 30 is formed from the well region 30 of the outermost unit cell with an n-type region having the same width as the second separation region 21 interposed therebetween. Yes.
- the planar position of the wide well region 31 includes the planar position of the gate electrode 82.
- the wide well region 31 is connected to the source electrode 80 through a well contact hole 91 opened in a part of the interlayer insulating film 55 adjacent to the well region 30 at a position near the active region.
- a first well contact region 35 and an ohmic electrode 70 (second ohmic electrode) are formed in the surface layer portion of the wide well region 31 that contacts the well contact hole 91.
- a part of the position farther from the active region than the planar position where the well contact hole 91 and the SBD contact hole 92 at a position farther from the well region 30 than the well contact hole 91 are formed is located above the drift layer 20 and A field insulating film 52 thicker than the gate insulating film 50 is formed below the gate electrode 60.
- a wide well region 31 having a larger area than the well region 30 is sandwiched from the well region 30 of the outermost unit cell with an n-type region having the same width as the second separation region 21. Is formed.
- a p-type JTE (junction termination extension) region 37 having an impurity concentration lower than that of the wide well region 31 is formed on the outer periphery side of the wide well region 31 and connected to the wide well region 31.
- the wide well region 31 is connected to the source electrode 80 through a well contact hole 91 opened in a part of the interlayer insulating film 55 adjacent to the well region 30.
- a first well contact region 35 and an ohmic electrode 70 are formed in the surface layer portion of the wide well region 31 that contacts the well contact hole 91.
- the third separation region 23 is a region that is surrounded by the wide-area well region 31 and is an n-type region due to the lack of the p-type implantation that forms the wide-area well region 31. That is, the third separation region 23 is formed in the wide well region 31 so as to penetrate from the surface layer of the wide well region 31 in the depth direction. As a result, an SBD surrounded by the wide well region 31 is formed in the invalid region.
- the diffusion potential of both the SBD formed in the active region and the SBD formed in the ineffective region is lower than the diffusion potential of the pn junction formed in silicon carbide.
- chemical vapor deposition (Chemical Vapor Deposition) is performed on the surface of a substrate 10 made of n-type low-resistance silicon carbide having a (0001) plane and a 4H polytype.
- the drift layer 20 made of silicon carbide having a thickness of 5 ⁇ m to 200 ⁇ m is epitaxially grown at an n-type impurity concentration of 1 ⁇ 10 14 cm ⁇ 3 to 1 ⁇ 10 17 cm ⁇ 3 by the CVD method.
- an implantation mask is formed on the surface of the drift layer 20 using a photoresist or the like, and Al, which is a p-type impurity, is ion-implanted.
- the depth of Al ion implantation is set to about 0.5 ⁇ m to 3 ⁇ m which does not exceed the thickness of the drift layer 20.
- the impurity concentration of ion-implanted Al is in the range of 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 and is higher than the first impurity concentration of the drift layer 20.
- the implantation mask is removed.
- the region into which Al is ion-implanted by this step becomes the well region 30 and the wide well region 31.
- an implantation mask is formed on the surface of the drift layer 20 using a photoresist or the like, and Al, which is a p-type impurity, is ion-implanted.
- the depth of Al ion implantation is set to about 0.5 ⁇ m to 3 ⁇ m which does not exceed the thickness of the drift layer 20.
- the impurity concentration of the ion-implanted Al is in the range of 1 ⁇ 10 16 cm ⁇ 3 to 1 ⁇ 10 18 cm ⁇ 3 , which is higher than the first impurity concentration of the drift layer 20 and the Al concentration of the well region 30. Lower than.
- the implantation mask is removed. A region into which Al is ion-implanted by this step becomes the JTE region 37.
- an implantation mask is formed on the surface of the drift layer 20 with a photoresist or the like, and N which is an n-type impurity is ion-implanted.
- the N ion implantation depth is shallower than the thickness of the well region 30.
- the impurity concentration of the ion-implanted N is in the range of 1 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 21 cm ⁇ 3 and exceeds the p-type second impurity concentration of the well region 30.
- the n-type region is the source region 40.
- an implantation mask is formed on the surface of the drift layer 20 with a photoresist or the like, and Al, which is a p-type impurity, is ion-implanted to remove the implantation mask.
- the region into which Al is implanted by this step becomes the first well contact region 35.
- the first well contact region 35 is provided in order to obtain good electrical contact between the well region 30 and the source-side ohmic electrode 70.
- the p-type impurity concentration of the first well contact region 35 is set to It is desirable that the concentration be higher than the p-type second impurity concentration.
- annealing is performed for 30 seconds to 1 hour in an inert gas atmosphere (1300 ° C. to 1900 ° C.) such as argon (Ar) gas by a heat treatment apparatus.
- an inert gas atmosphere (1300 ° C. to 1900 ° C.) such as argon (Ar) gas
- argon (Ar) gas By this annealing, ion-implanted N and Al are electrically activated.
- a field insulating film 52 made of a silicon dioxide film having a thickness of about 0.5 ⁇ m to 2 ⁇ m is formed in a region other than the position substantially corresponding to the above-described active region by using a CVD method, a photolithography technique, or the like.
- the field insulating film 52 at a position substantially corresponding to the cell region may be removed by photolithography or etching.
- the surface of the silicon carbide not covered with the field insulating film 52 is thermally oxidized to form silicon oxide as the gate insulating film 50 having a desired thickness.
- a polycrystalline silicon film having conductivity is formed on the gate insulating film 50 by a low pressure CVD method, and the gate electrode 60 is formed by patterning this.
- an interlayer insulating film 55 is formed by a low pressure CVD method.
- a contact hole that penetrates the interlayer insulating film 55 and the gate insulating film 50 and reaches the first well contact region 35 and the source region 40 of the unit cell is formed, and a well contact hole 91 is simultaneously formed.
- a heat treatment at a temperature of 600 ° C. to 1100 ° C. is performed to form a metal film containing Ni as a main component and a silicon carbide layer in the contact hole.
- silicide is formed between the silicon carbide layer and the metal film.
- the metal film remaining on the interlayer insulating film 55 other than the silicide formed by the reaction is removed by wet etching using sulfuric acid, nitric acid, hydrochloric acid, or a mixed solution of hydrogen peroxide and the like. As a result, the source-side ohmic electrode 70 is formed.
- a back surface ohmic electrode 71 is formed on the back side of the substrate 10 by forming a metal mainly composed of Ni on the back surface (second main surface) of the substrate 10 and performing heat treatment.
- the interlayer insulating film 55 on the first separation region 22, the gate insulating film 50 and the interlayer insulating film 55 at the position to be the SBD contact hole 92, and the gate contact hole 95 are formed by patterning using a photoresist or the like.
- the gate insulating film 50 and the interlayer insulating film 55 at the position are removed.
- wet etching that does not damage the silicon carbide surface that becomes the SBD interface is preferable.
- a Schottky electrode 75 is deposited by sputtering or the like.
- the Schottky electrode 75 it is preferable to deposit Ti, Mo, Ni or the like.
- a wiring metal such as Al is formed on the surface of the substrate 10 processed so far by sputtering or vapor deposition, and processed into a predetermined shape by photolithography, so that the ohmic electrode 70 and the Schottky electrode on the source side are formed.
- a source electrode 80 in contact with the gate electrode 75 and a gate electrode 82 in contact with the gate electrode 60 are formed.
- a drain electrode 85 which is a metal film, is formed on the surface of the back ohmic electrode 71 formed on the back surface of the substrate 10, the semiconductor device shown in FIGS. 1 to 6 is completed.
- the first state is a case where a high voltage is applied to the drain electrode 85 with respect to the source electrode 80 and a positive voltage equal to or higher than the threshold value is applied to the gate electrode 82. Call.
- Electrons flowing from the source electrode 80 to the drain electrode 85 are transferred from the source electrode 80 to the ohmic electrode 70, the source region 40, the channel region, and the second separation region 21 in accordance with an electric field formed by a positive voltage applied to the drain electrode 85.
- the drain layer 85 reaches the drain electrode 85 via the substrate 10.
- an on-current flows from the drain electrode 85 to the source electrode 80 by applying a positive voltage to the gate electrode 60.
- a voltage applied between the source electrode 80 and the drain electrode 85 is referred to as an on voltage
- a value obtained by dividing the on voltage by the density of the on current is referred to as an on resistance.
- the on-resistance is equal to the total resistance of the path through which the electrons flow. Since the product of the square of the on-resistance and the on-current is equal to the energization loss that the MOSFET consumes when energized, it is preferable that the on-resistance is low.
- the on-current flows only in the active region where the channel exists, and does not flow in the ineffective region.
- the second state is a case where a high voltage is applied to the drain electrode 85 with respect to the source electrode 80 and a voltage equal to or lower than the threshold value is applied to the gate electrode 60, and is hereinafter referred to as an “off state”.
- a reverse bias is applied to the pn junction formed between the well region 30 and the drift layer 20, and a thick depletion layer spreads toward the drift layer 20 having a relatively low concentration. It is possible to prevent the insulating film 50 from being applied.
- the gate insulating film 50 on the second separation region 21 does not have a p-type region immediately below, a relatively high electric field strength is applied as compared with the gate insulating film 50 on the well region 30.
- the electric field applied to the gate insulating film 50 is suppressed to a desired value or less by the depletion layer extending in the lateral direction from the well region 30 toward the second separation region 21. can do.
- a thin depletion layer spreads not only in the drift layer 20 and the second separation region 21 but also in the p-type well region 30 having a relatively high concentration. Holes generated from the depletion layer to be formed are discharged to the source electrode 80 through the first well contact region 35. That is, by forming an electrical contact between the well region 30 and the source electrode 80, it is possible to prevent a high electric field strength from being applied to the gate insulating film 50 on the well region 30 in the off state.
- the wide well formed in the region substantially including the planar positions of the gate insulating film 50 and the field insulating film 52 formed on the invalid region.
- a region 31 and a well contact hole 91 for forming an electrical contact between the wide well region 31 and the source electrode 80 are formed in part of the region 31. Therefore, similarly, it is possible to prevent a high electric field strength from being applied to the gate insulating film 50 and the field insulating film 52 on the invalid region.
- the leak current is large, the heat generation of the MOSFET increases and the MOSFET and the module using the MOSFET may be thermally destroyed. For this reason, it is preferable to keep the electric field applied to the Schottky junction low in order to reduce the leakage current.
- a low voltage is applied to the drain electrode 85 with respect to the source electrode 80, that is, a back electromotive voltage is applied to the MOSFET, and a reflux current flows from the source electrode 80 to the drain electrode 85.
- this state is referred to as a “reflux state”.
- a forward electric field (forward bias) is applied to the built-in SBD, and a unipolar current consisting of an electron current flows from the Schottky electrode 75 toward the silicon carbide layer.
- forward bias a forward electric field
- a unipolar current consisting of an electron current flows from the Schottky electrode 75 toward the silicon carbide layer.
- the inventors have found that the conditions under which the pn diode operates in the active region are affected by the surroundings of the unit cell, and based on a consideration that takes this into consideration, a method for making the operation of the pn diode in the active region difficult to occur. I found it.
- an SBD built-in MOSFET having only such a periodic arrangement of unit cells is referred to as an ideal SBD built-in MOSFET.
- FIG. 7 shows the result of calculating the current characteristics and the voltage characteristics in the reflux state by device simulation for the unit cell of the MOSFET with built-in SBD and the unit cell of the MOSFET with no built-in SBD.
- the vertical axis represents the current (A / cm 2 ) flowing through the drain electrode, and the horizontal axis represents the source-drain voltage (V).
- the triangle mark indicates the characteristics of the SBD built-in MOSFET, and the circle mark indicates the characteristics of the MOSFET not including the SBD.
- FIG. 8 also shows the characteristics of a MOSFET that does not incorporate an SBD, whose sectional view is shown.
- the source-drain voltage at which the pn diode operates is higher than that in the MOSFET not incorporating the SBD. This can be explained as follows. Prior to the description, it is stated that the voltage applied to the pn junction is the potential difference between the well region 30 and the contact surface of the drift layer 20 with respect to the well region 30.
- the SBD built-in MOSFET when the source-drain voltage is higher than the SBD operating voltage and lower than the pn diode operating voltage, a unipolar current passing through the SBD flows between the source and drain. A voltage drop corresponding to the product of the resistivity and current density occurs. That is, a voltage drop also occurs in the drift layer 20 and the substrate 10. The potential of the contact surface of the drift layer 20 with respect to the well region 30 is smaller than the source / drain voltage by a voltage equal to the voltage drop. Thanks to this effect, the SBD built-in MOSFET has a high source-drain voltage at which the pn diode operates, and can pass a larger amount of unipolar current as a return current until the pn diode operates.
- the vicinity of the end of the active region is considered.
- the wide well region 31 is adjacent to the unit cell at the end of the active region.
- the wide well region 31 cannot pass a unipolar current, so that almost all of the source-drain voltage is wide.
- the voltage is applied to a pn diode composed of a junction between the well region 31 and the drift layer 20.
- the problem here is that the pn diode in the unit cell near the end of the active region exceeds the operating voltage of the pn diode with a smaller source-drain voltage than the ideal pn diode of the SBD built-in MOSFET unit cell. This is a case where minority carrier injection occurs from the region 30 toward the drift layer 20. At this time, the holes diffused in the drift layer 20 cause recombination with electrons at that location, thereby generating crystal defects in the drift layer in the active region and increasing the on-resistance.
- the unipolar current due to SBD diffuses to the drift layer 20 immediately below the wide-area well region 31, and the voltage drop in the drift layer 20 immediately below the well region 30 of the outermost unit cell is ideal for the built-in SBD.
- This is smaller than the voltage drop in the drift layer 20 of the MOSFET.
- the voltage applied to the pn diode increases, and the bipolar operation starts from a source-drain voltage lower than that of an ideal SBD built-in MOSFET.
- the diffusion of the unipolar current by the SBD to the drift layer 20 immediately below the wide well region 31 is close to not only the outermost peripheral cell in the active region but also the outermost peripheral cell, particularly when the thickness of the drift layer 20 is large. It can also happen in cells. As a result, the source-drain voltage at which each unit cell starts bipolar operation is the lowest in the outermost peripheral cell, and approaches the characteristics of an ideal SBD built-in MOSFET as it goes toward the inner cell.
- the drift layer 20 may diffuse into the drift layer 20 immediately below the well region 30 in the adjacent active region.
- the resistivity of the drift layer 20 decreases.
- the resistivity of the drift layer 20 decreases, the voltage drop generated in the drift layer 20 decreases, and the voltage applied to the pn junction increases.
- the voltage applied to the pn diode increases, and the bipolar operation starts from a lower source-drain voltage. Furthermore, when bipolar operation starts in the outermost unit cell, minority carrier diffusion also occurs in the inner unit cell. Thus, the bipolar operation of the pn diode occurring in the wide well region 31 causes the bipolar operation of each unit cell from the adjacent unit cell toward the inside of the active region. Since this effect is gradually attenuated as it propagates to the inner unit cell, the voltage between the source and drain at which each unit cell starts bipolar operation is the lowest in the outermost cell, and the unit cell described above becomes closer to the inner cell. It approaches the characteristics when the periodic array of cells continues indefinitely.
- a bipolar operation occurs in a part of the unit cells near the outermost peripheral cell of the active region. This may cause crystal defects and increase the on-resistance of the entire chip.
- the range in which the bipolar operation occurs is higher as the driving source / drain voltage is higher and the reflux current flowing through the entire chip is larger. It is necessary to make the size of a certain value or less. However, doing so increases the chip area and increases the chip cost.
- the unipolar current due to the SBD is sufficiently secured immediately below the well region 30 of the outermost peripheral cell, and the voltage drop of the drift layer 20 is increased, so that the drift region 20 of the well region 30 and the well region 30 It is considered effective to reduce the potential difference with the contact surface.
- a part of the wide well region 31 is located in the vicinity of the well contact hole 91.
- the SBD is formed in a form lacking.
- a current flows from the SBD disposed in the vicinity of the SBD contact hole 92 toward the silicon carbide layer. Since this current is diffused in the lateral direction in the drift layer 20, the drift layer 20 not only immediately below the SBD contact hole 92 but also immediately below the well region 30 in the active region, the substrate 10, and the drift layer 20 in the vicinity of the adjacent well contact hole 91. And also in the substrate 10, a voltage drop is caused.
- the bipolar operation of the peripheral unit cell can be suppressed to a higher source-drain voltage.
- FIG. 9 shows a part of the wide well region 31 at a position closer to the unit cell region than the ten well cells of the SBD built-in MOSFET, the wide well region 31, and the first well contact region 35 in the wide well region 31.
- 5 is a result of calculation of current characteristics and voltage characteristics in a reflux state by device simulation in an SBD built-in MOSFET including an SBD formed by lacking.
- the vertical axis represents the current (A) flowing through the drain electrode, and the horizontal axis represents the source-drain voltage (V).
- the distance between the end of the outermost unit cell and the SBD formed by losing a part of the wide-area well region 31 is 5 ⁇ m, the end of the outermost unit cell and the first well of the wide-area well region 31.
- the distance from the contact region 35 is 20 ⁇ m.
- the thick broken line in the graph is the result of calculating the current characteristics and the voltage characteristics in the reflux state only for the unit cell of the SBD built-in MOSFET by device simulation, and the current flows when the source-drain voltage is about 1V.
- the one that starts shows the SBD in the cell region, and the one that starts to flow when the source-drain voltage is about 8 V shows the pn diode in the cell region.
- the current flowing through the SBDs of 10 cells having different positions around the current flowing through the SBD in the case of only the unit cell, and the position of 10 around the current flowing through the pn diode in the case of only the unit cell are different.
- the currents flowing through the pn diodes of the cells are collectively shown.
- FIG. 10 shows the result of the same calculation performed in the SBD built-in MOSFET that does not include the SBD formed by missing a part of the wide well region 31.
- the thick broken line in the graph is the result of calculating the current characteristic and the voltage characteristic in the reflux state for only the unit cell of the SBD built-in MOSFET by device simulation.
- the current flows when the source-drain voltage is about 1V.
- the one that starts shows the SBD in the cell region, and the one that starts to flow when the source-drain voltage is about 8 V shows the pn diode in the cell region.
- the current flowing through the SBDs of 10 cells having different positions around the current flowing through the SBD in the case of only the unit cell, and the position of 10 around the current flowing through the pn diode in the case of only the unit cell are different.
- the currents flowing through the pn diodes of the cells are collectively shown.
- the rise voltage of the outermost pn diode is reduced to about 6 V compared to the case where only the unit cell is calculated (the thick broken line in which the current starts to flow at about 8 V).
- the rising voltage of the outermost peripheral pn diode remains high at about 8V.
- FIG. 11A shows that there are 10 SBD built-in MOSFET unit cells, the wide well region 31, and the wide well region at a position closer to the unit cell region than the first well contact region 35 in the wide well region 31.
- SBD built-in MOSFET including the SBD formed by deleting a part of 31 an equipotential line is shown when a voltage of 6 V is applied between the source and drain.
- FIG. 11B shows equipotential lines when a voltage of 6 V is applied between the source and drain in an SBD built-in MOSFET that does not have an SBD formed by losing a part of the wide well region 31. ing.
- FIG. 11 (a) current spreads from the SBD formed by missing a part of the wide-area well region 31 to the drift layer 20 including the lower portion of the well region 30 of the outermost unit cell.
- a voltage drop occurs in the lower portion of the well region 30 of the unit cell, and the voltage applied to the pn junction of the well region 30 of the unit cell is smaller than in the case of FIG. 11B.
- FIG. 12 shows that ten SBD built-in MOSFET unit cells, the wide well region 31, and the wide well region 31 are located closer to the unit cell region than the first well contact region 35 in the wide well region 31.
- the distance between the end of the outermost unit cell and the SBD formed by partially missing the wide well region 31 is 1.5 ⁇ m to It is the result of having calculated by the device simulation the current characteristic and voltage characteristic in a recirculation
- the rhombus marks indicate the case where the distance between the end of the outermost unit cell and the SBD formed by missing a part of the wide-area well region 31 is 1.5 ⁇ m, and the square marks are The distance is 2 ⁇ m, the triangle indicates the distance is 3 ⁇ m, the circle indicates the distance is 4 ⁇ m, and the cross indicates the distance is 5 ⁇ m. Show.
- the broken line in the graph is the result of calculating the current characteristic and voltage characteristic in the reflux state by device simulation only for the unit cell of the SBD built-in MOSFET.
- the distance to the Schottky electrode 75 is 3 ⁇ m or less, the rising voltage of the pn diode in the well region 30 of the outermost unit cell is calculated for only the unit cell. Is bigger than. That is, in all the unit cells in the active region, the rise in the rising voltage of the pn diode in the well region 30 can be suppressed.
- the outermost periphery is preferably set to 3 ⁇ m or less.
- the rise of the rising voltage of the pn diode in the well region 30 of the unit cell can be suppressed. Further, as described above, by suppressing the pn diode operation in the well region 30 of the outermost peripheral cell, it is possible to suppress a decrease in the operating voltage of the pn diode in the well regions 30 of all the unit cells in the active region. .
- the semiconductor device includes a first conductivity type drift layer 20, a well region 30 as a second conductivity type first well region, and a wide well as a second conductivity type second well region.
- a region 31 a first conductivity type first separation region 22, a first conductivity type source region 40, a Schottky electrode 75 as a first Schottky electrode provided on the first separation region 22,
- An ohmic electrode 70 as a first ohmic electrode provided on each well region 30 and each source region 40 while being in contact with the well region 30 and each source region 40, and a second conductive region of the first conductivity type 21, an ohmic electrode 70 as a second ohmic electrode provided on the wide well region 31, a first conductivity type third separation region 23, and a second Schottky electrode provided on the third separation region 23 age
- the drift layer 20 is formed on a substrate 10 as a first conductivity type semiconductor substrate.
- a plurality of well regions 30 are provided apart from each other in the surface layer of the drift layer 20.
- the wide-area well region 31 is formed by sandwiching the entire plurality of well regions 30 in the surface layer of the drift layer 20 in plan view.
- the wide well region 31 has a larger formation area than each well region 30.
- the first separation region 22 is formed in each well region 30 so as to penetrate from the surface layer of each well region 30 in the depth direction.
- the source region 40 is formed on the surface layer of each well region 30 with the first separated region 22 in plan view.
- the second separation region 21 is a region that separates the well regions 30 from each other.
- the third separation region 23 is formed penetrating in the depth direction from the surface layer of the wide well region 31 at a position closer to the well region 30 than the ohmic electrode 70 as the second ohmic electrode in the wide well region 31.
- the gate electrode 60 is provided on a part of the well region 30 and the wide well region 31 except for the position where the Schottky electrode 75 and the ohmic electrode 70 are provided via a gate insulating film 50 as a first insulating film. It is done.
- the interlayer insulating film 55 is formed so as to cover the gate electrode 60.
- the source electrode 80 is provided so as to cover the Schottky electrode 75, the ohmic electrode 70, and the interlayer insulating film 55.
- a part of the wide-area well region 31 is located at a position closer to the unit cell region than the first well contact region 35 in the wide-area well region 31.
- the SBD formed in a deficiency is provided.
- the distance between the Schottky electrode 75 as the second Schottky electrode and the well region 30 is 3 ⁇ m or less.
- the current flowing from the SBD provided in the wide well region 31 to the drift layer 20 directly below the outermost peripheral cell can be increased, and the voltage drop can be further increased. Therefore, the pn diode operation of the outermost peripheral cell is suppressed.
- FIG. 13 is a schematic plan view corresponding to the position aa ′ in FIG. 4 for explaining the structure of the end portion of the active region adjacent to the gate electrode 82, which is transmitted through the electrode or the insulating film. Only the semiconductor region is represented.
- FIG. 14 is a schematic plan view corresponding to the position bb ′ of FIG. 4 for explaining the structure of the end portion of the active region where the gate electrode 82 does not exist and is adjacent to the end portion of the chip. Only the semiconductor region is expressed through the electrode or the insulating film.
- a part of the wide well region 31b is surrounded by the active region between the well region 30 of the outermost unit cell and the first well contact region 35 in the wide well region 31b.
- the third separation region 23b exists due to the defect.
- a Schottky electrode 75 is formed on the surface of the third separation region 23b so that a unipolar current can flow during the reflux operation.
- the SBD region in the wide well region 31b is continuously formed so as to surround the active region, that is, in a direction intersecting the direction approaching the well region 30 from the wide well region 31b in plan view.
- a unipolar current can flow uniformly from the SBD in the wide well region 31b to the drift layer 20 below the well region 30 of the unit cell. For this reason, there is no dispersion
- the third well region 31c is formed so as to be missing so as to surround the active region.
- the separation regions 23c may be formed in a plurality of discrete manners (details will be described in the third embodiment).
- the third separation region 23b is continuously formed in a direction crossing the direction approaching the well region 30 as the first well region in plan view.
- a unipolar current can flow uniformly from the SBD in the wide well region 31b to the drift layer 20 below the well region 30 of the unit cell. Therefore, there is no variation due to the planar position, and a decrease in the operating voltage of the pn diode in the well region 30 of the unit cell in the active region (particularly, the pn diode of the unit cell in the outermost periphery of the active region) can be suppressed. As a result, a larger amount of current can be circulated in the SBD, and the return current that can flow through the entire chip as a unipolar current increases, thereby reducing the chip size and thereby reducing the chip cost.
- FIG. 15 is a schematic plan view corresponding to the position aa ′ in FIG. 4 for explaining the structure of the end portion of the active region adjacent to the gate electrode 82, and is transmitted through the electrode or the insulating film. Only the semiconductor region is represented.
- FIG. 16 is a schematic plan view corresponding to the position of bb ′ in FIG. 4 for explaining the structure of the end portion of the active region where the gate electrode 82 does not exist and is adjacent to the end portion of the chip. Only the semiconductor region is expressed through the electrode or the insulating film.
- the periphery of the first well contact region 35 in the wide well region 31c including the space between the well region 30 of the outermost unit cell and the first well contact region 35 in the wide well region 31c.
- a part of the wide well region 31c is missing, and there is a third separation region 23c that does not completely surround the first well contact region 35.
- a Schottky electrode 75 is formed on the surface of the third separation region 23c so that a unipolar current can flow during the reflux operation.
- the displacement current is applied to the electrode even when a high dV / dt is applied such as during a switching operation. And leave a flowing path.
- the third separation region 23c is divided into a plurality of pieces as shown in FIG. It may be connected.
- the third separation region 23c surrounds the ohmic electrode 70 as the second ohmic electrode in a plan view, and at least part of the ohmic electrode 70 surrounding the ohmic electrode 70 is missing.
- the displacement current is applied to the electrode even when a high dV / dt is applied such as during a switching operation. And leave a flowing path.
- FIG. 18A is a diagram for explaining the structure of a portion adjacent to the gate electrode 82 in the terminal portion of the active region, and is a schematic cross-sectional view corresponding to the position aa ′ in FIG. Further, FIG. 18B is a schematic plan view of the portion of FIG. 18A, where only the semiconductor region is expressed through the electrode and the insulating film.
- FIG. 19A is a diagram for explaining the structure of a portion adjacent to the end portion of the chip where the gate electrode 82 does not exist in the end portion of the active region, and is located at the position bb ′ in FIG. It is a corresponding cross-sectional schematic diagram. Further, FIG. 19B is a schematic plan view of the portion of FIG. 19A, and only the semiconductor region is expressed through the electrode and the insulating film.
- a part of the wide well region 31f is lost between the well region 30 of the outermost unit cell and the first well contact region 35f in the wide well region 31f, and the third separated region is removed.
- 23 exists.
- a Schottky electrode 75 is formed on the surface of the third separation region 23 so that a unipolar current can flow during the reflux operation.
- a fourth separation region 24 is formed inside the first well contact region 35f in the wide well region 31f, and further, a Schottky electrode 75 in contact with at least a part of the surface of the fourth separation region 24, and the first well
- An ohmic electrode 70 that contacts at least a part of the surface of the contact region 35f is formed.
- the manufacturing method is almost the same as that of the first embodiment.
- the implantation position of the wide well region 31f and the first well contact region 35f is changed, and the ohmic electrode 70 and the Schottky electrode 75 are arranged at desired locations. Just change the layout.
- the semiconductor device includes the fourth separation region 24 and the Schottky electrode 75 as the third Schottky electrode.
- the fourth separation region 24 is a region of the first conductivity type formed so as to penetrate in the depth direction from the surface layer of the wide well region 31f as the second well region.
- the Schottky electrode 75 is an electrode provided on the fourth separation region 24.
- the ohmic electrode 70 as the second ohmic electrode is provided on the wide well region 31f.
- the SBD in the SBD built-in MOSFET, a part of the wide well region 31f is missing at a position closer to the unit cell region than the first well contact region 35f in the wide well region 31f and the first well contact region 31f.
- the SBD is formed so as to surround the active region, and the SBD is also provided in the first well contact region 35f in the wide well region 31f until the pn diode in the wide well region 31f operates.
- a unipolar current flows through the SBD built in the first well contact region 35f in the wide well region 31f.
- the conductivity modulation due to the bipolar current flowing from the pn diode in the wide well region 31f to the drift layer 20 immediately below the well region 30 of the unit cell is suppressed, and the voltage generated in the drift layer 20 immediately below the well region 30 of the unit cell.
- the drop can be kept sufficiently, and a decrease in the operating voltage of the pn diode in the well region 30 of the unit cell can be suppressed.
- FIG. 20 is a view of the SBD built-in MOSFET on which the current sense is mounted as viewed from above, that is, from the first main surface side, and the planar position of the active region is represented by a broken line.
- the source electrode 80a and the sense electrode 81 separated in a plane are formed on the first main surface.
- an active region made of an array of unit cells having the same layout as that formed in a part of the source electrode 80a is formed.
- the sectional view of this unit cell is the same as that of the unit cell below the source electrode 80 shown in FIG. 2, and it can be considered that the source electrode 80 is replaced with the sense electrode 81.
- the sense electrode 81 is provided so as to cover the Schottky electrode 75 formed on the first separation region 22 and the ohmic electrode 70 formed on the well region and the source region.
- a unit cell included in the active region below the source electrode 80a is referred to as a main cell
- a unit cell included in the active region below the sense electrode 81 is referred to as a sense cell.
- the gate electrode 60 and the drain electrode 85 in the main cell are electrically short-circuited with the corresponding electrodes in the sense cell and have the same potential.
- the sense electrode 81 is also operated at approximately 0 volts, which is substantially the same as the source electrode 80a.
- the same current always flows per unit cell of the sense cell and the main cell.
- the number of sense cells is overwhelmingly smaller than the number of main cells, for example, 1 / 10,000.
- the current flowing through the source electrode can be estimated.
- the overcurrent is detected and an off signal is given to the gate electrode 82 to prevent the element from being thermally destroyed. is there.
- FIG. 21 is a schematic cross-sectional view of a region from the end of the main cell array to the end of the sense cell array
- FIG. 22 is a schematic cross-sectional view of the region when the present invention is not used. . In either case, it is a schematic cross-sectional view corresponding to the portion c-c ′ in FIG.
- a gate electrode is formed so as to connect the two active regions, and a gate insulating film 50 or a field insulating film 52 is formed below the gate electrode.
- a gate insulating film 50 or a field insulating film 52 is formed below the gate electrode.
- the main cell and the sense cell are separated from each other by the wide well region 31.
- the third separated region 23 is missing in a part of the vicinity of the sense cell. Is formed.
- the wide well region 31 is formed on the surface layer of the drift layer 20 with a sense cell corresponding to a part of the plurality of well regions 30 sandwiched in plan view.
- the sense cell is separated from other well regions 30 by being sandwiched between the wide-area well regions 31 in plan view.
- the third separation region 23 is formed at a position closer to the sense cell than the ohmic electrode 70 in the wide well region 31.
- the Schottky electrode 75 is formed in such a manner that at least a part of the third separated region 23 is in contact.
- the Schottky electrode 75 is connected to the sense electrode 81 through an SBD contact hole 92 that penetrates the interlayer insulating film 55 and the gate insulating film 50.
- the wide well region 31a is formed without being lost, and the SBD contact hole 92 is not formed. Therefore, the interlayer insulating film 55a and the gate electrode 60a are formed up to the corresponding portion. ing.
- the fabrication method is almost the same as in the first embodiment, and it is only necessary to change each mask layout.
- the sense electrode 81 can be formed simultaneously with the source electrode 80 and the gate electrode 82, that is, by once depositing a metal material and patterning and etching using a photoresist.
- the third separation region may be continuously formed in a direction intersecting the direction approaching the sense region from the wide well region in plan view.
- the semiconductor device includes the sense region (sense cell) and the sense electrode 81.
- the sense cell is a region that includes at least one first well region 30 of the plurality of well regions 30 and is separated from other well regions 30 by being sandwiched between the wide-area well regions in plan view.
- the sense electrode 81 includes a Schottky electrode 75 as a first Schottky electrode formed on the first separation region 22 in the sense cell, and an ohmic electrode as a first ohmic electrode formed on the sense cell and the source region 40. 70 is provided.
- the sense electrode 81 is an electrode different from the source electrode 80.
- the SBD provided between the sense cell and the ohmic electrode in the wide well region causes a voltage drop even in the drift layer immediately below the sense cell, and the pn diode operation of the sense cell can be suppressed.
- This effect is obtained by forming the SBD in a form in which a part of the wide-area well region 31 near the sense cell is lost, and connecting the Schottky electrode 75 to the sense electrode 81 instead of the source electrode 80, thereby making the SBD more This is realized by being able to be placed close to the sense cell.
- the unipolar current flowing from the SBD arranged in a part of the wide well region 31 causes a voltage drop in the drift layer 20 and the substrate 10 immediately below and in the vicinity of the SBD, and the forward direction applied to the pn diode in the vicinity of the SBD. This can be explained from the fact that it is effective to dispose the SBD closer to the sense cell because of the mechanism of reducing the voltage.
- the occurrence of crystal defects in the sense cell is particularly harmful as compared with the occurrence of crystal defects in the main cell. This is because the number of cells for current sensing is much smaller than the number of cells in the main cell, and even if a crystal defect of the same area occurs, the resistance change of the entire active region is larger for current sensing. It is. If the resistance of the current sense changes, the current flowing through the source electrode 80 cannot be correctly estimated, and when the overcurrent flows, an off signal cannot be correctly given to the gate electrode 60, leading to element breakdown. Increase.
- FIG. 23 is a schematic cross-sectional view corresponding to the portion c-c ′ of FIG. As shown in FIG. 23, it is also effective to form SBDs for the wide well region 31 both in the vicinity of the main cell and in the vicinity of the sense cell and to be connected to the source electrode 80 and the sense electrode 81, respectively. .
- the flowing current is usually small and has a small capacity, so that it is more susceptible to breakage due to discharge due to static electricity or the like than the main cell. Therefore, in order to increase the capacity, the number of unit cells is increased, and in order to suppress to a desired current value, at least one of the sense cells is filled with the well region 30 without providing the second separation region 21, or the sense cell
- the source region 40 may not be provided in at least one of them. Even in this case, it is preferable to provide the third separation region 23 in the unit cell and form the SBD.
- nitrogen is used as the n-type (first conductivity type) impurity, but phosphorus or arsenic may be used.
- aluminum is used as the p-type (second conductivity type) impurity, but boron or gallium may be used.
- the semiconductor element using silicon carbide is particularly effective.
- the semiconductor element using silicon carbide is also effective in other wide gap semiconductor elements and has a certain effect even in a semiconductor element using silicon. .
- the first well contact region 35 is formed at a location in contact with the ohmic electrode 70 in the wide-area well region 31, but the first well contact region 35 may not be formed.
- an n-channel MOSFET is used.
- a p-channel MOSFET in which the first conductivity type is p-type and the second conductivity type is n-type may be used.
- the present invention can also be used for a MOSFET having a super junction structure.
- silicon oxide is used as the gate insulating film 50, but a deposited film by a CVD method may be used.
- a so-called vertical MOSFET in which the drain electrode 85 is formed on the back surface of the substrate 10 has been described.
- a so-called horizontal type MOSFET such as a RESURF MOSFET in which the drain electrode 85 is formed on the surface of the drift layer 20 is described. It can also be used for MOSFETs.
- MOSFET Metal-Semiconductor Field Effect Transistors.
- the source-side ohmic electrode 70 and the Schottky electrode 75 are separately manufactured.
- the source-side ohmic electrode 70 and the Schottky electrode 75 may be continuously formed of the same material, or may be continuously formed of different materials. Good.
- the unit structure may be a hexagonal shape, and further, for example, the cross-sectional structure in FIG. It may be a continuous stripe shape.
- the semiconductor device described in the above embodiment can be used for power, railway, car, home appliance, solar cell, communication, or the like.
- constituent elements constituting the invention are conceptual units, and include a case where one constituent element includes a plurality of structures and a case where one constituent element corresponds to a part of the structure. Further, each component of the present invention includes structures having other structures or shapes as long as the same functions are exhibited.
- 10 substrate 20 drift layer, 21 second separation region, 22 first separation region, 23, 23b, 23c, 23d third separation region, 24 fourth separation region, 30 well region, 31, 31a, 31b, 31c, 31f Wide well region, 35, 35f First well contact region, 37 JTE region, 40 source region, 50 gate insulating film, 52 field insulating film, 55, 55a interlayer insulating film, 60, 60a, 82 gate electrode, 70 ohmic electrode, 71 back ohmic electrode, 75 Schottky electrode, 80, 80a source electrode, 81 sense electrode, 85 drain electrode, 91 well contact hole, 92 SBD contact hole, 95 gate contact hole.
Abstract
Description
<構成>
まず、第1実施形態に関する半導体装置の構成を説明する。図1は、活性領域に配置されるSBD内蔵MOSFETのユニットセルの断面模式図である。図2は、SBD内蔵MOSFETのユニットセルを上から見た図であり、図1の電極又は絶縁膜などを透過し、半導体層が形成される領域(半導体領域)のみを表現している。
続いて、本実施形態の半導体装置であるSBD内蔵MOSFETの製造方法について説明する。
次に、本実施形態における半導体装置であるSBD内蔵MOSFETの動作を、3つの状態に分けて簡単に説明する。
以下に、本実施形態による効果を例示する。
<構成>
図13は、活性領域の終端部分のうち、ゲート電極82に隣接する箇所の構造を説明する、図4のa-a’の位置に相当する平面模式図であり、電極又は絶縁膜などを透過し、半導体領域のみが表現されている。また、図14は、活性領域の終端部分のうち、ゲート電極82が存在せず、チップ終端部分に隣接する箇所の構造を説明する、図4のb-b’の位置に相当する平面模式図であり、電極又は絶縁膜などを透過し、半導体領域のみが表現されている。
以下に、本実施形態による効果を例示する。
<構成>
図15は、活性領域の終端部分のうち、ゲート電極82に隣接する箇所の構造を説明する、図4のa-a’の位置に相当する平面模式図であり、電極又は絶縁膜などを透過し、半導体領域のみが表現されている。また、図16は、活性領域の終端部分のうち、ゲート電極82が存在せず、チップ終端部分に隣接する箇所の構造を説明する、図4のb-b’の位置に相当する平面模式図であり、電極又は絶縁膜などを透過し、半導体領域のみが表現されている。
以下に、本実施形態による効果を例示する。
<構成>
図18(a)部は、活性領域の終端部分のうち、ゲート電極82に隣接する箇所の構造を説明する図であり、図4のa-a’の位置に相当する断面模式図である。また、図18(b)部は、図18(a)部の箇所の平面模式図であり、電極及び絶縁膜などを透過し、半導体領域のみが表現されている。
以下に、本実施形態による効果を例示する。
<構成>
本実施形態では、電流センスを内蔵するSBD内蔵MOSFETを例に挙げて説明する。
以下に、本実施形態による効果を例示する。
上記実施形態では、n型(第1導電型)不純物として窒素を用いたが、リン又はヒ素であってもよい。
Claims (12)
- 第1導電型の半導体基板(10)上に形成された、第1導電型のドリフト層(20)と、
前記ドリフト層(20)表層において互いに離間して複数設けられた、第2導電型の第1ウェル領域(30)と、
前記ドリフト層(20)表層において複数の前記第1ウェル領域(30)全体を平面視上挟んで形成された、各前記第1ウェル領域(30)よりも形成面積が広い第2導電型の第2ウェル領域(31、31b、31f)と、
各前記第1ウェル領域(30)内において、各前記第1ウェル領域(30)表層から深さ方向に貫通して形成された第1導電型の第1離間領域(22)と、
各前記第1ウェル領域(30)表層において、平面視上前記第1離間領域(22)を挟んで形成された第1導電型のソース領域(40)と、
前記第1離間領域(22)上に設けられた第1ショットキー電極(75)と、
各前記第1ウェル領域(30)と各前記ソース領域(40)とに接触しつつ、各前記第1ウェル領域(30)上と各前記ソース領域(40)上とに設けられた第1オーミック電極(70)と、
各前記第1ウェル領域(30)を互いに離間させる領域である第1導電型の第2離間領域(21)と、
前記第2ウェル領域(31、31b、31f)上に設けられた第2オーミック電極(70)と、
前記第2ウェル領域(31、31b、31f)内の前記第2オーミック電極(70)よりも第1ウェル領域(30)に近い位置において、前記第2ウェル領域(31、31b、31f)表層から深さ方向に貫通して形成された第1導電型の第3離間領域(23、23b、23c)と、
前記第3離間領域(23、23b、23c)上に設けられた第2ショットキー電極(75)と、
前記第1及び第2ショットキー電極(75)と、前記第1及び第2オーミック電極(70)とが設けられた位置を除く前記第1及び第2ウェル領域(30、31、31b、31f)上の一部に、第1絶縁膜(50)を介して設けられたゲート電極(60)と、
前記ゲート電極(60)を覆って形成された第2絶縁膜(55)と、
前記第1及び第2ショットキー電極(75)と、前記第1及び第2オーミック電極(70)と、前記第2絶縁膜(55)とを覆って設けられたソース電極(80)とを備える、
半導体装置。 - 前記第2ショットキー電極(75)と前記第1ウェル領域(30)との間の距離が3μm以下である、
請求項1に記載の半導体装置。 - 前記第3離間領域(23b)が、平面視において前記第2ウェル領域(31b)から前記第1ウェル領域(30)に近づく方向と交差する方向に、連続的に形成される、
請求項1又は2に記載の半導体装置。 - 前記第3離間領域(23c)が、平面視において前記第2オーミック電極(70)を囲み、かつ、前記第2オーミック電極(70)を囲む少なくとも一部が欠損して形成される、
請求項1又は2に記載の半導体装置。 - 前記第2ウェル領域(31f)表層から深さ方向に貫通して形成された第1導電型の第4離間領域(24)と、
前記第4離間領域(24)上に設けられた第3ショットキー電極(75)とをさらに備え、
前記第2オーミック電極(70)が、前記第2ウェル領域(31f)上に設けられる、
請求項1又は2に記載の半導体装置。 - 前記ドリフト層(20)が、炭化珪素からなる、
請求項1又は2に記載の半導体装置。 - 第1導電型の半導体基板(10)上に形成された、第1導電型のドリフト層(20)と、
前記ドリフト層(20)表層において互いに離間して複数設けられた、第2導電型の第1ウェル領域(30)と、
前記ドリフト層(20)表層において複数の前記第1ウェル領域(30)のうちの一部を平面視上挟んで形成された、各前記第1ウェル領域(30)よりも形成面積が広い第2導電型の第2ウェル領域(31、31b)と、
複数の前記第1ウェル領域(30)のうちの少なくとも1つの前記第1ウェル領域(30)を含み、かつ、第2ウェル領域(31、31b)に平面視上挟まれることによって他の前記第1ウェル領域(30)から分離されたセンス領域と、
少なくとも前記センス領域における各前記第1ウェル領域(30)内において、各前記第1ウェル領域(30)表層から深さ方向に貫通して形成された第1導電型の第1離間領域(22)と、
少なくとも前記センス領域における各前記第1ウェル領域(30)表層において、平面視上前記第1離間領域(22)を挟んで形成された第1導電型のソース領域(40)と、
前記第1離間領域(22)上に設けられた第1ショットキー電極(75)と、
少なくとも前記センス領域における各前記第1ウェル領域(30)上と各前記ソース領域(40)上とに設けられた第1オーミック電極(70)と、
各前記第1ウェル領域(30)を互いに離間させる領域である第1導電型の第2離間領域(21)と、
前記第2ウェル領域(31、31b)上に設けられた第2オーミック電極(70)と、
前記第2ウェル領域(31、31b)内の前記第2オーミック電極(70)よりも前記センス領域に近い位置において、前記第2ウェル領域(31、31b)表層から深さ方向に貫通して形成された第1導電型の第3離間領域(23、23b)と、
前記第3離間領域(23、23b)上に設けられた第2ショットキー電極(75)と、
前記第1及び第2ショットキー電極(75)と、前記第1及び第2オーミック電極(70)とが設けられた位置を除く前記第1及び第2ウェル領域(30、31、31b)上の一部に、第1絶縁膜(50)を介して設けられたゲート電極(60)と、
前記ゲート電極(60)を覆って形成された第2絶縁膜(55)と、
前記第1ショットキー電極(75)と、前記第1オーミック電極(70)とを覆って設けられたセンス電極(81)とを備える、
半導体装置。 - 前記第2ショットキー電極(75)と前記第1ウェル領域(30)との間の距離が3μm以下である、
請求項7に記載の半導体装置。 - 前記第3離間領域(23b)が、平面視において前記第2ウェル領域(31b)から前記センス領域に近づく方向と交差する方向に、連続的に形成される、
請求項7又は8に記載の半導体装置。 - 前記センス領域は、複数の前記第1ウェル領域(30)を含み、
前記センス領域のうちの少なくとも1つの前記第1ウェル領域(30)において、前記ソース領域(40)が形成されていない、
請求項7又は8に記載の半導体装置。 - 前記センス領域は、複数の前記第1ウェル領域(30)を含み、
前記センス領域のうちの一部は、他の前記第1ウェル領域(30)との間の前記第2離間領域(21)が形成されていない、
請求項7又は8に記載の半導体装置。 - 前記ドリフト層(20)が、炭化珪素からなる、
請求項7又は8に記載の半導体装置。
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