WO2015008550A1 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- WO2015008550A1 WO2015008550A1 PCT/JP2014/064678 JP2014064678W WO2015008550A1 WO 2015008550 A1 WO2015008550 A1 WO 2015008550A1 JP 2014064678 W JP2014064678 W JP 2014064678W WO 2015008550 A1 WO2015008550 A1 WO 2015008550A1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
- H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
- H01L21/047—Making n or p doped regions or layers, e.g. using diffusion using ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0856—Source regions
- H01L29/0865—Disposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0882—Disposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1608—Silicon carbide
Definitions
- the present invention relates to a semiconductor device and a manufacturing method thereof.
- a structure in which a well region for forming a channel, a source region, and a drain region are formed in the drift region in a direction perpendicular to the surface from the drift region surface is known (for example, , See Patent Document 1).
- the trench-shaped gate electrode is also formed in the drift region in a direction perpendicular to the surface from the drift region surface.
- Such a semiconductor device has a lateral structure parallel to the surface of the semiconductor substrate, the direction of the main current directly controlled by the gate electrode is parallel to the surface of the semiconductor substrate, and the main current is perpendicular to the surface from the semiconductor substrate surface. Distributed in the direction. Therefore, the surface area of the semiconductor substrate is not limited. Further, since the channel width can be defined by the depth of the drift region, the channel width can be increased even with a certain surface area.
- the well region extends in the depth direction of the drift region, and the end of the well region is in the drift region.
- a guard ring is provided to prevent electric field concentration at the end of the well region.
- the semiconductor device described in Patent Document 1 since the semiconductor device described in Patent Document 1 has a lateral structure, it is difficult to form a guard ring, and the electric field concentration at the end of the well region cannot be reduced. Therefore, there is a problem that the breakdown voltage of the entire semiconductor device is lowered.
- an object of the present invention is to provide a semiconductor device capable of improving the breakdown voltage.
- a semiconductor device includes a substrate, a drift region of a first conductivity type formed on the first main surface of the substrate, made of the same material as the substrate, and having a higher impurity concentration than the substrate, and a drift region Inside, the second main surface opposite to the first main surface in contact with the substrate in the drift region extends in the direction perpendicular to the second main surface, and the end extends into the substrate.
- the drain region of the first conductivity type spaced apart from the well region and extending in the vertical direction from the second main surface, and the second region in the well region
- a first conductivity type source region extending in a vertical direction from the main surface, and a vertical direction from the second main surface, penetrating the source region and the well region in one direction parallel to the second main surface.
- the gate groove is extended so that the gate Comprising a gate electrode formed through a film, a source electrode electrically connected to the source region and the well region, and a drain electrode electrically connected to the drain region.
- FIG. 1 is a perspective view showing an example of a semiconductor device according to the first embodiment of the present invention.
- FIG. 2 is a perspective view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
- FIG. 3 is a perspective view subsequent to FIG. 2 for explaining the method of manufacturing the semiconductor device according to the first embodiment of the present invention.
- FIG. 4 is a perspective view subsequent to FIG. 3 for illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
- FIG. 5A is a perspective view subsequent to FIG. 4 for illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
- FIG. 5B is a cross-sectional view taken along the line AA in FIG.
- FIG. 6A is a perspective view subsequent to FIG.
- FIG. 5 for illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
- FIG. 6B is a top view of FIG.
- FIG. 7 is a perspective view subsequent to FIG. 6A for explaining the semiconductor device manufacturing method according to the first embodiment of the present invention.
- FIG. 8 is a perspective view showing a modification of the semiconductor device according to the first embodiment of the present invention.
- FIG. 9 is a perspective view showing another modification of the semiconductor device according to the first embodiment of the present invention.
- FIG. 10 is a perspective view showing still another modification of the semiconductor device according to the first embodiment of the present invention.
- FIG. 11 is a perspective view showing still another modification of the semiconductor device according to the first embodiment of the present invention.
- FIG. 12 is a perspective view showing an example of a semiconductor device according to the second embodiment of the present invention.
- 13 is a cross-sectional view taken along the line AA of FIG.
- FIG. 14A is a perspective view for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention.
- FIG. 14B is a perspective view subsequent to FIG. 14A for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention.
- FIG. 15A is a cross-sectional view taken along the line AA in FIG.
- FIG. 15B is a cross-sectional view taken along the line BB in FIG.
- FIG. 15C is a cross-sectional view taken along the line CC of FIG. 14B.
- 16 (a) to 16 (c) are cross-sectional views subsequent to FIGS.
- FIGS. 16 (a) to 16 (c) are cross-sectional views subsequent to FIGS. 16 (a) to 16 (c) for illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention.
- 18 (a) to 18 (c) are cross-sectional views subsequent to FIGS. 17 (a) to 17 (c) for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention.
- 19 (a) to 19 (c) are cross-sectional views subsequent to FIGS. 18 (a) to 18 (c) for illustrating a method for manufacturing a semiconductor device according to the second embodiment of the present invention. is there.
- 20 (a) to 20 (c) are cross-sectional views subsequent to FIGS. 19 (a) to 19 (c) for illustrating a method for manufacturing a semiconductor device according to the second embodiment of the present invention.
- 21 (a) to 21 (c) are cross-sectional views subsequent to FIGS. 20 (a) to 20 (c) for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention.
- 22 (a) to 22 (c) are cross-sectional views subsequent to FIGS. 21 (a) to 21 (c) for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention.
- 23 (a) to 23 (c) are cross-sectional views subsequent to FIGS.
- FIGS. 22 (a) to 22 (c) for illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention.
- 24 (a) to 24 (c) are cross-sectional views subsequent to FIGS. 23 (a) to 23 (c) for illustrating the method for manufacturing a semiconductor device according to the second embodiment of the present invention.
- 25 (a) to 25 (c) are cross-sectional views subsequent to FIGS. 24 (a) to 24 (c) for illustrating the method for manufacturing a semiconductor device according to the second embodiment of the present invention.
- FIG. 26 is a top view corresponding to FIGS. 25 (a) to 25 (c).
- 27 (a) to 27 (c) are cross-sectional views subsequent to FIGS.
- FIG. 25 (a) to 25 (c) for illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention.
- 28 (a) to 28 (c) are cross-sectional views subsequent to FIGS. 27 (a) to 27 (c) for illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention.
- FIG. 29 is a top view corresponding to FIGS. 28 (a) to 28 (c).
- FIG. 30 is a perspective view showing an example of a semiconductor device according to the third embodiment of the present invention.
- the “first conductivity type” and the “second conductivity type” are opposite conductivity types. That is, if the first conductivity type is n-type, the second conductivity type is p-type. If the first conductivity type is p-type, the second conductivity type is n-type. In the following description, the first conductivity type is n-type and the second conductivity type is p-type. However, the first conductivity type may be p-type and the second conductivity type may be n-type. When the n-type and the p-type are switched, the polarity of the applied voltage is also reversed.
- FIG. 1 is a perspective view schematically showing the configuration of the semiconductor device according to the first embodiment of the present invention.
- a metal oxide semiconductor field effect transistor MOSFET
- FIG. 1 the electrode wiring is not shown for easy understanding. 1 illustrates three semiconductor elements, but the present invention is not limited to this. For example, a large number of semiconductor elements may be arranged in the x-axis direction and the z-axis direction of FIG.
- the semiconductor device includes a substrate 1, an n ⁇ -type drift region 4 disposed on one main surface of the substrate 1, P-type well region 2 provided in the n-type region, an n + -type source region 3 provided in the well region 2, and an n + -type drain region provided in the drift region 4 and separated from the well region 2. 5 and a gate electrode 7 provided in the drift region 4 via the gate insulating film 6.
- the substrate 1 has a thickness of about several tens to several hundreds ⁇ m.
- a semi-insulating substrate or an insulating substrate can be used as the substrate 1, for example.
- the insulating substrate means a substrate having a sheet resistance of several k ⁇ / ⁇ or more
- the semi-insulating substrate means a substrate having a sheet resistance of several tens of ⁇ / ⁇ or more.
- silicon carbide SiC
- the substrate 1 is an insulating substrate made of silicon carbide will be described.
- the drift region 4 has a thickness of about several ⁇ m to several tens of ⁇ m.
- the impurity concentration of the drift region 4 is higher than that of the substrate 1 and is, for example, about 1 ⁇ 10 14 to 1 ⁇ 10 18 cm ⁇ 3 .
- Drift region 4 is made of the same material as substrate 1.
- substrate 1 is made of silicon carbide, it is an epitaxially grown layer made of silicon carbide.
- the well region 2 has a main surface (hereinafter referred to as “first main surface”) opposite to a main surface (hereinafter referred to as “first main surface”) in contact with the substrate 1 of the drift region 4 in the drift region 4. ) Extending in the direction perpendicular to the second main surface of the drift region 4 (y-axis direction in FIG. 1). Further, the end of the well region 2 extends to the inside of the substrate 1 in the direction perpendicular to the second main surface of the drift region 4 (the y-axis direction in FIG. 1).
- “the end of the well region 2” means a bottom surface of the well region 2 parallel to the second main surface of the drift region 4 and a second main surface of the drift region 4 that is continuous with the bottom surface.
- Means a part formed by a part of the side surface perpendicular to The well region 2 is extended in one direction (z-axis direction in FIG. 1) parallel to the second main surface of the drift region 4.
- the impurity concentration of the well region 2 is about 1 ⁇ 10 15 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 .
- the source region 3 extends from the second main surface of the drift region 4 in the well region 2 in the direction perpendicular to the second main surface of the drift region 4 (y-axis direction in FIG. 1). Source region 3 extends in parallel to well region 2 in one direction (z-axis direction in FIG. 1) parallel to the second main surface of drift region 4. Source region 3 has the same conductivity type as drift region 4. The impurity concentration of the source region 3 is higher than that of the drift region 4 and is about 1 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 21 cm ⁇ 3 .
- a source electrode 15 is electrically connected to the source region 3 and the well region 2 and takes the same potential.
- a material of the source electrode 15 for example, nickel (Ni), titanium (Ti), molybdenum (Mo), or the like can be used.
- a gate groove 8 is formed in the drift region 4.
- the gate groove 8 is provided from the second main surface of the drift region 4 in a direction perpendicular to the second main surface of the drift region 4 (y-axis direction in FIG. 1).
- the gate trench 8 extends so as to penetrate the source region 3 and the well region 2 in one direction (x-axis direction in FIG. 1) parallel to the second main surface of the drift region 4.
- the bottom surface of the gate trench 8 may be shallower than the bottom surface of the source region 3 or may coincide with the bottom surface of the source region 3.
- a gate electrode 7 is formed on the surface of the gate trench 8 via a gate insulating film 6.
- a silicon oxide film (SiO 2 film) can be used.
- the drain region 5 extends from the second main surface of the drift region 4 in the direction perpendicular to the second main surface of the drift region 4 (y-axis direction in FIG. 1).
- the drain region 5 extends in parallel with the well region 2 and the source region 3 in one direction (z-axis direction in FIG. 1) parallel to the second main surface of the drift region 4.
- Drain region 5 has the same conductivity type as drift region 4.
- the impurity concentration of the drain region 5 is higher than that of the drift region 4 and about the same as that of the source region 3, and is about 1 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 21 cm ⁇ 3 .
- a drain electrode 16 is electrically connected to the drain region 5.
- As the material of the drain electrode 16 for example, nickel (Ni), titanium (Ti), molybdenum (Mo), or the like can be used.
- the semiconductor device functions as a transistor by controlling the potential of the gate electrode 7 while applying a positive potential to the drain electrode 16 with reference to the potential of the source electrode 15. To do. That is, when the voltage between the gate electrode 7 and the source electrode 15 is set to a predetermined threshold voltage or more, an inversion layer serving as a channel is formed in the well region 2 located on the side surface of the gate electrode 7 and is turned on. A current flows to the electrode 15. Specifically, electrons flow from the source electrode 15 to the source region 3 and from the source region 3 to the drift region 4 through the channel. Further, it flows from the drift region 4 to the drain region 5 and finally flows to the drain electrode 16.
- the inversion layer of the well region 2 disappears and is turned off, and the current between the drain electrode 16 and the source electrode 15 is cut off. At this time, a high voltage of several hundred to several thousand volts is applied between the drain and the source.
- the channel width can be defined by the depth of the drift region 4, so that the channel width can be increased even at a constant surface area. It becomes possible. Further, since the end of the well region 2 extends into the substrate 1, the electric field concentration occurring at the end of the well region 2 can be greatly reduced, and the decrease in breakdown voltage can be suppressed. Further, the end of the well region 2 extends to the substrate 1, and the impurity concentration of the substrate 1 is lower than the impurity concentration of the drift region 4, so that the drift region 4 is aligned in the direction parallel to the second main surface of the drift region 4. 4 and the substrate 1 have the same length, the breakdown voltage between the substrate 1 and the well region 2 is larger than the breakdown voltage between the drift region 4 and the well region 2. Therefore, the breakdown voltage can be further improved as compared with the structure described in Patent Document 1.
- the substrate 1 is a semi-insulating substrate or an insulating substrate
- the end of the well region 2 is formed in the insulating region. For this reason, the breakdown voltage at the end of the well region 2 can be significantly increased, and a semiconductor device with a high breakdown voltage can be provided.
- silicon carbide As the material of the substrate 1, since silicon carbide has high insulation and high thermal conductivity, the back surface of the substrate 1 is attached to the cooling mechanism via an adhesive, thereby providing a semiconductor. Heat generated by current when the device is turned on can be efficiently dissipated, and the semiconductor device can be efficiently cooled.
- Silicon carbide is a semiconductor with a wide band gap and has a low intrinsic carrier concentration. Therefore, high insulation can be easily realized, and a semiconductor device with high breakdown voltage can be provided.
- a substrate 1 is prepared as shown in FIG.
- the substrate 1 is an insulating substrate made of non-doped silicon carbide and has a thickness of about several tens to several hundreds of ⁇ m.
- An n ⁇ type silicon carbide epitaxial layer is formed as drift region 4 on substrate 1.
- the drift region 4 is formed to have an impurity concentration of 1 ⁇ 10 14 to 1 ⁇ 10 18 cm ⁇ 3 and a thickness of several ⁇ m to several tens of ⁇ m, for example.
- a p-type well region 2, an n + -type source region 3 and an n + -type drain region 5 are formed in the drift region 4.
- the source region 3 and the drain region 5 may be formed simultaneously.
- An ion implantation method is used to form the well region 2, the source region 3 and the drain region 5.
- a mask material may be formed on the drift region 4 by the following process.
- a silicon oxide film (SiO 2 film) can be used as the mask material, and a thermal CVD method or a plasma CVD method can be used as the deposition method.
- a resist is applied on the mask material, and the resist is patterned using a general photolithography method or the like. A part of the mask material is selectively removed by etching using the patterned resist as a mask. As an etching method, wet etching using hydrofluoric acid or dry etching such as reactive ion etching (RIE) can be used. Next, the resist is removed with oxygen plasma or sulfuric acid. Thereafter, using the mask material as a mask, p-type and n-type impurities are ion-implanted into the drift region 4 to form a p-type well region 2 and an n + -type source region 3.
- RIE reactive ion etching
- the p-type impurity for example, aluminum (Al) or boron (B) can be used.
- n-type impurity for example, nitrogen (N) can be used.
- the mask material is removed by wet etching using, for example, hydrofluoric acid.
- the ion-implanted impurity is activated by heat treatment (annealing).
- the heat treatment temperature is, for example, about 1700 ° C., and argon (Ar) or nitrogen (N) can be suitably used as the atmosphere.
- the impurity concentration of the source region 3 and the drain region 5 formed by this method is preferably 1 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 21 cm ⁇ 3 , and the implantation depth is the first main region of the drift region 4. Shallow than the surface.
- the impurity concentration of the well region 2 is preferably 1 ⁇ 10 15 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 , and the implantation depth is deeper than the first main surface of the drift region 4, and the end of the well region 2 is Reaches the inside of the substrate 1.
- the thickness of the drift region 4 is 1 ⁇ m or more, the implantation energy may be above the MKeV level.
- a mask material 9 is formed in order to form the gate groove 8 in the drift region 4.
- the mask material 9 a material obtained by patterning an insulating film in the same manner as the mask material used in the process shown in FIG. 3 can be used.
- the gate groove 8 is formed using the mask material 9 as a mask. Note that the structure after the formation of the gate trench 8 is not shown.
- a dry etching method such as RIE is preferably used.
- the depth of the gate trench 8 is formed shallower than that of the source region 3.
- the mask material 9 is removed. For example, when the mask material 9 is a silicon oxide film, the mask material 9 is removed by cleaning with hydrofluoric acid.
- FIG. 5B shows the AA section of FIG.
- the gate insulating film 6 is formed on the surfaces of the drift region 4 and the gate groove 8 by a thermal oxidation method or a deposition method.
- a thermal oxidation method for example, in the case of thermal oxidation, a silicon oxide film is formed in all portions where the substrate comes into contact with oxygen by heating the substrate to a temperature of about 1100 ° C. in an oxygen atmosphere.
- the temperature is about 1000 ° C.
- a material to be the gate electrode 7 is deposited on the surface of the gate insulating film 6.
- Polysilicon is generally used as the material for the gate electrode 7 and will be described here using polysilicon.
- Low pressure CVD may be used as the polysilicon deposition method.
- the gate groove 8 can be completely filled with polysilicon. For example, when the width of the gate groove 8 is 2 ⁇ m, the thickness of the polysilicon is made thicker than 1 ⁇ m. Further, by annealing in POCl 3 at about 950 ° C.
- FIGS. 5A and 5B show the structure after the polysilicon is etched. 5A and 5B, the depths of the gate grooves 8 are different from each other. However, as shown in FIG. 5A, they may coincide with the bottom surface of the source region 3, It may be formed shallower than the source region 3 as shown in FIG.
- FIG. 6A an interlayer insulating film 10 is formed, and an electrode contact hole 11 is formed.
- FIG. 6B shows the position of the contact hole 11 as viewed from directly above.
- the interlayer insulating film 10 is not shown in FIG.
- the interlayer insulating film 10 is generally preferably a silicon oxide film, and a thermal CVD method or a plasma CVD method can be used as a deposition method.
- a resist is applied on the interlayer insulating film 10, and the resist is patterned using a general photolithography method (not shown).
- a part of the interlayer insulating film 10 is selectively removed by wet etching using hydrofluoric acid or the like or dry etching such as reactive ion etching (RIE), and the contact hole 11 is opened. To do. Thereafter, the resist is removed with oxygen plasma or sulfuric acid. 6A and 6B show the shape after the contact hole 11 is opened.
- RIE reactive ion etching
- a gate wiring 12, a source wiring 13, and a drain wiring 14 are formed as shown in FIG.
- the interlayer insulating film between the gate wiring 12, the source wiring 13, and the drain wiring 14 is omitted for easy understanding.
- metal wiring such as titanium (Ti), nickel (Ni), molybdenum (Mo), or the like can be used.
- Ti titanium
- Ni nickel
- Mo molybdenum
- a specific method for forming the gate wiring 12, the source wiring 13, and the drain wiring 14 is described using Ti. First, Ti is deposited by MOCVD or the like. Next, Ti is selectively etched using a resist or the like as a mask. Next, an interlayer insulating film of the gate wiring 12 and the source wiring 13 is deposited to form a contact hole.
- the interlayer insulating film is deposited by sputtering or the like, and the contact hole can be formed in the same manner as shown in FIG.
- a metal material to be the source wiring 13 is deposited and etched by the same method as the formation of the gate wiring 12.
- an interlayer insulating film of the source wiring 13 and the drain wiring 14 is deposited, a contact hole is formed, and a metal material of the drain wiring 14 is deposited.
- FIG. 7 shows the semiconductor device after the drain wiring 14 is formed. Through the above steps, the semiconductor device shown in FIG. 1 is completed.
- the semiconductor device manufacturing method according to the first embodiment of the present invention can realize the semiconductor device capable of improving the breakdown voltage shown in FIG.
- the substrate 1 is an insulating or semi-insulating substrate.
- the substrate 1 is a semiconductor substrate having the same conductivity type (n-type) as the drift region 4. The case where it is is demonstrated.
- the substrate 1 is made of, for example, silicon carbide, and the impurity concentration of the substrate 1 is lower than the impurity concentration of the drift region 4.
- the operation method and manufacturing method of the semiconductor device in this case are substantially the same as the case where the substrate 1 is an insulating or semi-insulating substrate.
- the substrate 1 is a semiconductor substrate of a conductivity type (p-type) different from that of the drift region 4, current flows from the source region 3 through the well region 2 in which the channel is formed in the ON state of the semiconductor device.
- a depletion layer spreads from the substrate 1 to the drift region 4. This narrows the current path and reduces the current.
- the breakdown voltage between the substrate 1 and the drift region 4 must be carefully designed.
- the substrate 1 is a semiconductor substrate having the same conductivity type (n-type) as the drift region 4, the current path can be extended to the substrate 1. As a result, the current can be increased, and a reduction in loss can be expected.
- the breakdown voltage between the substrate 1 and the drift region 4 is simplified in design, and a high breakdown voltage semiconductor device can be provided.
- FIG. 8 shows a semiconductor device having a structure modified from FIG.
- the semiconductor device shown in FIG. 8 is different from the structure of the semiconductor device shown in FIG. 1 in that the source region 3 and the drain region 5 are extended into the substrate 1.
- the semiconductor device manufacturing method shown in FIG. 8 is characterized in that impurities are implanted deeper than the first main surface of the drift region 4 during ion implantation for forming the source region 3 and the drain region 5. Unlike the first embodiment, the other procedures are substantially similar.
- the source region 3 is extended into the substrate 1, whereby the side area of the source region 3 perpendicular to the second main surface of the drift region 4 is increased. Therefore, the current when the semiconductor device is in an on state can be increased, and loss can be reduced.
- the drain region 5 extends into the substrate 1, the side area of the drain region 5 perpendicular to the second main surface of the drift region 4 is increased. Therefore, the current when the semiconductor device is in an on state can be increased, and loss can be reduced.
- the side areas of the source region 3 and the drain region 5 can be utilized to the maximum. A large current can flow.
- the source region 3 and the drain region 5 are both extended into the substrate 1, but one of the source region 3 and the drain region 5 extends into the substrate 1. Even when it is extended, it is possible to pass a larger current compared to the structure shown in FIG.
- FIG. 9 shows a semiconductor device having a structure modified from FIG.
- the semiconductor device shown in FIG. 9 is different from the semiconductor device shown in FIG. 8 in that the gate groove 8 is dug deeper and a part of the gate groove 8 enters the substrate 1.
- the operation method of the semiconductor device shown in FIG. 9 is substantially the same as that of the semiconductor device shown in FIG.
- the semiconductor device manufacturing method shown in FIG. 9 differs from the semiconductor device shown in FIG. 8 in that the gate groove 8 is formed deeper than the first main surface of the drift region 4 in the step of forming the gate groove 8. The procedure is substantially the same.
- a part of the gate groove 8 extends into the substrate 1, so that the bottom surface of the gate groove 8 and the corner portion formed by the bottom surface and the side surface are inside the substrate 1.
- the electric field concentration at the bottom and corners of the gate groove 8 is the structure shown in FIG.
- the withstand voltage can be improved.
- the capacitance generated in this region becomes the capacitance between the gate and the drain, and loss occurs during the operation of the semiconductor device.
- the substrate 1 is an insulating substrate, there is almost no capacity in the region in contact with the substrate 1, so that loss during operation of the semiconductor device can be reduced.
- FIG. 10 shows a semiconductor device having a structure modified from FIG.
- the semiconductor device shown in FIG. 10 is different from the semiconductor device shown in FIG. 9 in that the bottom of the gate groove 8 enters the well region 2.
- the operation method of the semiconductor device shown in FIG. 10 is substantially the same as that of the semiconductor device shown in FIG. 10 differs from the semiconductor device shown in FIG. 9 in that the gate groove 8 is formed deeper than the source region 3 in the step of forming the gate groove 8 in the manufacturing method of the semiconductor device shown in FIG.
- the procedure is substantially similar.
- the gate groove 8 when the gate groove 8 is deeper than the source region 3 in the direction perpendicular to the second main surface of the drift region 4 and the bottom surface of the gate groove 8 is located in the well region 2,
- the gate-source capacitance generated in the region in contact with the well region 2 on the bottom surface of the substrate via the gate insulating film 6 varies depending on the voltage of the gate electrode 7.
- the well region 2 is a p-type semiconductor
- the gate voltage when the gate voltage is negative, a depletion layer spreads in the well region 2 and the gate-source capacitance generated at the bottom surface of the gate groove 8 is small.
- the gate voltage is positive and equal to or higher than the threshold voltage of the semiconductor device
- the well-source region 2 is inverted and the gate-source capacitance generated at the bottom surface of the gate trench 8 is the maximum and becomes the capacitance of the gate insulating film 6.
- the capacitance of the region formed by the gate electrode 7, the gate insulating film 6 and the source region 3 is the gate voltage. Regardless, it always becomes the capacity of the gate insulating film 6.
- the gate-source capacitance can be reduced at the bottom of the gate groove 8, a low-loss semiconductor device can be provided.
- FIG. 11 shows a semiconductor device having a structure modified from FIG.
- the semiconductor device shown in FIG. 11 is different from the semiconductor device shown in FIG. 10 in that the bottom of the gate groove 8 is formed deeper than the well region 2.
- the semiconductor device manufacturing method shown in FIG. 11 is different from the semiconductor device shown in FIG. 10 in that the gate groove 8 is formed deeper than the well region 2 in the step of forming the gate groove 8.
- the thermal silicon is different.
- the oxide film formed on the bottom surface of the gate groove 8 parallel to the second main surface of the drift region 4 is the second main surface of the drift region 4. It becomes thinner than the oxide film formed on the side surface perpendicular to the surface. For this reason, the gate-source breakdown voltage between the gate electrode 7 and the source electrode 15 becomes weak at the bottom surface of the gate groove 8.
- the gate-source capacitance generated at the bottom surface of the gate groove 8 occupies a large proportion of the total gate-source capacitance.
- the gate-source capacitance at the bottom surface of the gate groove 8 also increases, resulting in loss when the semiconductor element operates. An increasing problem occurs.
- the bottom surface of the gate groove 8 contacts the substrate 1 and is not electrically connected to the source region 3. For this reason, the gate-source capacitance between the gate electrode 7 and the source electrode 15 hardly occurs at the bottom surface of the gate groove 8. Therefore, by reducing the gate-source capacitance generated at the bottom surface of the gate trench 8, the total capacitance between the gate and source can be greatly reduced, and a semiconductor device with low loss and high reliability can be provided. Furthermore, when the substrate 1 is an insulating substrate, the gate-drain capacitance formed on the bottom surface of the gate groove 8 can be reduced, and a low-loss semiconductor device can be provided.
- FIG. 12 is a perspective view showing a configuration of a semiconductor device according to the second embodiment of the present invention.
- the electrode wiring is not shown for easy understanding.
- the structure of the electrode wiring is the same as in FIG.
- the source groove 17 is formed in the source region 3 and the drain groove 20 is formed in the drain region 5 as shown in FIG. This is different from the first embodiment of the present invention.
- a p + type well contact region 19 having a higher impurity concentration than the well region 2 is formed at the bottom of the source trench 17 so as to be in contact with the well region 2.
- a conductive layer 24 is embedded in the source groove 17.
- the conductive layer 24 is at the same potential as the source electrode 15, and the source region 3 and the well contact region 19 are ohmically connected.
- a conductive layer 25 is embedded in the drain trench 20.
- the conductive layer 25 has the same potential as the drain electrode 16 and is ohmically connected to the drain region 5.
- a material of the conductive layers 24 and 25 for example, a conductive material such as nickel (Ni), titanium (Ti), or molybdenum (Mo) can be used.
- the width of the source groove 17 is a
- the width of the drain groove 20 is b
- the width of the gate groove 8 is c
- the relationship is a> b> c. That is, the width a of the source trench 17 is wider than the width b of the drain trench 20, and the width b of the drain trench 20 is wider than the width c of the gate trench 8.
- FIG. 13 shows a cross-sectional view of the portion of the source groove 17 when viewed along the AA section of FIG.
- the gate electrode 7 is ohmically connected to the conductive layer 18 and has the same potential as the conductive layer 18. Further, the gate electrode 7 and the conductive layer 24 are insulated by the interlayer insulating film 10.
- the end of the well region 2 extends into the substrate 1, the electric field concentration occurring at the end of the well region 2 can be greatly reduced, The decrease can be suppressed. Further, the end of the well region 2 extends to the substrate 1, and the impurity concentration of the substrate 1 is lower than the impurity concentration of the drift region 4, so that the drift region 4 is aligned in the direction parallel to the second main surface of the drift region 4. 4 and the substrate 1 have the same length, the breakdown voltage between the substrate 1 and the well region 2 is larger than the breakdown voltage between the drift region 4 and the well region 2. Therefore, the breakdown voltage can be further improved as compared with the structure described in Patent Document 1.
- the substrate 1 is a semi-insulating substrate or an insulating substrate
- the end of the well region 2 is formed in the insulating region. For this reason, the breakdown voltage at the end of the well region 2 can be significantly increased, and a semiconductor device with a high breakdown voltage can be provided.
- silicon carbide As the material of the substrate 1, since silicon carbide has high insulation and high thermal conductivity, the back surface of the substrate 1 is attached to the cooling mechanism through the conductive material, thereby providing a semiconductor. Heat generated by current when the device is turned on can be efficiently dissipated, and the semiconductor device can be efficiently cooled. Further, since silicon carbide is a semiconductor with a wide band gap and a low intrinsic carrier concentration, high insulation can be easily realized, and a semiconductor device with high breakdown voltage can be provided.
- the depth of the impurity implantation can be made shallower than that in the first embodiment in forming the source region 3 and the well region 2. Accordingly, since a high implantation energy is not required, a low-cost semiconductor device can be provided.
- the conductive layer 24 is embedded in the source trench 17, and the conductive layer 24 and the source region 3 are electrically at the same potential.
- a resistance component is attached in a direction perpendicular to the substrate 1 in the source region 3. This resistance component acts to reduce the current when the semiconductor device operates, resulting in a reduction in current.
- the resistance component in the vertical direction of the source region 3 becomes a resistance component obtained by paralleling the resistance component of the source region 3 and the resistance component of the conductive layer 24.
- the resistance of the conductive layer 24 is generally smaller than the resistance of the semiconductor, thereby lowering the parallel resistance component. Therefore, a low-loss semiconductor device can be provided.
- the gate groove 8 and the source groove 17 are simultaneously formed using a mask pattern.
- the width a of the gate groove 8 is 1 ⁇ m
- the width c of the source groove 17 is 2 ⁇ m.
- the source region 3 can be formed by implanting oblique ions of n-type impurities.
- the well region 2 can be formed by implanting p-type impurities obliquely. Therefore, the gate trench 8 and the source trench 17 can be formed at once, and the source region 3 and the well region 2 can be formed by self-alignment. That is, it is possible to provide a semiconductor device that can be easily manufactured at low cost.
- the drain groove 20 in the drain region 5
- the depth of the impurity implantation can be made shallower than that in the first embodiment in the formation of the drain region 5. For this reason, since high injection energy is not required, a low-cost semiconductor device can be provided.
- the conductive layer 25 is embedded in the drain groove 20, and the conductive layer 25 and the drain region 5 are electrically at the same potential.
- the resistance component of the drain region 5 is attached in the direction perpendicular to the second main surface of the drift region 4. This resistance component acts to reduce the current when the semiconductor device operates, resulting in a reduction in current.
- the resistance component in the vertical direction of the drain region 5 becomes a resistance component obtained by paralleling the resistance component of the drain region 5 and the resistance component of the conductive layer 25.
- the resistance of the conductive layer 25 is generally lower than that of a semiconductor, thereby lowering the parallel resistance component. That is, a low-loss semiconductor device can be provided.
- the drain groove 20 and the gate groove 8 can be formed at the same time, and the drain region 5 can be formed without using a mask.
- the drain groove 20 and the gate groove 8 are simultaneously formed with a mask pattern.
- the width c of the gate groove 8 is 1 ⁇ m
- the width b of the drain groove 20 is 2 ⁇ m.
- the drain region 5 can be formed by oblique ion implantation of n-type impurities. Therefore, the drain region 5 can be formed by self-alignment. That is, it is possible to provide a semiconductor device that is inexpensive and easy to manufacture.
- a drain groove 20 is formed in the drain region 5 and a source groove 17 is formed in the source region 3.
- Conductive layers 24 and 25 are disposed in the source groove 17 and the drain groove 20, and the conductive layers 24 and 25 and the source region 3 and the drain region 5 have the same potential.
- the effect of this structure will be described using the drain region 5 as an example.
- the resistance component of the drain region 5 is attached in the direction perpendicular to the second main surface of the drift region 4. This resistance component acts to reduce the current when the semiconductor device operates, resulting in a reduction in current.
- the resistance component in the vertical direction of the drain region 5 becomes a resistance component obtained by paralleling the resistance component of the drain region 5 and the resistance component of the conductive layer 25.
- the resistance of the conductive layer 25 is generally lower than that of a semiconductor, thereby lowering the parallel resistance component.
- the same effect as that of the drain region 5 can be obtained in the source region 3 and the current in the on operation of the semiconductor device can be increased. That is, a low-loss semiconductor device can be provided.
- the gate groove 8 since the width a of the source groove 17 is wider than the width b of the drain groove 20 and the width b of the drain groove 20 is wider than the width c of the gate groove 8, the gate groove 8, the source groove 17 and the drain groove 20 can be simultaneously formed.
- the source region 3, the drain region 5, and the well region 2 can be formed by self-alignment. Therefore, it is possible to provide a highly reliable semiconductor device that is easy to manufacture, low in cost, free from misalignment.
- the well contact region 19 can be formed by self-alignment, is easy to manufacture, is low cost, and provides a highly reliable semiconductor device without misalignment. it can. Further, when the well contact region 19 is a p-type region having a high impurity concentration, it is easy to make an ohmic connection with the conductive layer 24, the contact resistance can be lowered, and the potential of the well region 2 can be easily controlled by the source electrode 15. For this reason, a highly reliable semiconductor device can be provided.
- a substrate 1 is prepared.
- the substrate 1 is an insulating substrate made of non-doped silicon carbide and has a thickness of about several tens to several hundreds of ⁇ m.
- An n ⁇ type silicon carbide epitaxial layer is formed as drift region 4 on substrate 1.
- the drift region 4 has, for example, an impurity concentration of 1 ⁇ 10 14 to 1 ⁇ 10 18 cm ⁇ 3 and a thickness of several ⁇ m to several tens of ⁇ m.
- FIG. 14B is a perspective view after forming the mask material 9 for simultaneously forming the gate groove 8, the drain groove 20 and the source groove 17.
- the mask material 9 a material obtained by patterning an insulating film can be used as in the process shown in FIG.
- the gate groove 8, the drain groove 20, and the source groove 17 are formed by a dry etching method or the like. Further, as shown in FIG.
- a step of depositing the mask material 21 (hereinafter referred to as “second step”) is performed.
- a silicon oxide film can be used as the mask material 21, and a thermal CVD method, a plasma CVD method, or a low pressure CVD method can be used as a deposition method. Among these, the low pressure CVD method is preferable from the viewpoint of improving the film coverage.
- the deposited thickness is at least half of the width c of the gate trench 8 and less than half of the width b of the drain trench 20.
- the thickness of the mask material 21 is set in the range of 0.5 ⁇ m or more and less than 1 ⁇ m.
- the thickness after setting the thickness and depositing the mask material 21 is shown in FIGS. 16 (a) to 16 (c).
- the gate groove 8 is completely filled with the mask material 21, and the source groove 17 and the drain groove 20 are not completely filled.
- a step of forming the drain region 5 and the source region 3 simultaneously (hereinafter referred to as “third step”) is performed.
- an ion implantation method is used.
- the mask material 21 deposited in the second step is used as a mask in the implantation region without patterning by photolithography, unlike the first embodiment.
- the source region 3 and the drain region 5 are n-type, nitrogen (N) or phosphorus (P) can be used as the n-type impurity.
- N nitrogen
- P phosphorus
- the traveling direction of the ion beam is inclined at a certain angle from the direction perpendicular to the main surface of the substrate 1 so that impurities are implanted also into the sidewalls of the drain trench 20 and the source trench 17.
- the impurity concentration is preferably 1 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 21 cm ⁇ 3 .
- the implantation depth is set to be thicker than the mask material 21 and thinner than the total thickness of the mask material 21 and the mask material 9. The reason is that when the implantation is performed deeper than the mask material 9, n-type impurities are also implanted into the surface of the drift region 4.
- the semiconductor device after the third step is shown in FIGS. 17 (a) to 17 (c). As shown in FIGS. 17A to 17C, n-type impurities are implanted into the side walls and bottom of the source trench 17 and the drain trench 20, respectively.
- a step of depositing the mask material 22 (hereinafter referred to as “fourth step”) is performed.
- a silicon oxide film can be used as the mask material 22, and a thermal CVD method, a plasma CVD method, or a low pressure CVD method can be used as a deposition method. Among these, the low pressure CVD method is preferable from the viewpoint of improving the film coverage.
- the deposition thickness is set to be equal to or greater than the value obtained by subtracting the thickness of the mask material 21 from half the width b of the drain groove 20 and less than the value obtained by subtracting the thickness of the mask material 21 from half the width c of the source groove 17.
- FIGS. 18A to 18C show the shapes after setting the thickness and depositing the mask material 22 in this way. As shown in FIGS. 18A to 18C, the gate groove 8 and the drain groove 20 are completely filled with the mask material 21 and the mask material 22, and the source groove 17 is not completely filled. Become.
- a step of forming the well region 2 (hereinafter referred to as “fifth step”) is performed.
- an ion implantation method is used. Unlike the first embodiment, patterning by photolithography is not used for the implantation region.
- the mask material 21 and the mask material 22 deposited in the second process and the fourth process are used as a mask. Since the well region 2 is p-type, aluminum (Al) or boron (B) can be used as the p-type impurity.
- Al aluminum
- B boron
- the traveling direction of the ion beam is inclined at a certain angle from the direction perpendicular to the main surface of the substrate 1 so that impurities are implanted into the side wall and the bottom surface of the source groove 17.
- the impurity concentration is preferably 1 ⁇ 10 15 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 .
- the implantation depth is set to be deeper than the total thickness of the mask material 21, the mask material 22, and the source region, and shallower than the total thickness of the mask material 21, the mask material 22, and the mask material 9.
- the semiconductor device after the fifth step is shown in FIGS. 19 (a) to 19 (c). As shown in FIGS. 19A to 19C, p-type impurities are implanted into the side wall and the bottom of the source trench 17.
- a step of forming the well contact region 19 (hereinafter referred to as “sixth step”) is performed.
- the mask material 21 and the mask material 22 may be etched before the sixth step is performed. Etching is performed on the entire surface without selective etching using a photolithography method.
- anisotropic dry etching such as reactive ion etching (RIE) is suitable as an etching method.
- the etching thickness may be the total thickness of the mask material 21 and the mask material 22.
- 20A to 20C show cross-sectional structures after anisotropic dry etching. As shown in FIGS.
- the gate groove 8 and the drain groove 20 are still completely filled with the mask material 21 and the mask material 22.
- the mask material 21 and the mask material 22 remain on the side wall of the source groove 17, but the source region 3 is exposed on the bottom surface of the source groove 17. Further, the mask material 9 remains on the surface of the drift region 4.
- a sixth step of forming the well contact region 19 by ion implantation is performed on this shape. Since the well contact region 19 is p-type, aluminum (Al) or boron (B) can be used as the p-type impurity. At this time, by performing ion implantation while the substrate temperature is heated to about 600 ° C., the occurrence of crystal defects in the implanted region can be suppressed.
- the implantation concentration of the p-type impurity is preferably at least twice the impurity concentration of the source region 3.
- the implantation depth may be deeper than the source region 3 and shallower than the well region 2.
- the mask material 9, the mask material 21, and the mask material 22 are removed.
- the mask material 9, the mask material 21, and the mask material 22 are silicon oxide films, they can be removed by hydrofluoric acid cleaning.
- the ion-implanted impurity is activated by heat treatment (annealing).
- a temperature of about 1700 ° C. can be used as the heat treatment temperature, and argon (Ar) or nitrogen (N) can be suitably used as the atmosphere.
- the gate insulating film 6 is formed.
- the cross-sectional structure after forming the gate insulating film 6 is shown in FIGS.
- the formation method of the gate insulating film 6 may be a thermal oxidation method or a deposition method.
- a silicon oxide film is formed in all portions where the substrate comes into contact with oxygen by heating the substrate in an oxygen atmosphere at a temperature of about 1100 ° C.
- annealing is performed at about 1000 ° C. in an atmosphere of nitrogen (N), argon (Ar), N 2 O, or the like, in order to reduce the interface state between the well region 2 and the gate insulating film 6 interface. May be performed.
- a material 23 to be the gate electrode 7 is deposited.
- the cross-sectional structure after deposition is shown in FIGS. 23 (a) to 23 (c).
- the material 23 to be the gate electrode 7 is generally polysilicon, and here, description will be made using polysilicon.
- a low pressure CVD method may be used as a method for depositing the polysilicon 23 .
- the deposited thickness of the polysilicon 23 is set to a value larger than 1 ⁇ 2 of the width c of the gate groove 8.
- the gate groove 8 can be completely filled with the polysilicon 23.
- the width c of the gate groove 8 is 2 ⁇ m
- the thickness of the polysilicon 23 is made thicker than 1 ⁇ m.
- the n-type polysilicon 23 is formed, and the gate electrode 7 can be made conductive.
- the polysilicon 23 other than the gate electrode 7 is etched.
- the etching method can be applied to isotropic etching or anisotropic etching.
- the etching amount is set so that the polysilicon 23 remains in the gate groove 8.
- the etching amount is preferably 1.5 ⁇ m. % Overetching is no problem.
- FIGS. 24A to 24C show the structure after the polysilicon 23 is etched and the gate electrode 7 is formed.
- FIG. 25A to FIG. 25C show the cross-sectional structure after the interlayer insulating film 10 is formed.
- FIG. 26 shows the position of the contact hole 11 viewed from directly above.
- the interlayer insulating film 10 is generally preferably a silicon oxide film, and a thermal CVD method or a plasma CVD method can be used as a deposition method.
- a contact hole is opened.
- a resist is applied on the interlayer insulating film 10, and the resist is patterned using a general photolithography method.
- the interlayer insulating film 10 is etched using the patterned resist as a mask.
- etching method wet etching using hydrofluoric acid or dry etching such as reactive ion etching (RIE) can be used.
- RIE reactive ion etching
- the conductive layer 18, the conductive layer 24, and the conductive layer 25 are formed.
- metals such as titanium (Ti), nickel (Ni), and molybdenum (Mo) are generally used.
- Ti is deposited.
- the MOCVD method is suitable as the deposition method.
- selective etching of Ti using a mask is performed.
- a resist is suitable for the mask material.
- 28A to 28C show the cross-sectional structure after etching, and FIG. 29 shows the surface structure. In FIG. 29, the interlayer insulating film 10 is not shown for easy understanding.
- gate wiring, source wiring, and drain wiring are formed (not shown) as in the first embodiment.
- the manufacturing cost can be reduced by simultaneously forming the gate groove 8, the source groove 17 and the drain groove 20 in the first step.
- a semiconductor device can be manufactured with high reliability with less misalignment of the mask than when formed individually.
- the gate groove 8, the source groove 17, and the drain groove 20 are formed so that the width a of the source groove 17 is wider than the width b of the drain groove 20, and the width b of the drain groove 20 is wider than the width c of the gate groove 8. .
- the drain groove 20 The mask material 21 is deposited with a thickness of half or less of the width b.
- the source region 3 and the drain region 5 can be simultaneously formed on the side walls or the bottom surface of the source trench 17 and the drain trench 20 by ion implantation of n-type impurities from an oblique direction. Therefore, compared with the conventional manufacturing technique, the source region 3 and the drain region 5 can be simultaneously formed at a predetermined position by one injection, and the cost can be reduced. Furthermore, since no mask is used, there is no misalignment and a semiconductor device can be manufactured with high reliability.
- the thickness of the mask material 22 is set so as to completely fill the drain groove 20 and leave a space in the source groove 17. .
- the mask material 22 can be formed by self-alignment without using a photolithography method. That is, there is no misalignment due to the mask, and the semiconductor device can be manufactured with high reliability.
- the fifth step it is possible to form the well region 2 on the bottom and side walls of the source groove 17 so as to surround the source region 3 by ion implantation of p-type impurities from an oblique direction. Since a mask is not used as compared with the conventional manufacturing technique, there is no misalignment and a semiconductor device can be manufactured with high reliability.
- a well contact region 19 is formed by ion implantation of p-type impurities into the substrate 1 using a vertical ion implantation method.
- the implantation depth is deeper than the source region 3 in contact with the bottom of the source trench 17 and the impurity concentration is higher than that of the source region 3 in contact with the bottom of the source trench 17.
- the well contact region 19 may be formed by ion implantation of p-type impurities in the sixth step without removing the mask material 21 and the mask material 22.
- the implantation concentration is set to be twice or more the impurity concentration of the source region 3, and the implantation depth is set deeper than the total thickness of the mask material 21, mask material 22 and source region 3 and shallower than the well region 2.
- the well contact region 19 may be formed by first removing the source region 3 and then implanting p-type impurities vertically. Since the source region 3 is removed, the implantation concentration has no relation to the impurity concentration of the source region 3. Also, the implantation depth need only be set shallower than the well region 2. Since the cost of ion implantation varies depending on the impurity concentration and depth, there is no limitation on the implantation concentration and implantation depth for forming the well contact region 19, so that the well contact region 19 can be formed at low cost.
- the structure of the substrate 1 is modified with respect to the first embodiment of the present invention.
- a high impurity concentration n + is formed on the main surface (back surface) opposite to the main surface in contact with the drift region 4 of the substrate 1.
- a back conductive region 26 of the mold is formed. Drain region 5 extends from second main surface of drift region 4 to back surface conductive region 26 in a direction perpendicular to the second main surface of drift region 4.
- the drain wiring 14 is electrically connected to the main surface (back surface) opposite to the main surface in contact with the substrate 1 of the back surface conductive region 26.
- the end of the well region 2 extends into the substrate 1, the electric field concentration occurring at the end of the well region 2 can be greatly reduced, The decrease can be suppressed. Further, the end of the well region 2 extends to the substrate 1, and the impurity concentration of the substrate 1 is lower than the impurity concentration of the drift region 4, so that the drift region 4 is aligned in the direction parallel to the second main surface of the drift region 4. 4 and the substrate 1 have the same length, the breakdown voltage between the substrate 1 and the well region 2 is larger than the breakdown voltage between the drift region 4 and the well region 2. Therefore, the breakdown voltage can be further improved as compared with the structure described in Patent Document 1.
- the substrate 1 is a semi-insulating substrate or an insulating substrate
- the end of the well region 2 is formed in the insulating region. For this reason, the breakdown voltage at the end of the well region 2 can be significantly increased, and a semiconductor device with a high breakdown voltage can be provided.
- silicon carbide As the material of the substrate 1, since silicon carbide has high insulation and high thermal conductivity, the back surface of the substrate 1 is attached to the cooling mechanism through the conductive material, thereby providing a semiconductor. Heat generated by current when the device is turned on can be efficiently dissipated, and the semiconductor device can be efficiently cooled. Further, since silicon carbide is a semiconductor with a wide band gap and a low intrinsic carrier concentration, high insulation can be easily realized, and a semiconductor device with high breakdown voltage can be provided.
- a back surface conductive region 26 of the same conductivity type (n type) as the drain region 5 is formed on the back surface of the substrate 1, and the drain region 5 is in contact with the back surface conductive region 26, so that the drain electrode (not shown) is attached to the substrate 1. It becomes possible to arrange on the back side. Thereby, the gate electrode 7 and the source electrode (not shown) can be arranged on the surface of the semiconductor device, and the drain electrode (not shown) can be arranged on the back side of the semiconductor device. Therefore, the area of the drain wiring 14 connected to the drain electrode (not shown) can be maximized to the chip area of the semiconductor device, and the resistance of the wiring portion can be reduced. Further, as compared with the wiring structure shown in FIG. 7, the parasitic capacitance between the drain wiring 14 and the source wiring 13 and between the drain wiring 14 and the gate wiring can be greatly reduced. That is, a low-loss semiconductor device can be provided.
- the n + -type back conductive region 26 having a high impurity concentration is formed on the back surface of the substrate 1 by ion implantation.
- the implantation concentration is preferably 1 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 21 cm ⁇ 3 .
- the implantation depth is not particularly limited and can be determined as appropriate.
- the drain wiring 14 can be formed by the same method as in the first embodiment. Although not shown, a drain groove may be formed in the drain region 5 as in the second embodiment.
- the material of the substrate 1 is not limited to silicon carbide.
- a semiconductor having a wide band gap can be used as the material of the substrate 1. Examples of the semiconductor having a wide band gap include gallium nitride (GaN), diamond, zinc oxide (ZnO), and aluminum gallium nitride (AlGaN).
- the n-type polysilicon is used for the gate electrode 7.
- p-type polysilicon may be used.
- the gate electrode 7 may be another semiconductor material or another conductive material such as a metal material.
- a material of the gate electrode 7, for example, p-type polysilicon carbide, silicon germanium (SiGe), aluminum (Al), or the like can be used.
- a silicon oxide film is used as the gate insulating film 6
- a silicon nitride film may be used, or a silicon oxide film and a silicon nitride film may be used.
- a laminate may be used.
- isotropic etching can be performed by cleaning with hot phosphoric acid at 160 ° C., for example.
- a metal may be used, an alloy of a semiconductor and a metal, or a conductor other than that may be used.
- the metal material include nickel (Ni), titanium (Ti), (Mo), and the like.
- the method for depositing the metal material include electron beam evaporation, metal organic chemical vapor deposition (MOCVD), and sputtering.
- the alloy of the semiconductor and the metal may be nickel silicide (SiNi), tungsten silicide (SiW), titanium silicide (TiSi), or the like. Examples of a method for depositing these alloys include sputtering.
- nitrides such as titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN) can also be used.
- semiconductor material polysilicon, germanium (Ge), tin (Sn), gallium arsenide (GaAs), or the like can be used.
- n-type impurities such as phosphorus (P), arsenic (As), and antimony (Sb) or p-type impurities such as boron (B), aluminum (Al), and gallium (Ga) into these materials.
- Conductivity can be imparted.
- the MOSFET has been described as an example of the semiconductor device.
- the semiconductor device according to the embodiment of the present invention can be applied to an insulated gate bipolar transistor (IGBT) and a thyristor.
- IGBT insulated gate bipolar transistor
Abstract
Description
図1は本発明の第1の実施の形態に係る半導体装置の構成を模式的に示す斜視図である。第1の実施の形態では、半導体装置の一例として金属酸化膜半導体電界効果トランジスタ(MOSFET)を説明する。図1では分かり易くするため、電極配線は図示を省略している。また、図1では3つの半導体素子を図示しているが、これに限定されるものではなく、例えば図1のx軸方向及びz軸方向に多数の半導体素子が配列されていてもよい。
本発明の第1の実施の形態では、基板1が絶縁性又は半絶縁性基板である場合を説明したが、変形例として、基板1がドリフト領域4と同一導電型(n型)の半導体基板である場合を説明する。基板1は例えば炭化珪素からなり、基板1の不純物濃度は、ドリフト領域4の不純物濃度より低い。この場合の半導体装置の動作方法及び製造方法は、基板1が絶縁性又は半絶縁性基板である場合と実質的に同様である。
図8に、図1から変形した構造の半導体装置を示す。図8に示した半導体装置は、ソース領域3とドレイン領域5が基板1内まで延設されている点が、図1に示した半導体装置の構造と異なる。図8に示した半導体装置の製造方法は、ソース領域3とドレイン領域5を形成するイオン注入の際に、不純物をドリフト領域4の第1の主面よりも深く注入する点が本発明の第1の実施の形態と異なり、他の手順は実質的に同様である。
図9に、図8から変形した構造の半導体装置を示す。図9に示す半導体装置は、ゲート溝8が更に深く掘り下げられ、ゲート溝8の一部が基板1に入り込む点が、図8に示した半導体装置と異なる。図9に示す半導体装置の動作方法は、図8に示した半導体装置と実質的に同様である。図9に示す半導体装置の製造方法は、ゲート溝8の形成工程において、ゲート溝8をドリフト領域4の第1の主面より深く形成する点が、図8に示した半導体装置と異なり、他の手順は実質的に同様である。
図10に、図9から変形した構造の半導体装置を示す。図10に示す半導体装置は、ゲート溝8の底部がウェル領域2に入り込む点が、図9に示した半導体装置と異なる。図10に示す半導体装置の動作方法は、図9に示した半導体装置と実質的に同様である。また、図10に示す半導体装置の製造方法は、ゲート溝8の形成工程において、ゲート溝8の深さをソース領域3より深く形成する点が、図9に示した半導体装置と異なり、他の手順は実質的に同様である。
図11に、図10から変形した構造の半導体装置を示す。図11に示す半導体装置は、ゲート溝8の底部がウェル領域2より深く形成されている点が、図10に示した半導体装置と異なる。図11に示す半導体装置の製造方法は、ゲート溝8の形成工程において、ゲート溝8の深さをウェル領域2より深く形成する点が、図10に示した半導体装置と異なる。
図12は本発明の第2の実施の形態に係る半導体装置の構成を示す斜視図である。図12では分かり易くするため、電極配線の図示を省略している。電極配線の構造は図7と同様である。
本発明の第3の実施の形態は、本発明の第1の実施の形態に対して、基板1の構造を変形するものである。本発明の第3の実施の形態に係る半導体装置では、図30に示すように、基板1のドリフト領域4と接する主面とは反対側の主面(裏面)に、高不純物濃度のn+型の裏面導電領域26が形成されている。ドレイン領域5は、ドリフト領域4の第2の主面から、ドリフト領域4の第2の主面に垂直方向に裏面導電領域26まで延設されている。裏面導電領域26の基板1と接する主面とは反対側の主面(裏面)には、ドレイン配線14が電気的に接続されている。
上記のように、本発明は第1~第3の実施の形態によって記載したが、この開示の一部をなす論述及び図面はこの発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施の形態、実施例及び運用技術が明らかとなろう。
2…ウェル領域
3…ソース領域
4…ドリフト領域
5…ドレイン領域
6…ゲート絶縁膜
7…ゲート電極
8…ゲート溝
9,21,22…マスク材
10…層間絶縁膜
11…コンタクトホール
12…ゲート配線
13…ソース配線
14…ドレイン配線
15…ソース電極
16…ドレイン電極
17…ソース溝
18,24,25…導電層
19…ウェルコンタクト領域
20…ドレイン溝
23…ポリシリコン
26…裏面導電領域
Claims (24)
- 基板と、
前記基板の第1の主面に形成され、前記基板と同じ材料からなり、前記基板よりも高不純物濃度の第1導電型のドリフト領域と、
前記ドリフト領域内において、前記ドリフト領域の前記基板と接する第1の主面とは反対側の第2の主面から、前記第2の主面の垂直方向に延設され、且つ前記基板内まで端部が延設された第2導電型のウェル領域と、
前記ドリフト領域内において、前記ウェル領域と離間して、前記第2の主面から前記垂直方向に延設された第1導電型のドレイン領域と、
前記ウェル領域内において、前記第2の主面から前記垂直方向に延設された第1導電型のソース領域と、
前記第2の主面から前記垂直方向に設けられ、前記第2の主面と平行な一方向において前記ソース領域及び前記ウェル領域を貫通するように延設されたゲート溝と、
前記ゲート溝の表面にゲート絶縁膜を介して形成されたゲート電極と、
前記ソース領域及び前記ウェル領域に電気的に接続されたソース電極と、
前記ドレイン領域に電気的に接続されたドレイン電極
とを備えることを特徴とする半導体装置。 - 前記基板が第1導電型であることを特徴とする請求項1に記載の半導体装置。
- 前記基板が半絶縁性又は絶縁性であることを特徴とする請求項1に記載の半導体装置。
- 前記基板が炭化珪素からなることを特徴とする請求項1~3のいずれか1項に記載の半導体装置。
- 前記ソース領域が前記垂直方向において前記基板内まで延設されていることを特徴とする請求項1~4のいずれか1項に記載の半導体装置。
- 前記ゲート溝が前記垂直方向において前記基板内まで延設されていることを特徴とする請求項1~5のいずれか1項に記載の半導体装置。
- 前記ゲート溝が前記垂直方向において前記ソース領域より深いことを特徴とする請求項1~6のいずれか1項に記載の半導体装置。
- 前記ゲート溝が前記垂直方向において前記ウェル領域より深いことを特徴とする請求項1~7のいずれか1項に記載の半導体装置。
- 前記ドレイン領域が前記垂直方向において前記基板内まで延設されていることを特徴とする請求項1~8のいずれか1項に記載の半導体装置。
- 前記ソース領域において前記第2の主面から前記垂直方向に延設されたソース溝を更に備える特徴とする請求項1~9のいずれか1項に記載の半導体装置。
- 前記ソース溝の幅が前記ゲート溝の幅より広いことを特徴とする請求項10に記載の半導体装置。
- 前記ドレイン領域において前記第2の主面から前記垂直方向に延設されたドレイン溝を更に備えることを特徴とする請求項1~9のいずれか1項に記載の半導体装置。
- 前記ドレイン溝の幅が前記ゲート溝の幅より広いことを特徴とする請求項12に記載の半導体装置。
- 前記ソース領域において前記第2の主面から前記垂直方向に延設されたソース溝と、
前記ドレイン領域において前記第2の主面から前記垂直方向に延設されたドレイン溝
とを更に備えることを特徴とする請求項1~9のいずれか1項に記載の半導体装置。 - 前記ソース溝の幅が前記ドレイン溝の幅より広く、且つ前記ドレイン溝の幅が前記ゲート溝の幅より広いことを特徴とする請求項14に記載の半導体装置。
- 前記ソース溝の底部が前記基板と接し、
前記ソース溝の底部に前記ウェル領域と接するように形成された第2導電型のウェルコンタクト領域を更に有し、
前記ウェルコンタクト領域、前記ソース領域及び前記ウェル領域が同電位をとることを特徴とする請求項10、11、14及び15のいずれか1項に記載の半導体装置。 - 前記基板の第1の主面とは反対側の第2の主面に形成された第1導電型の裏面導電領域を更に備え、
前記ドレイン領域が前記垂直方向において前記基板を貫通して前記裏面導電領域まで延設されていることを特徴とする請求項1~16のいずれか1項に記載の半導体装置。 - 基板と、前記基板の第1の主面に形成され、前記基板と同じ材料からなり、前記基板よりも高不純物濃度の第1導電型のドリフト領域と、前記ドリフト領域内において、前記ドリフト領域の前記基板と接する第1の主面とは反対側の第2の主面から、前記第2の主面の垂直方向に延設され、且つ前記基板内まで端部が延設された第2導電型のウェル領域と、前記ドリフト領域内において、前記ウェル領域と離間して、前記第2の主面から前記垂直方向に延設された第1導電型のドレイン領域と、前記ウェル領域内において、前記第2の主面から前記垂直方向に延設された第1導電型のソース領域と、前記第2の主面から前記垂直方向に設けられ、前記第2の主面と平行な一方向において前記ソース領域及び前記ウェル領域を貫通するように延設されたゲート溝と、前記ゲート溝の表面にゲート絶縁膜を介して形成されたゲート電極と、前記ソース領域において前記第2の主面から前記垂直方向に延設されたソース溝と、前記ドレイン領域において前記第2の主面から前記垂直方向に延設されたドレイン溝と、前記ソース溝の底部に前記ウェル領域と接するように形成された第2導電型のウェルコンタクト領域とを備える半導体装置の製造方法であって、
前記基板の第1の主面に形成した前記ドリフト領域内に、前記第2の主面から前記垂直方向に、前記ゲート溝、前記ソース溝及び前記ドレイン溝を同時に形成する第1工程を含むことを特徴とする半導体装置の製造方法。 - 前記第1工程において、前記ソース溝の幅が前記ドレイン溝の幅より広く、且つ前記ドレイン溝の幅が前記ゲート溝の幅より広くなるように、前記ゲート溝、前記ソース溝及び前記ドレイン溝を形成し、
前記第1工程の後に、前記ゲート溝の幅の半分以上、且つ前記ドレイン溝の幅の半分以下の厚さで第1のマスク材を堆積する第2工程を更に含むことを特徴とする請求項18に記載の半導体装置の製造方法。 - 前記第2工程の後に、斜めイオン注入法を用いて、前記ソース溝及び前記ドレイン溝の底面及び側壁に、前記ソース領域及びドレイン領域をそれぞれ形成する第3工程を更に含むことを特徴とする請求項19に記載の半導体装置の製造方法。
- 前記第3工程の後に、前記ソース溝内に空間を残存し、且つ前記ドレイン溝を埋めるように、第2のマスク材を堆積する第4工程を更に含むことを特徴とする請求項20に記載の半導体装置の製造方法。
- 前記第4工程の後に、斜めイオン注入法を用いて前記ソース領域を囲むように前記ウェル領域を形成する第5工程を更に含むことを特徴とする請求項21に記載の半導体装置の製造方法。
- 前記第5工程の後に、垂直イオン注入法を用いて、前記ソース領域より深く且つ前記ソース領域よりも高い不純物濃度で、前記ウェルコンタクト領域を形成する第6工程を更に含むことを特徴とする請求項22に記載の半導体装置の製造方法。
- 前記第6工程において、前記ソース溝の一部の底部と接するソース領域を除去した後に、垂直イオン注入法を用いて前記ウェルコンタクト領域を形成することを特徴とする請求項23に記載の半導体装置の製造方法。
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Also Published As
Publication number | Publication date |
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EP3024018B1 (en) | 2018-08-08 |
EP3024018A1 (en) | 2016-05-25 |
JP6004109B2 (ja) | 2016-10-05 |
US20160181371A1 (en) | 2016-06-23 |
JPWO2015008550A1 (ja) | 2017-03-02 |
CN105556647B (zh) | 2017-06-13 |
CN105556647A (zh) | 2016-05-04 |
US10861938B2 (en) | 2020-12-08 |
EP3024018A4 (en) | 2017-06-07 |
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