WO2011093003A1 - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

Info

Publication number
WO2011093003A1
WO2011093003A1 PCT/JP2010/073903 JP2010073903W WO2011093003A1 WO 2011093003 A1 WO2011093003 A1 WO 2011093003A1 JP 2010073903 W JP2010073903 W JP 2010073903W WO 2011093003 A1 WO2011093003 A1 WO 2011093003A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
potential
data
electrode
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2010/073903
Other languages
English (en)
French (fr)
Inventor
Yasuyuki Takahashi
Toshihiko Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to KR1020137013992A priority Critical patent/KR101299256B1/ko
Priority to KR1020127022100A priority patent/KR101800850B1/ko
Priority to KR1020177033130A priority patent/KR101893904B1/ko
Priority to KR1020187024377A priority patent/KR101948707B1/ko
Publication of WO2011093003A1 publication Critical patent/WO2011093003A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • H10B20/25—One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/26—Floating gate memory which is adapted to be one-time programmable [OTP], e.g. containing multiple OTP blocks permitting limited update ability
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to semiconductor memory devices and to a manufacturing method thereof.
  • a semiconductor memory device also includes an external memory device (an auxiliary memory device) such as a hard disk or a flexible disk in a broad sense.
  • an auxiliary memory device such as a hard disk or a flexible disk in a broad sense.
  • a semiconductor memory device almost always refers to a semiconductor memory device such as a CPU (central processing unit).
  • a volatile memory refers to a semiconductor memory device in which data is lost when the power is turned off.
  • a nonvolatile memory is a semiconductor memory device in which data is continuously held even after power is turned off and in which data can be held semi-permanently after the data is written.
  • nonvolatile memories such as an unwritable read only memory (ROM), a flash memory in which writing and erasing can be performed multiple times, and an electronically erasable and programmable read only memory (EEPROM).
  • ROM unwritable read only memory
  • EEPROM electronically erasable and programmable read only memory
  • a write-once memory in which writing can be performed only once is preferable because data is difficult to falsify and high security can be provided in this memory.
  • An example of a write-once memory is an anti-fuse type memory in which voltage is applied to both terminals of an element formed using amorphous silicon to form silicide in the terminals and to short-circuit. Further, a rewritable memory such as a flash memory or an EEPROM is used and a memory region where erasure is not performed is provided, whereby the rewritable memory is logically used as a write-once memory in some cases (see Patent Document 1).
  • Patent Document 1 Japanese Published Patent Application No. H7-297293
  • the silicide-type write-once memory becomes in a semi-short-circuit state with high resistance (the state in which resistance is high such that data is not recognized as data 1 described later by a reading operation) due to shortage of writing voltage or the like.
  • An element which becomes a semi-short-circuit state with high resistance is a substantially defective element.
  • the silicide-type write-once memory cannot write data in a plurality of memory cells at the same time, and it is difficult to write data in many memory elements in a short time.
  • the flash memory or the EEPROM it is possible to write data in a plurality of memory cells at the same time, but the writing time is as long as approximately 100 ⁇ $.
  • an object of one embodiment of the present invention is to provide a semiconductor memory device in which high voltage is not needed in writing, a defect is less likely to occur, the writing time is short, and data cannot be rewritten without an increase in cost.
  • One embodiment of the present invention is a semiconductor memory device including a memory element which includes a diode-connected first transistor and a second transistor whose gate is connected to one terminal of a source electrode and a drain electrode of the diode-connected first transistor. Note that one terminal of a source electrode and a drain electrode of the second transistor and the one terminal of the source electrode and the drain electrode of the diode-connected first transistor form a parasitic capacitance.
  • Another embodiment of the present invention is a semiconductor memory device including a memory element which includes a diode-connected first transistor, a second transistor whose gate is connected to one terminal of a source electrode and a drain electrode of the diode-connected first transistor, and a capacitor connected to the one terminal of the source electrode and the drain electrode of the diode-connected first transistor and the gate of the second transistor.
  • a state of writing data is set.
  • the second transistor is off, that is, voltage lower than the threshold voltage is applied to the gate thereof, a state of non-writing data is set.
  • One terminal of the source electrode and the drain electrode of the diode-connected first transistor functions as an anode.
  • a channel region of the diode-connected first transistor is formed using an oxide semiconductor, whereby off-state current can be reduced to less than or equal to 1 x 10 ⁇ 19 ⁇ / ⁇ , and further, less than or equal to 1 x 10 ⁇ 20 ⁇ / ⁇ .
  • a potential of the gate of the second transistor which rises by writing of data, or the potential of the gate of the second transistor and the capacitor, which rises by writing of data, is less likely to leak from the diode-connected first transistor, and the potential of the gate of the second transistor can be held. In other words, the data which is written once can be held.
  • the writing voltage can be set to voltage with which the second transistor can be turned on, that is, greater than or equal to the threshold voltage of the second transistor, and the writing voltage can be reduced.
  • a boosting circuit for writing voltage is not necessarily provided. Power consumption in writing can be reduced, and an increase in a channel length for higher withstand voltage and formation of an LDD region are unnecessary. Therefore, the size of a memory element can be reduced, and high integration can be achieved.
  • a memory element can be formed using a transistor; therefore, writing defects can be reduced.
  • the writing time is determined by the on-state current of the diode-connected first transistor and the capacitance of the capacitor, and writing of data is finished in approximately 1 even when the on-state current of the first transistor is 10 ⁇ 6 A and the capacitance of the capacitor is 1 pF. Further, writing of data in a plurality of memory elements can be performed at the same time. Therefore, the writing time is greatly reduced.
  • the memory cell included in a semiconductor memory device of one embodiment of the present invention is a write-once memory; therefore, rewriting of data due to the malfunction of a logic circuit does not occur.
  • a rewritable memory can be formed only by modification in the wiring layout of the memory element in the write-once memory; therefore, a semiconductor memory device in which a rewritable memory and a write-once memory are combined can be formed. Accordingly, the security of holding data in the semiconductor memory device can be improved.
  • a semiconductor memory device in which high voltage is not needed in writing, a defect is less likely to occur, the writing time is short, and data cannot be rewritten can be formed without an increase in cost.
  • FIGS. 1A and IB are equivalent circuits each illustrating a semiconductor memory device according to one embodiment of the present invention.
  • FIGS. 2A and 2B are equivalent circuits each illustrating a semiconductor memory device according to one embodiment of the present invention.
  • FIG 3 is an equivalent circuit illustrating a semiconductor memory device according to one embodiment of the present invention.
  • FIGS. 4 A and 4B are equivalent circuits each illustrating a semiconductor memory device according to one embodiment of the present invention.
  • FIGS. 5A and 5B are equivalent circuits each illustrating a semiconductor memory device according to one embodiment of the present invention.
  • FIG 6 is an equivalent circuit illustrating a semiconductor memory device according to one embodiment of the present invention.
  • FIGS. 7A and 7B are equivalent circuits each illustrating a semiconductor memory device according to one embodiment of the present invention.
  • FIG 8 is an equivalent circuit illustrating a semiconductor memory device according to one embodiment of the present invention.
  • FIGS. 9 A and 9B are equivalent circuits each illustrating a semiconductor memory device according to one embodiment of the present invention.
  • FIGS. 10A and 10B are block diagrams each illustrating a semiconductor memory device according to one embodiment of the present invention.
  • FIGS. 11A and 11B are equivalent circuits each illustrating a semiconductor memory device according to one embodiment of the present invention.
  • FIGS. 12 A and 12B are equivalent circuits each illustrating a semiconductor memory device according to one embodiment of the present invention.
  • FIGS. 13A and 13B are equivalent circuits each illustrating a semiconductor memory device according to one embodiment of the present invention.
  • FIG 14 is a top view illustrating a semiconductor memory device according to one embodiment of the present invention.
  • FIG 15 is a cross-sectional view illustrating a semiconductor memory device according to one embodiment of the present invention.
  • FIGS. 16A to 16E are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to one embodiment of the present invention.
  • FIG 17 is a diagram illustrating an RFID tag.
  • FIG 18 is a diagram illustrating an RFID tag.
  • FIGS. 19A to 19F are diagrams illustrating application examples of RFID tags.
  • FIGS. 20 A to 20C are equivalent circuits used for simulation and a graph showing results thereof.
  • FIG 21 is a graph showing characteristics of a transistor including an oxide semiconductor.
  • FIG 22 is a circuit diagram for evaluating characteristics of a transistor including an oxide semiconductor.
  • FIG 23 is a timing chart for evaluating characteristics of a transistor including an oxide semiconductor.
  • FIG 24 is a graph showing characteristics of a transistor including an oxide semiconductor.
  • FIG 25 is a graph showing characteristics of a transistor including an oxide semiconductor.
  • FIG 26 is a graph showing characteristics of a transistor including an oxide semiconductor.
  • voltage refers to a potential difference between a given potential and a reference potential (e.g., a ground potential) in many cases. Accordingly, voltage, potential, and a potential difference can be referred to as potential, voltage, and a voltage difference, respectively.
  • both a source electrode and a drain electrode in a transistor are connected to a semiconductor layer. Current flows in accordance with a potential difference between the source electrode and the drain electrode when voltage is applied to a gate electrode; therefore, the source electrode and the drain electrode may be exchanged for each other depending on an operation, and it is sometimes difficult to identify where a source electrode and a drain electrode are from their positions.
  • names “source electrode” and “drain electrode” are used.
  • names “one of a source electrode and a drain electrode” and “the other of the source electrode and the drain electrode” are used.
  • names “first electrode” and “second electrode” are used. Note that there is no particular difference in meaning depending on such names.
  • a memory element which is one embodiment of the present invention is illustrated in each of FIGS. 1A and IB.
  • a memory element 101 illustrated in FIG 1A includes a diode-connected transistor 102, a transistor 103, and a capacitor 104.
  • a gate of the transistor 103 is connected to a first electrode of the capacitor 104 and a first electrode of the transistor 102.
  • a second electrode of the transistor 102 is connected to a gate of the transistor 102.
  • a connection region where the gate of the transistor 103, the first electrode of the capacitor 104, and the first electrode of the transistor 102 are connected is referred to as a node A
  • a connection region where the second electrode of the transistor 102 and the gate thereof are connected is referred to as a node B.
  • the first electrode of the diode-connected transistor 102 functions as an anode.
  • a channel region of the diode-connected transistor 102 is formed using an oxide semiconductor.
  • the transistor 102 including an oxide semiconductor in the channel region has low off-state current.
  • the transistor 102 is diode-connected, and the gate of the transistor 102 is connected to the second electrode of the transistor 102. Therefore, current flows from the node B to the node A when the transistor 102 is on; however, current which flows from the node A to the node B is extremely small when the transistor 102 is off.
  • a state in which the potential of the node A is low (that is, the transistor 103 is turned off) is data 0, whereas a state in which the potential of the node A is high (that is, the transistor 103 is turned on) is data 1.
  • the diode-connected transistor 102 is on, and the voltage which is higher than the threshold voltage of the transistor 103 is charged in the capacitor 104, that is, voltage which makes the transistor 103 turn on is applied to the node A, whereby data 1 can be written to the memory element 101.
  • the transistor 102 is turned off. Even when the potential of the node B where the gate of the transistor 102 is connected to the second electrode thereof decreases, the transistor 102 has very low off-state current and is diode-connected; therefore, current is less likely to flow from the first electrode of the transistor 102 to the second electrode thereof. Accordingly, voltage charged in the node A does not decrease, and voltage of the node A can be held for a long period of time. Consequently, written information (data 1) cannot be rewritten, and the memory element 101 can be operated as a write-once memory substantially. Note that the capacitance of the capacitor 104 is set as appropriate in accordance with the required retention time of data.
  • the capacitor 104 is not necessarily provided.
  • the memory element in that case includes the diode-connected transistor 102 and the transistor 103, and the gate of the transistor 103 is connected to the first electrode of the transistor 102, as illustrated in FIG IB.
  • the second electrode of the transistor 102 is connected to the gate of the transistor 102.
  • FIG 2A is a diagram illustrating one embodiment of a NOR memory cell array.
  • a memory cell 110 includes a memory element 111; a transistor 115 whose gate is connected to a word line WL1 for writing, whose first electrode is connected to the memory element 111, and whose second electrode is connected to a bit line BLl for writing; and a transistor 116 whose gate is connected to a word line WL2 for reading, whose first electrode is connected to a bit line BL2 for reading, and whose second electrode is connected to the memory element 111.
  • the transistor 115 functions as a selection transistor for writing, and the transistor 116 functions as a selection transistor for reading.
  • the memory element 111 includes a diode-connected transistor 112, a transistor 113, and a capacitor 114.
  • a second electrode of the transistor 112 is connected to a gate thereof and is connected to the first electrode of the transistor 115.
  • a gate of the transistor 113 is connected to a first electrode of the capacitor 114 and a first electrode of the transistor 112.
  • a first electrode of the transistor 113 is connected to the second electrode of the transistor 116, and a second electrode of the transistor 113 has a fixed potential.
  • a second electrode of the capacitor 114 also has a fixed potential.
  • FIG 2B is a diagram illustrating one embodiment of a NOR memory cell array which is different from that in FIG 2A.
  • a memory cell 130 includes a memory element 131; and a transistor 135 whose gate is connected to the word line WL1 for writing, whose first electrode is connected to the memory element 131, and whose second electrode is connected to the bit line BL1 for writing.
  • the transistor 135 functions as a selection transistor for writing.
  • the memory element 131 includes a diode-connected transistor 132, a transistor 133, and a capacitor 134.
  • a second electrode of the transistor 132 is connected to a gate thereof and is connected to the first electrode of the transistor 135.
  • a gate of the transistor 133 is connected to a first electrode of the capacitor 134 and a first electrode of the transistor 132.
  • a first electrode of the transistor 133 is connected to the bit line BL2 for reading, and a second electrode thereof has a fixed potential.
  • a second electrode of the capacitor 134 is connected to the word line WL2 for reading.
  • FIG 3 is a diagram illustrating one embodiment of a NAND memory cell array.
  • a memory cell 120 includes a memory element 121; and a transistor 125 whose gate is connected to a word line WL for writing, whose first electrode is connected to the memory element 121, and whose second electrode is connected to a bit line BL for writing.
  • the transistor 125 functions as a selection transistor for writing.
  • the memory element 121 includes a diode-connected transistor 122, a transistor 123, and a capacitor 124.
  • a second electrode of the transistor 122 is connected to a gate thereof and is connected to the first electrode of the transistor 125.
  • a gate of the transistor 123 is connected to a first electrode of the capacitor 124 and a first electrode of the transistor 122.
  • a first electrode of the transistor 123 is connected to a data line DL for reading, and a second electrode of the transistor 123 is connected to a first electrode of the transistor 123 of the next line.
  • a second electrode of the capacitor 124 has a fixed potential.
  • Channel regions of the diode-connected transistors 112, 122, and 132 are each formed using an oxide semiconductor.
  • the transistors 112, 122, and 132 each including an oxide semiconductor in the channel region have low off-state current.
  • the transistors 112, 122, and 132 are diode-connected, and the gates of the transistors 112, 122, and 132 are connected to the second electrodes of the transistors 112, 122, and 132, respectively. Therefore, current flows from the node B to the node A when the transistors 112, 122, and 132 are on; however, extremely small current flows from the node A to the node B when the transistors 112, 122, and 132 are off.
  • Each of channel regions of the transistors 113, 115, 116, 123, 125, 133, and 135 can be formed using any of an amorphous silicon layer, a micro-crystalline silicon layer, a polysilicon layer, and a single crystal silicon layer.
  • each of the channel regions of the transistors 113, 115, 116, 123, 125, 133, and 135 may be formed using an oxide semiconductor.
  • the channel region of the diode-connected first transistor is formed using an oxide semiconductor, whereby off-state current can be reduced to less than or equal to 1 x 10 -19 ⁇ / ⁇ , and further, less than or equal to 1 x 10 ⁇ 20 ⁇ / ⁇ . Therefore, the potential of the gate of the second transistor and the capacitor, which rises by writing of data, is less likely to leak from the diode-connected first transistor, and the potential of the gate of the second transistor can be held. In other words, the data which is written once can be held.
  • the data writing voltage can be set to voltage with which the second transistor can be turned on, that is, greater than or equal to the threshold voltage of the second transistor, and the writing voltage can be reduced.
  • a boosting circuit for writing voltage is not necessarily provided. Power consumption in writing can be reduced, and an increase in a channel length for higher withstand voltage and formation of an LDD region are unnecessary. Therefore, the size of a memory element can be reduced, and high integration can be achieved.
  • the writing time of the semiconductor memory device described in this embodiment is determined by the on-state current of the diode-connected first transistor and the capacitance of the capacitor, and writing of data is finished in approximately 1 in the case where the on-state current of the first transistor is 10 ⁇ 6 A and the capacitance of the capacitor is 1 pF. Further, writing of data in a plurality of memory elements can be performed at the same time. Therefore, the writing time can be greatly reduced.
  • the memory cell included in the semiconductor memory device described in this embodiment is a write-once memory; therefore, rewriting of data due to the malfunction of a logic circuit does not occur. Accordingly, the security of holding data in the semiconductor memory device can be improved.
  • the first potential is a potential at which the transistors 113 and 115 are turned on.
  • the first potential is a potential which is higher than the threshold voltage of each of the transistors 113 and 115, and is 2 V here.
  • the transistor 115 functioning as a selection transistor for writing and the diode-connected transistor 112 are turned on, so that the potential of the node A, that is, the potential of the capacitor 114 and the gate of the transistor 113, increases to approximately the same as the potential of the bit line BL1 for writing; accordingly, the transistor 113 is turned on.
  • the potential of the bit line BL1 for writing and the potential of the word line WL1 for writing are 0 V as illustrated in FIG 4B. Accordingly, although the transistor 115 functioning as a selection transistor for writing and the diode-connected transistor 112 are off, the off-state current of the transistor 112 which is formed using an oxide semiconductor is very low; therefore, the voltage of the node A is held for a long period of time. Specifically, the off-state current of the transistor 112 formed using an oxide semiconductor is less than or equal to 1 x 10 "19 A/fim, preferably less than or equal to 1 x 10 ⁇ 20 ⁇ / ⁇ .
  • to hold data here means a state in which the potential of the capacitor 114 is greater than or equal to 90 % of the potential in writing of data 1, namely, greater than or equal to 1.8 V.
  • FIG 5A illustrates a method for reading data 1
  • FIG 5B illustrates a method for reading data 0.
  • the potential of the word line WL2 for reading is changed to turn on the transistor 116 functioning as a selection transistor for reading, so that an output from a readout circuit 117 is determined in accordance with the voltage of the bit line BL2 for reading.
  • the bit line BL1 for writing and the word line WL1 for writing are each set at a ground potential in reading, and the transistors 112 and 115 are off.
  • a second potential is applied to the word line WL2 for reading which belongs to a column through which data is read, and the transistor 116 is turned on as illustrated in FIG 5 A.
  • a third potential which is a negative potential is also applied to word lines WL2 for reading which belong to columns through which data is not read.
  • the second potential is a potential at which the transistor 116 is turned on.
  • the second potential is set as a potential which is higher than the threshold voltage of the transistor 116, and is 2 V here.
  • the transistor 113 In the case of data 1, the transistor 113 is turned on; therefore, the output from the readout circuit 117 is determined by comparison between resistance of a resistor (referred to as Rl) included in the readout circuit 117 and the sum of on-resistance of the transistor 113 and on-resistance of the transistor 116.
  • Rl a resistor
  • the resistance of the resistor Rl in the readout circuit is higher than the sum of the on-resistance of the transistor 113 and the on-resistance of the transistor 116, the potential of a node C of the bit line BL2 for reading is approximately 0 V.
  • the potential of the node C is inverted by an inverter 118 included in the readout circuit 117 to be output as data 1.
  • the second potential is applied to the word line WL2 for reading, and the transistor 116 is turned on as illustrated in FIG 5B.
  • the transistor 113 is off; therefore, the output from the readout circuit 117 is determined by comparison between the resistance of the resistor Rl included in the readout circuit 117 and the sum of off-resistance of the transistor 113 and on-resistance of the transistor 116.
  • the resistance of the resistor Rl included in the readout circuit 117 is lower than the sum of the off-resistance of the transistor 113 and the on-resistance of the transistor 116, the potential of the node C of the bit line BL2 for reading is set to approximately 2 V by the readout circuit 117.
  • the potential is inverted by the inverter 118 included in the readout circuit 117 to be output as data 0.
  • the third potential which is a negative potential is applied to word lines WL2 for reading.
  • the third potential is a potential at which the transistor 116 is turned off.
  • the third potential is a negative potential which is lower than the threshold voltage of the transistor 116, and is -2 V here. The transistor 116 is turned off. Therefore, there is no possibility of reading data in the memory cells in which reading of data is not selected.
  • the first potential is applied to the bit line BLl for writing and the word line WL1 for writing which belong to the memory cell 130 in which data is written, and the word line WL2 for reading is set at a ground potential.
  • the first potential is a potential at which the transistors 133 and 135 are turned on.
  • the first potential is a potential higher than the threshold voltage of each of the transistors 133 and 135, and is 2 V here.
  • the transistor 135 and the diode-connected transistor 132 are turned on, so that electric charge is charged in the node A, that is, the capacitor 134 and the gate of the transistor 133, and the potential increases to approximately the same as the potential of the bit line BLl for writing; accordingly, the transistor 133 is turned on.
  • data 1 can be written.
  • the potential of the bit line BL1 for writing and the potential of the word line WL1 for writing are 0 V. Accordingly, although the transistor 135 functioning as a selection transistor for writing and the diode-connected transistor 132 are off, the off-state current of the transistor 132 which is formed using an oxide semiconductor is very low; therefore, the voltage of the node A is held for a long period of time. Consequently, the memory element 131 functions as a write-once memory.
  • FIG 7 A illustrates a method for reading data 1
  • FIG 7B illustrates a method for reading data 0.
  • the potential of the word line WL2 for reading is changed, and data is read in accordance with the voltage of the bit line BL2 for reading.
  • the word line WL2 for reading which belongs to a column through which data is read is set at a ground potential, and the other word lines WL2 for reading are set at the third potential which is a negative potential as illustrated in FIG 7A.
  • the word line WL2 for reading which belongs to a column through which data is read is set at a ground potential, and the other word lines WL2 for reading are set at the third potential which is a negative potential as illustrated in FIG 7B.
  • the third potential which is a negative potential is applied to the word lines WL2 for reading in the memory cells which belong to the columns through which data is not read.
  • the potential of the capacitor 134 of the memory cell is a value in which the third potential is added to the potential stored in the node A. Because the third potential is a negative potential, the potential of the capacitor 134 of the memory cell decreases, and the transistor 133 is turned off regardless of data written to the memory cell. Therefore, there is no possibility of reading data in the memory cell which is not selected for reading.
  • FIG 3 according to Embodiment 1 will be described with reference to drawings.
  • the first potential is applied to the bit line BL and the word line WL which belong to the memory cell 120 in which data is written.
  • the first potential is a potential at which the transistors 123 and 125 are turned on.
  • the second electrode of the capacitor 124, which is not connected to the transistors 123 and 125, is a ground potential.
  • the transistor 125 and the diode-connected transistor 122 are turned on, so that the potential of the node A, that is, the potential of the capacitor 124 and the gate of the transistor 123, increases to approximately the same as the potential of the bit line BL for writing; accordingly, the transistor 123 is turned on.
  • the potential of the bit line BL for writing is 0 V. Accordingly, although the transistor 125 functioning as a selection transistor for writing and the diode-connected transistor 122 are off, the off-state current of the transistor 122 which is formed using an oxide semiconductor is very low; therefore, the potential of the node A is held for a long period of time. Consequently, the memory element 121 functions as a write-once memory.
  • FIG 9A illustrates a method for reading data 1
  • FIG 9B illustrates a method for reading data 0. Reading of data is performed in such a manner that voltages are applied to all the second electrodes of the capacitor 124, which are electrodes not connected to the transistor 123 in all the memory cells connected to a given bit line, that is, in the capacitors 124 included in the memory cells 120 which are included in a region 129.
  • a ground potential is applied to the second electrode of the capacitor 124 of the memory cell which belongs to a line and in which data is read, and a fourth potential is applied to the second electrode of the capacitor 124 of the other of the memory cells included in the region 129, and an output from the readout circuit 117 is determined in accordance with the voltage of the bit line BL for reading.
  • the fourth potential is a potential which is higher than the threshold voltage of the transistor 123, and the fourth potential is 2 V here.
  • the first electrode of the capacitor 124 of the memory cell 120 in which data is read is 0 V as illustrated in FIG 9B. Therefore, the transistor 123 of the memory cell in which data is read is off.
  • the potential of the first electrode of the capacitor 124 increases, whereby the transistor 123 is turned on.
  • the potential of the node C of the data line DL is set to approximately 2 V by the readout circuit 117.
  • a semiconductor memory device in which high voltage is not needed in writing, a defect is less likely to occur, the writing time is short, and data cannot be rewritten can be provided.
  • FIG 10A is an example of a semiconductor memory device including the memory cell array described in Embodiment 1.
  • a semiconductor memory device 300 includes a memory cell array 301, a column decoder 302, a row decoder 303, and an interface circuit 304.
  • the memory cell array 301 includes a plurality of memory cells 305 arranged in matrix.
  • the interface circuit 304 generates signals for driving the column decoder 302 and the row decoder 303 from external signals and outputs data which is read from the memory cell 305 to the outside.
  • the column decoder 302 receives a signal for driving the memory cell 305 from the interface circuit 304 and generates a signal for writing or reading which is to be transmitted to a bit line.
  • the row decoder 303 receives a signal for driving the memory cell 305 from the interface circuit 304 and generates a signal for writing or reading which is to be transmitted to a word line. With the signal which is to be output to the bit line from the column decoder 302 and the signal which is to be output to the word line from the row decoder 303, the memory cell which performs access in the memory cell array 301 is uniquely determined.
  • a semiconductor memory device 310 illustrated in FIG 10B includes a first memory cell array 311, a second memory cell array 312, the column decoder 302, the row decoder 303, and the interface circuit 304.
  • memory cells 313 each having the write-once memory described in Embodiment 1 and Embodiment 2 are arranged in matrix.
  • memory cells 314 each having a rewritable memory element are arranged in matrix.
  • the rewritable memory element can be formed by the same process as that of the write-once memory described in Embodiment 1 and Embodiment 2.
  • the structure of the rewritable memory element is described with reference to FIG llA and FIG 11B.
  • FIG 11A is a diagram illustrating a memory cell having a rewritable memory element of NOR type and a memory cell array.
  • a memory cell 400 includes a memory element 401; a transistor 402 whose gate is connected to the word line WL1 for writing, whose first electrode is connected to the memory element 401, and whose second electrode is connected to the bit line BL1 for writing; and a transistor 406 whose gate is connected to the word line WL2 for reading, whose first electrode is connected to the bit line BL2 for reading, and whose second electrode is connected to the memory element 401.
  • the transistor 406 functions as a selection transistor for reading.
  • the memory element 401 includes a transistor 403 and a capacitor 404.
  • a gate of the transistor 403 is connected to a first electrode of the capacitor 404 and the first electrode of the transistor 402.
  • a first electrode of the transistor 403 is connected to the second electrode of the transistor 406, and a second electrode of the transistor 403 has a fixed potential.
  • a second electrode of the capacitor 404 also has a fixed potential.
  • the transistor 402 is formed using an oxide semiconductor in a manner similar to that of the transistor 102 described in Embodiment 1.
  • the transistors 403 and 406 can be formed in a manner similar to that of the transistor 103 described in Embodiment 1.
  • FIG 12A illustrates a method for writing data 1
  • FIG 12B illustrates a method for writing data 0.
  • the first potential is applied to the bit line BL1 for writing and the word line WLl for writing which are connected to the memory cell 400 in which data is written, and the word line WL2 for reading has a ground potential.
  • the first potential is a potential at which the transistors 402 and 403 are turned on and which is higher than the threshold voltage of each of the transistors 402 and 403, and is 2 V here.
  • the bit line BL1 for writing which is connected to the memory cell 400 in which data is written has a ground potential
  • the first potential is applied to the word line WLl for writing
  • the word line WL2 for reading has a ground potential.
  • the first potential is a potential at which the transistor 402 is turned on and which is higher than the threshold voltage of the transistor 402, and is 2 V here.
  • the transistor 402 When the potential of the word line WL1 for writing is the first potential, the transistor 402 is turned on, and the potential of the node A, that is, the potential of the capacitor 404 and the potential of the gate of the transistor 403 decreases to a potential of the bit line BL1 for writing which is a ground potential. Thus, the transistor 403 is turned off, and data 0 can be written. Note that to prevent unintended reading of data, the word line WL2 for reading is made to have a ground potential and the transistor 406 is turned off in a writing period.
  • FIG 13A illustrates a method for reading data 1
  • FIG. 13B illustrates a method for reading data 0.
  • the potential of the word line WL2 for reading is changed, the transistor 406 functioning as a selection transistor for reading is turned on, and an output from the readout circuit 117 is determined in accordance with the voltage of the bit line BL2 for reading.
  • the second potential is applied to the word line WL2 for reading which belongs to a line through which data is read, and the transistor 406 is turned on.
  • the transistor 403 is on; therefore, the node C of the bit line BL2 for reading has a ground potential in a manner similar to that of the reading method of the write-once memory element of NOR type illustrated in FIG 2A according to Embodiment 2.
  • the potential of the node C is inverted by the inverter included in the readout circuit 117 and is output as data 1.
  • the second potential is applied to the word line WL2 for reading, and the transistor 406 is turned on.
  • the transistor 403 is off; therefore, the bit line BL2 for reading is set to approximately 2 V by the readout circuit 117.
  • the potential is inverted by the inverter included in the readout circuit 117 and is output as data 0.
  • the third potential which is a negative potential is applied to the word line WL2 for reading.
  • the third potential is a potential at which the transistor 406 is turned off and a negative potential that is lower than the threshold voltage of the transistor 406, and is -2 V here.
  • the transistor 406 is turned off. Therefore, there is no possibility of reading data in the memory cell in which reading of data is not selected.
  • FIG 11B is a diagram illustrating a memory cell including a rewritable memory element of NOR type which is different from the memory cell in FIG 11 A.
  • the memory cell illustrated in FIG 11B has a structure including a transistor 405 between the transistor 402 and the bit line BL1 for writing which are illustrated in FIG 11 A.
  • a connection of the gate of the transistor 112 described in Embodiment 1 is changed, and the gate is merely connected to the word line WL1 for writing.
  • the write-once memory can be replaced with the rewritable memory or the rewritable memory can be replaced with the write-once memory. Since a method for writing data and a method for reading data are in common with FIG 11 A, these are omitted.
  • the write-once memory and the rewritable memory element are of NOR type; however, a NAND type can be used as appropriate.
  • the write-once memory and the rewritable memory can be provided on the same semiconductor memory device.
  • the rewritable memory can be formed by the same process as that of the write-once memory described in Embodiment 1 and Embodiment 2, and the write-once memory can be used as a write-once memory and the rewritable memory can be used as a rewritable memory without depending on the operation by a logic signal. Therefore, it is possible to provide a semiconductor memory device in which rewriting of data due to malfunction of a logic circuit does not occur in principle.
  • Embodiments 1 to 3 a structure of the semiconductor memory device described in Embodiments 1 to 3 and a manufacturing method thereof are described with reference to FIG 14, FIG 15, and FIGS. 16Ato 16E.
  • Embodiment 1 the structure of the semiconductor memory device described in Embodiment 1 is described using a top view and a cross-sectional view, and the structure can be applied to Embodiment 2 and Embodiment 3, as appropriate.
  • FIG 14 is one embodiment of a top view of the memory cell 110 in the semiconductor memory device described in Embodiment 1, and a cross-sectional view taken along lines A-B, C-D, and E-F of FIG 14 is illustrated in FIG 15.
  • a transistor 502 illustrated in FIG 14 corresponds to the transistor 113 illustrated in FIG. 2A
  • a transistor 503 corresponds to the transistor 116 illustrated in FIG 2A
  • a diode-connected transistor 505 corresponds to the diode-connected transistor 112 illustrated in FIG 2 A
  • a transistor 506 corresponds to the transistor 115 illustrated in FIG 2 A.
  • a capacitor 504 corresponds to the capacitor 114 illustrated in FIG 2A.
  • transistors are n-channel transistors here, it is needless to say that p-channel transistors can be used. Further, the technical nature of the present invention disclosed herein is to form a channel region of the diode-connected transistor
  • a specific structure of a semiconductor memory device is not necessarily limited to the structure described herein.
  • the transistor 502 and the capacitor 504 are provided over an insulating layer 510 and an insulating layer 512 which are stacked over a substrate 508; the transistor 505 is provided over the insulating layer 510, the insulating layer 512, an insulating layer 536, an insulating layer 538, and an insulating layer 540 which are stacked.
  • the semiconductor memory device described in this embodiment includes the transistor 502, the transistor 503 (not illustrated), the capacitor 504, and the transistor
  • capacitor 506 (not illustrated) in the lower part, and the diode-connected transistor 505 in the upper part. Note that the capacitor 504 may be provided in the upper part instead of in the lower part but.
  • the transistor 502 includes a semiconductor layer 519 formed over the insulating layer 512, a gate insulating layer 522 provided over the semiconductor layer 519, a gate electrode 526 provided over the gate insulating layer 522, and wirings 534a and 534b which are electrically connected to the semiconductor layer 519.
  • the semiconductor layer 519 is formed with a channel region 514, and low-concentration impurity regions 516 and high-concentration impurity regions 518 (these are also collectively referred to simply as impurity regions) which are provided so as to sandwich the channel region 514.
  • a sidewall insulating layer 530 is provided on a side surface of the gate electrode 526. Further, the sidewall insulating layer 530 overlaps with the low-concentration impurity regions 516.
  • the capacitor 504 includes a semiconductor layer 520 which is formed over the insulating layer 512 and with a high-concentration impurity region, a gate insulating layer 524 provided over the semiconductor layer 520, a capacitor electrode 528 provided over the gate insulating layer 524, a wiring 534c electrically connected to the semiconductor layer 520, and the wiring 534b connected to the capacitor electrode 528.
  • a sidewall insulating layer 532 is provided on a side surface of the capacitor electrode 528.
  • the insulating layer 536, the insulating layer 538, and the insulating layer 540 are provided so as to cover the transistor 502 and the capacitor 504.
  • the diode-connected transistor 505 includes an oxide semiconductor layer 542 electrically connected to the wiring 534c and a wiring 534d which are provided over the insulating layer 540; a gate insulating layer 544 covering the wiring 534c, the wiring 534d, and the oxide semiconductor layer 542; and a gate electrode 546a which is provided over the gate insulating layer 544 and which overlaps with the oxide semiconductor layer 542. Further, the gate electrode 546a seals an opening formed in the gate insulating layer 544, and the gate electrode 546a is electrically connected to the wiring 534d to be diode-connected.
  • An insulating layer 552 and an insulating layer 554 are provided so as to cover the transistor 505.
  • a wiring 546b functioning as a ground wiring and the wiring 546b is electrically connected to the wiring 534a of the transistor 502 through an opening formed in the gate insulating layer 544.
  • the capacitor electrode 528 is electrically connected to the wiring 534a; therefore, the capacitor electrode 528 of the capacitor 504 is electrically connected to the wiring 546b.
  • the wiring 534a is electrically connected to the high-concentration impurity region 518 and the capacitor electrode 528 of the capacitor 504 through openings formed in the insulating layer 536, the insulating layer 538, and the insulating layer 540.
  • the wiring 534b is electrically connected to the high-concentration impurity region 518 through an opening formed in the insulating layer 536, the insulating layer 538, and the insulating layer 540.
  • the wiring 534c is electrically connected to the semiconductor layer 520 which is a high-concentration impurity semiconductor and the gate electrode 526 (see FIG 14) of the transistor 502 through openings formed in the insulating layer 536, the insulating layer 538, and the insulating layer 540.
  • the wiring 534d is electrically connected to a high-concentration impurity region of the transistor 506 through an opening formed in the insulating layer 536, the insulating layer 538, and the insulating layer 540, and is electrically connected to the oxide semiconductor layer 542 of the transistor 505.
  • a wiring 534e is electrically connected to the high-concentration impurity region of the transistor 506 through an opening formed in the insulating layer 536, the insulating layer 538, and the insulating layer 540.
  • a wiring 534f is electrically connected to a high-concentration impurity region of the transistor 503 through an opening formed in the insulating layer 536, the insulating layer 538, and the insulating layer 540.
  • the substrate 508 have at least heat resistance high enough to withstand heat treatment performed later.
  • a glass substrate whose strain point is higher than or equal to 730 °C is preferably used.
  • a glass material such as aluminosilicate glass, aluminoborosilicate glass, or barium borosilicate glass is used, for example.
  • a glass substrate containing BaO and B 2 0 3 so that the amount of BaO is larger than that of B 2 0 3 is preferably used.
  • a substrate formed of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate can be used.
  • crystallized glass or the like may be used.
  • a semiconductor substrate such as a silicon wafer, whose surface is provided with an insulating layer, or a conductive substrate formed of a metal material, whose surface is provided with an insulating layer can be used.
  • a plastic substrate can be used. Note that in the case where a plastic substrate is used for the substrate 508, an adhesive agent may be provided between the substrate 508 and the insulating layer 510.
  • the insulating layer 510 is preferably formed using a nitride insulating layer, and the insulating layer 512 is preferably formed using an oxide insulating layer.
  • the nitride insulating layer there are a silicon nitride layer, a silicon nitride oxide layer, an aluminum nitride layer, and the like.
  • the oxide insulating layer there are a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, and the like.
  • the semiconductor layer 519 of the transistor 502 and the semiconductor layer 520 of the capacitor 504, which is a high-concentration impurity semiconductor, can be formed using an amorphous silicon layer, a microcrystalline silicon layer, a polycrystalline silicon layer, or a single crystal silicon layer.
  • a transistor in which a single crystal silicon layer is used for a channel region in addition to a transistor in which a single crystal semiconductor substrate is used for a channel region, a transistor formed using a so-called silicon-on-insulator (SOI) substrate in which a single crystal silicon layer used for a channel region is formed on an insulating region can be employed.
  • the semiconductor layer 519 of the transistor 502 may be formed using an oxide semiconductor layer which is similar to an oxide semiconductor layer in the diode-connected transistor 505 to be described.
  • the gate insulating layer 522 and the gate insulating layer 524 can be formed in a single layer or a stacked layer using a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer.
  • the gate insulating layer 522 and the gate insulating layer 524 may be formed using a high-k material such as hafnium silicate (HfSiO x ), hafnium silicate to which nitrogen is added hafnium aluminate to which nitrogen is added (HfAl x O y N z ), hafnium oxide, or yttrium oxide, whereby gate leakage current can be reduced.
  • a stacked structure in which a high-k material and one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, and an aluminum oxide layer are stacked can be used.
  • the thickness of each of the gate insulating layer 522 and the gate insulating layer 524 can be greater than or equal to 10 nm and less than or equal to 300 nm.
  • the gate electrode 526 and the capacitor electrode 528 can be formed using a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten; an alloy containing any of these metal elements as a component; an alloy containing these metal elements in combination; or the like. Further, one or more metal elements selected from manganese, magnesium, zirconium, and beryllium may be used. Further, each of the gate electrode 526 and the capacitor electrode 528 may have a single-layer structure or a stacked structure of two or more layers.
  • a single-layer structure of an aluminum layer containing silicon there are a single-layer structure of an aluminum layer containing silicon; a two-layer structure in which a titanium layer is stacked over an aluminum layer; a two-layer structure in which a titanium layer is stacked over a titanium nitride layer; a two-layer structure in which a tungsten layer is stacked over a titanium nitride layer; a two-layer structure in which a tungsten layer is stacked over a tantalum nitride layer; and a three-layer structure in which a titanium layer, an aluminum layer, and a titanium layer are stacked in that order.
  • a layer, an alloy layer, or a nitride layer which contains aluminum and one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.
  • the gate electrode 526 and the capacitor electrode 528 can be formed using a light-transmitting conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added.
  • the gate electrode 526 and the capacitor electrode 528 can have a stacked structure having a layer containing the above light-transmitting conductive material and a layer containing the above metal element.
  • the sidewall insulating layer 530 and the sidewall insulating layer 532 can be formed using a material similar to that of the gate insulating layer 522 and the gate insulating layer 524. Note that a sidewall insulating layer is not formed in some cases for integration of the transistor and the capacitor.
  • the insulating layer 536 and the insulating layer 540 can be formed in a manner similar to that of the gate insulating layer 522 and the gate insulating layer 524.
  • the insulating layer 538 can be formed using an organic resin layer. Examples of the organic resin layer include acrylic, epoxy, polyimide, polyamide, polyvinylphenol, and benzocyclobutene. Alternatively, a siloxane polymer can be used.
  • the wirings 534a to 534f can be formed using a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten; an alloy containing any of these metal elements as a component; an alloy containing these metal elements in combination; or the like. Further, one or more metal elements selected from manganese, magnesium, zirconium, and beryllium may be used. Further, each of the wirings 534a to 534f may have a single-layer structure or a stacked structure of two or more layers.
  • a single-layer structure of an aluminum layer containing silicon there are a single-layer structure of an aluminum layer containing silicon; a two-layer structure in which a titanium layer is stacked over an aluminum layer; a two-layer structure in which a titanium layer is stacked over a titanium nitride layer; a two-layer structure in which a tungsten layer is stacked over a titanium nitride layer; a two-layer structure in which a tungsten layer is stacked over a tantalum nitride layer; and a three-layer structure in which a titanium layer, an aluminum layer, and a titanium layer are stacked in that order.
  • a layer, an alloy layer, or a nitride layer which contains aluminum and one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.
  • the wirings 534a to 534f can be formed using a light-transmitting conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added. It is also possible to have a stacked structure having a layer containing the above light-transmitting conductive material and a layer containing the above metal element.
  • transistor 505 and the transistor 506 can each have a structure which is similar to the structure of the transistor 502.
  • an oxide semiconductor layer using any of the folio wings can be used: a four-component metal oxide such as an In-Sn-Ga-Zn-O-based metal oxide; a three-component metal oxide such as an In-Ga-Zn-O-based metal oxide, an In-Sn-Zn-O-based metal oxide, an In-Al-Zn-O-based metal oxide, a Sn-Ga-Zn-O-based metal oxide, an Al-Ga-Zn-O-based metal oxide, or a Sn-Al-Zn-O-based metal oxide; or a two-component metal oxide such as an In-Zn-O-based metal oxide, a Sn-Zn-O-based metal oxide, an Al-Zn-O-based metal oxide, a Zn-Mg-O-based metal oxide, a Sn-Mg-O-based metal oxide, or an In-Mg-O-based metal oxide.
  • a four-component metal oxide such as an In-
  • an n-component metal oxide includes an oxide of n kinds of metals.
  • the oxide semiconductor may contain, as an impurity, an element other than the metal oxide that is the main component at less than or equal to 1 %, preferably at less than or equal to 0.1 %.
  • M represents one or more elements selected from the elements of Group 13 such as gallium (Ga), aluminum (Al), and boron (B).
  • Ga gallium
  • Al aluminum
  • B boron
  • the contents of In and Zn are not zero.
  • the above-described expression includes In-Ga-Zn-O-based metal oxide, In-Zn-O-based metal oxide, and the like.
  • the energy gap of the metal oxide which forms the oxide semiconductor layer 542 is 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more.
  • an oxide semiconductor with an amorphous structure, a microcrystalline structure, a polycrystalline structure, or a single crystal structure can be used as appropriate.
  • an oxide semiconductor having a crystal in which the c-axis is approximately parallel to a direction which is perpendicular to a surface of the oxide semiconductor can be used.
  • concentration be less than or equal to 1 x 10 /cm .
  • the carrier density can be obtained by the Hall effect measurement.
  • Lower carrier density can be obtained from the measurement results of capacitance-voltage (CV) measurement.
  • the hydrogen concentration in the oxide semiconductor layer can be measured by secondary ion mass spectrometry (SIMS).
  • the i-type or substantially i-type oxide semiconductor layer 542 is used for a channel region of the transistor 505, and the off-state current of the transistor 505 can be less than or equal to 1 x 10 " ⁇ / ⁇ , further less than or equal to 1 x 10 "" ⁇ / ⁇ .
  • the i-type or substantially i-type oxide semiconductor layer has a wide band gap and requires a large amount of thermal energy for electronic excitation; therefore, direct recombination and indirect recombination are less likely to occur.
  • the number of holes which are minority carriers is substantially zero in a state where a negative potential is applied to a gate electrode (i.e., in an off state); accordingly, direct recombination and indirect recombination are less likely to occur, and the amount of current is very small.
  • a circuit can be designed with the oxide semiconductor layer that can be considered as an insulator in a state where the transistor is in a non-conducting state (also referred to as an OFF state).
  • the transistor 505 serves as a normally-off transistor with very low leakage current in an off state, and has excellent switching characteristics.
  • a material used for the gate insulating layer 522 and the gate insulating layer 524 can be used as appropriate. Note that in the case where the gate insulating layer 544 has a stacked structure, a layer on a side which is in contact with the oxide semiconductor layer 542 is formed using an oxide insulating layer, whereby oxygen can be supplied to the oxygen deficiency included in the oxide semiconductor layer 542, and the oxide semiconductor layer 542 can be made to be an i-type or substantially i-type oxide semiconductor layer.
  • the insulating layer 552 and the insulating layer 554 can be formed in a manner similar to that of the insulating layer 536, the insulating layer 538, or the insulating layer 540.
  • a channel region of the diode-connected transistor 505 is formed using an i-type or substantially i-type oxide semiconductor layer; thus, off-state current can be extremely reduced. Therefore, voltage applied to the capacitor 504 can be held for a long time.
  • FIGS. 16A to 16E a manufacturing process of the transistor 505 in the semiconductor memory device illustrated in FIG 15 is described with reference to FIGS. 16A to 16E. Note that a known manufacturing process of a transistor may be employed as appropriate for each manufacturing process of the transistor 502, the transistor 503, and the transistor 506.
  • the wiring 534c and the wiring 534d which function as a source electrode and a drain electrode of the transistor 505 are formed over the insulating layer 540.
  • the insulating layer 540 can be formed by a sputtering method, a CVD method, a printing method, a coating method, or the like.
  • the dense high-quality insulating layer 540 having high withstand voltage can be formed by high-density plasma-enhanced CVD using microwaves (e.g., a frequency of 2.45 GHz).
  • microwaves e.g., a frequency of 2.45 GHz.
  • a close contact between an oxide semiconductor layer and the high-quality gate insulating layer 540 can reduce interface states and produce desirable interface characteristics.
  • the insulating layer 540 formed by the high-density plasma-enhanced CVD can have a uniform thickness, the insulating layer 540 has excellent step coverage.
  • the thickness of the insulating layer 540 formed using the high-density plasma-enhanced CVD can be controlled precisely.
  • the i-type or substantially i-type oxide semiconductor layer is extremely sensitive to an interface state or interface charge; therefore, formation of the insulating layer 540 by the high density plasma-enhanced CVD using microwaves can reduce interface states and produce desirable interface characteristics.
  • the substrate 508 is heated when the insulating layer 540 is formed, whereby the amount of hydrogen, water, a hydroxyl group, hydride, or the like included in the insulating layer 540 can be reduced.
  • the insulating layer 540 is preferably formed while hydrogen, water, a hydroxyl group, hydride, or the like remaining in a treatment chamber is removed in order to reduce the amount of hydrogen, water, a hydroxyl group, hydride, or the like included in the insulating layer 540.
  • an entrapment vacuum pump in order to remove hydrogen, water, a hydroxyl group, hydride, or the like remaining in the treatment chamber.
  • Typical examples of entrapment vacuum pumps are a cryopump, an ion pump, and a titanium sublimation pump.
  • a turbo pump provided with a cold trap can be used as the evacuation unit.
  • the purity of the sputtering gas used in forming the insulating layer 540 is preferably 6N (99.9999 %) or higher, more preferably 7N (99.99999 %) or higher (that is, the concentration of the impurities is 1 ppm or lower, preferably 0.1 ppm or lower), whereby the amount of hydrogen, water, a hydroxyl group, hydride, or the like included in the insulating layer 540 can be reduced.
  • the wiring 534c and the wiring 534d are formed using a printing method, an ink-jet method, or the like, whereby the number of steps can be reduced.
  • a conductive layer is formed over the insulating layer 540 by a sputtering method, a CVD method, an evaporation method, or the like, the conductive layer is etched using, as a mask, a resist formed in a photolithography process, whereby the wiring 534c and the wiring 534d can be formed.
  • an oxide semiconductor layer 541 is formed over the insulating layer 540, the wiring 534c, and the wiring 534d.
  • the oxide semiconductor layer 541 can be formed by a printing method, an ink-jet method, or the like.
  • an oxide semiconductor layer is formed over the insulating layer 540 by a sputtering method, a CVD method, a coating method, a pulsed laser evaporation method, or the like, and the oxide semiconductor layer is etched using, as a mask, a resist formed in a photolithography process, whereby the island-shaped oxide semiconductor layer 541 can be formed.
  • the carrier density of the oxide semiconductor layer depends on the hydrogen concentration in a source gas and a target under deposition conditions and the oxygen concentration therein, a material to be deposited and the composition thereof, heat treatment conditions, and the like.
  • the hydrogen concentration in the oxide semiconductor layer is decreased or the oxygen concentration in the oxide semiconductor layer is increased to reduce oxygen deficiencies, whereby the oxide semiconductor layer is made to be an i-type or substantially i-type oxide semiconductor layer.
  • the oxide semiconductor layer 541 since treatment by which the oxide semiconductor layer is made to be i-type or substantially i-type is performed later, the oxide semiconductor layer 541 may be either an i-type oxide semiconductor layer or an n-type oxide semiconductor layer.
  • the substrate is heated, whereby impurities such as hydrogen, water, a hydroxyl group, or hydride included in the oxide semiconductor layer can be reduced. Further, in the first heat treatment, crystal growth can be promoted.
  • the relative density of a metal oxide in the metal oxide target is set to greater than or equal to 80 %, preferably greater than or equal to 95 %, more preferably greater than or equal to 99.9 %. Accordingly, the impurity concentration in the oxide semiconductor layer can be reduced, and a transistor which has excellent electrical characteristics or high reliability can be obtained.
  • the oxide semiconductor layer when preheat treatment is performed before the oxide semiconductor layer is formed, hydrogen, water, a hydroxyl group, hydride, or the like which remains on the inner wall of the sputtering apparatus, on a surface of a target, or inside a target material can be removed. Accordingly, impurities such as hydrogen, water, a hydroxyl group, or hydride included in the oxide semiconductor layer can be reduced.
  • an entrapment vacuum pump is preferably used so as to remove hydrogen, water, a hydroxyl group, hydride, or the like remaining in the sputtering apparatus. Accordingly, hydrogen, water, a hydroxyl group, hydride, or the like is removed, whereby the concentration of hydrogen, water, a hydroxyl group, hydride, or the like included in the oxide semiconductor layer can be reduced.
  • the first heat treatment is performed, and impurities such as hydrogen, water, a hydroxyl group, or hydride included in the oxide semiconductor layer 541 are removed. That is, at least one of dehydration and dehydrogenation can be performed. Note that in the first heat treatment, an oxygen deficiency is formed in the oxide semiconductor layer 541.
  • the temperature of the first heat treatment is higher than or equal to 400 °C and lower than or equal to 750 °C, preferably higher than or equal to 400 °C and lower than the strain point of the substrate.
  • the heat treatment apparatus for the first heat treatment is not limited to a particular apparatus, and the apparatus may be provided with a device for heating an object to be processed by heat radiation or heat conduction from a heating element such as a resistance heating element.
  • a heating element such as a resistance heating element.
  • an electric furnace, or a rapid thermal annealing (RTA) apparatus such as a gas rapid thermal annealing (GRTA) apparatus or a lamp rapid thermal annealing (LRTA) apparatus can be used as the heat treatment apparatus.
  • RTA rapid thermal annealing
  • GRTA gas rapid thermal annealing
  • LRTA lamp rapid thermal annealing
  • An LRTA apparatus is an apparatus for heating an object to be processed by radiation of light (an electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp.
  • a GRTA apparatus is an apparatus for heat treatment using a high-temperature gas.
  • hydrogen, water, a hydroxyl group, hydride, or the like be not contained in nitrogen or a rare gas such as helium, neon, or argon.
  • the purity of nitrogen or a rare gas such as helium, neon, or argon introduced into a heat treatment apparatus is preferably 6N (99.9999 %) or higher, more preferably 7N (99.99999 %) or higher (that is, the concentration of the impurities is 1 ppm or lower, preferably 0.1 ppm or lower).
  • an atmosphere in a furnace may be a nitrogen atmosphere, and the atmosphere may be switched to an oxygen atmosphere at the time of performing cooling.
  • oxygen can be supplied into the oxide semiconductor layer, so that the hydrogen concentration can be reduced and oxygen can be supplied to the oxygen deficiency formed in the oxide semiconductor layer; accordingly, an i-type or substantially i-type oxide semiconductor layer can be formed.
  • the oxide semiconductor layer might be crystallized to be an oxide semiconductor layer including crystals.
  • the oxide semiconductor layer having a crystal in which the c-axis is approximately parallel to a direction which is perpendicular to a surface is formed in a superficial portion of the amorphous oxide semiconductor layer in some cases.
  • the substrate is introduced into an electric furnace, and heat treatment is performed in an inert gas atmosphere, such as a nitrogen atmosphere or a rare gas atmosphere, at 450 °C for one hour.
  • an inert gas atmosphere such as a nitrogen atmosphere or a rare gas atmosphere
  • the gate insulating layer 544 is formed.
  • the gate insulating layer 544 can be formed in a manner similar to that of the insulating layer 540. Note that when a silicon oxide layer is formed as the gate insulating layer 544 by a sputtering method, oxygen can be supplied from the silicon oxide layer to the oxygen deficiency which is included in the oxide semiconductor layer 541 and is generated by the first heat treatment, the oxygen deficiency which contributes to the formation of a donor can be reduced, and a structure which satisfies a stoichiometric mixture ratio can be formed. As a result, the i-type or substantially i-type oxide semiconductor layer 542 can be formed. A close contact between the oxide semiconductor layer and the high-quality insulating layer 540 can reduce interface states and produce desirable interface characteristics.
  • the i-type or substantially i-type oxide semiconductor layer is extremely sensitive to an interface state or interface charge; therefore, formation of the insulating layer 540 by the high density plasma-enhanced CVD using microwaves can reduce interface states and produce desirable interface characteristics.
  • second heat treatment (preferably, at a temperature higher than or equal to 200 °C and lower than or equal to 400 °C, for example, at a temperature higher than or equal to 250 °C and lower than or equal to 350 °C) is preferably performed in an inert gas atmosphere or in an oxygen gas atmosphere.
  • the second heat treatment may be performed after a protective insulating layer or a planarization insulating layer is formed over the gate insulating layer 544.
  • oxygen can be supplied from the oxide insulating layer of the gate insulating layer 544 to the oxygen deficiency which is included in the oxide semiconductor layer and is generated by the first heat treatment, the oxygen deficiency which contributes to the formation of a donor can be reduced, and a structure which satisfies a stoichiometric mixture ratio can be formed.
  • the i-type or substantially i-type oxide semiconductor layer 542 can be formed.
  • the second heat treatment is performed at 250 °C for 1 hour in a nitrogen atmosphere.
  • the gate electrode 546a is formed over the gate insulating layer 544 and the wiring 534d.
  • a transistor in which the gate electrode 546a and the wiring 534d are diode-connected can be formed.
  • the gate electrode 546a can be formed in a manner similar to that of the wiring 534c and the wiring 534d.
  • the insulating layer 552 and the insulating layer 554 are formed over the gate insulating layer 544 and the gate electrode 546a.
  • heat treatment may be performed at a temperature higher than or equal to 100 °C and lower than or equal to 200 °C for more than or equal to 1 hour and less than or equal to 30 hours in the air. With the heat treatment, reliability of the transistor can be improved.
  • the oxide semiconductor layer 541 is formed after the wiring 534c and the wiring 534d are formed; however, the wiring 534c and the wiring 534d may be formed after the oxide semiconductor layer 541 is formed over the insulating layer 540.
  • a structure may be employed in which the gate electrode 546a is formed over the insulating layer 540, the gate insulating layer 544 is formed over the gate electrode 546a, the oxide semiconductor layer 541 is formed over the gate insulating layer 544, and wirings functioning as a source electrode and a drain electrode are formed over the oxide semiconductor layer 541.
  • one of the wirings functioning as a source electrode and a drain electrode is electrically connected to the wiring 534c. Further, the other of the wirings functioning as a source electrode and a drain electrode is electrically connected to the gate electrode 546a.
  • the transistor 505 in which a channel region includes the i-type or substantially i-type oxide semiconductor layer and which has very low off-state current can be formed.
  • a circuit illustrated in FIG 17 is an RFID tag.
  • Radio frequency identification RFID: non-contact automatic identification technique using radio frequency
  • RFID has features such as capability of reading stored information without contact, operation without a battery, and superiority in durability and weatherability.
  • the reason why operation is possible without a battery is a radio wave (including an operation instruction or the like) received by an antenna included in the RFID tag is rectified in a circuit, so that power can be generated.
  • a memory to which data can be written or rewritten by a user is frequently provided in order to improve its function.
  • An RFID tag 1520 includes an antenna circuit 1521 and a signal processing circuit 1522.
  • the signal processing circuit 1522 includes a rectifier circuit 1523, a power supply circuit 1524, a demodulation circuit 1525, an oscillator circuit 1526, a logic circuit 1527, a memory control circuit 1528, a memory circuit 1529, a logic circuit 1530, an amplifier 1531, and a modulation circuit 1532.
  • the memory circuit 1529 includes the semiconductor memory device of any of the above embodiments.
  • Communication signals received by the antenna circuit 1521 are input into the demodulation circuit 1525.
  • the frequency of the communication signal received that is, the frequency of a signal transmitted and received between the antenna circuit 1521 and a reader/writer is, for example, 13.56 MHz, 915 MHz, or 2.45 GHz in UHF (ultra high frequency) band, which is determined on the basis of the ISO standards or the like.
  • the frequency of a signal transmitted and received between the antenna circuit 1521 and the reader/writer is not limited to this, and for example, any of the following frequencies can be used: 300 GHz to 3 THz which is a submillimeter wave, 30 GHz to 300 GHz which is a millimeter wave, 3 GHz to 30 GHz which is a microwave, 300 MHz to 3 GHz which is an ultra high frequency, and 30 MHz to 300 MHz which is a very high frequency.
  • a signal transmitted and received between the antenna circuit 1521 and the reader/writer is a signal obtained by modulating a carrier wave.
  • a carrier wave is modulated by analog modulation or digital modulation, and any of amplitude modulation, phase modulation, frequency modulation, and spread spectrum may be used.
  • amplitude modulation or frequency modulation is used.
  • An oscillation signal output from the oscillator circuit 1526 is supplied as a clock signal to the logic circuit 1527.
  • the carrier wave which has been modulated is demodulated in the demodulation circuit 1525.
  • the demodulated signal is transmitted to the logic circuit 1527 and analyzed.
  • the signal analyzed in the logic circuit 1527 is transmitted to the memory control circuit 1528.
  • the memory control circuit 1528 controls the memory circuit 1529, extracts data stored in the memory circuit 1529, and transmits the data to the logic circuit 1530.
  • the signal sent to the logic circuit 1530 is amplified by the amplifier 1531 after being encoded by the logic circuit 1530.
  • the modulation circuit 1532 modulates a carrier wave. By the modulated carrier wave, the reader/writer recognizes a signal from the RFID tag 1520.
  • a carrier wave input to the rectifier circuit 1523 is rectified and input to the power supply circuit 1524.
  • Power supply voltage obtained in this manner is supplied from the power supply circuit 1524 to the demodulation circuit 1525, the oscillator circuit 1526, the logic circuit 1527, the memory control circuit 1528, the memory circuit 1529, the logic circuit 1530, the amplifier 1531, the modulation circuit 1532, and the like.
  • a connection between the signal processing circuit 1522 and the antenna in the antenna circuit 1521 is not specifically limited.
  • the antenna and the signal processing circuit 1522 are connected by wire bonding or bump connection.
  • the signal processing circuit 1522 is formed to have a chip shape and one surface thereof is used as an electrode and attached to the antenna.
  • the signal processing circuit 1522 and the antenna can be attached to each other by the use of an anisotropic conductive film (ACF).
  • ACF anisotropic conductive film
  • the antenna is either stacked over the same substrate as the signal processing circuit 1522, or formed as an external antenna. Needless to say, the antenna is provided on the above or below of the signal processing circuit.
  • the rectifier circuit 1523 converts AC signals that are induced by carrier waves received by the antenna circuit 1521 into DC signals.
  • the RFID tag 1520 may include a battery 1581 as illustrated in FIG 18.
  • the battery 1581 also supplies power supply voltage to each circuit of the signal processing circuit 1522, such as the demodulation circuit 1525, the oscillator circuit 1526, the logic circuit 1527, the memory control circuit 1528, the memory circuit 1529, the logic circuit 1530, the amplifier 1531, and the modulation circuit 1532.
  • Surplus voltage of the power supply voltage output from the rectifier circuit 1523 may be charged in the battery 1581.
  • an antenna circuit and a rectifier circuit are provided in the RFID tag in addition to the antenna circuit 1521 and the rectifier circuit 1523, energy stored in the battery 1581 can be obtained from electromagnetic waves and the like that are generated randomly.
  • Electric power is charged in the battery, whereby the RFID tag can be continuously used.
  • a battery formed into a sheet form can be used.
  • a lithium polymer battery that includes a gel electrolyte, a lithium ion battery, a lithium secondary battery, or the like, a reduction in the size of the battery can be realized.
  • a nickel-hydrogen battery, a nickel-cadmium battery, a capacitor having high capacitance, or the like can be used as the battery.
  • the RFID tag 1520 can be employed for a wide range of uses and can be used by being provided for bills, coins, securities, bearer bonds, certificates (driver's licenses, resident cards, and the like; see FIG 19A), recording media (DVD software, video tapes, and the like; see FIG 19B), containers for wrapping objects (wrapping paper, bottles, and the like; see FIG 19C), vehicles (bicycles and the like; see FIG 19D), personal belongings (bags, glasses, and the like), foods, plants, animals, human bodies, clothes, daily necessities, or products such as electronic devices (liquid crystal display devices, EL display devices, television units, mobile phones, and the like); tags of each product (see FIGS. 19E and 19F); or the like.
  • the RFID tag 1520 is fixed to a product by being mounted on a printed board, attached to a surface of the product, or embedded in the product.
  • the RFID tag 1520 is incorporated in paper of a book or an organic resin package to be fixed to each object. Since the RFID tag 1520 can be reduced in size, thickness, and weight, it can be fixed to a product without spoiling the design of the product. Further, bills, coins, securities, bearer bonds, documents, or the like can have an identification function by being provided with the RFID tag 1520, and the identification function can be utilized to prevent counterfeiting.
  • the RFID tag of the present invention when attached to containers for wrapping objects, recording media, personal belongings, foods, clothes, daily necessities, electronic devices, or the like, a system such as an inspection system can be efficiently used. Vehicles can also have higher security against theft or the like by being provided with the RFID tag 1520.
  • FIGS. 20A to 20C Circuit diagrams for simulation and the results thereof are illustrated in FIGS. 20A to 20C.
  • a circuit illustrated in FIG 20A is the memory element which is one embodiment of the present invention, and the circuit includes a diode-connected transistor 601, a transistor 602, and a capacitor 603.
  • a circuit for simulation which is equivalent to this circuit is illustrated in FIG 20B.
  • the circuit illustrated in FIG 20B includes a resistor 611, a transistor 612, a capacitor 613, a resistor 614, and a resistor 615.
  • the resistor 611 is equivalent to the diode-connected transistor 601 in an off state, and the resistor 614 shows a gate leakage component of the transistor 612, and the resistor 615 shows a leakage component between electrodes of the capacitor 613.
  • the resistance value of the resistor 611 was seen as a value of the off-state current of the diode-connected transistor 601 whose channel region was formed using an oxide semiconductor layer.
  • the resistance value of the resistor 611 was a value of the off-state current of the diode-connected transistor 601 whose channel region was not formed using an oxide semiconductor layer.
  • the condition 1 2 x 10 20 ⁇ (in terms of off-state current, 10 ⁇ 20 A);
  • Each of the resistance value of the resistor 614 and the resistance value of the resistor 615 was assumed to be 10 times as large as that of the resistor 611.
  • FIG 20C shows the simulation results.
  • FIG 20C is a graph in which the horizontal axis represents elapsed time and the vertical axis represents the voltage of the node A.
  • the retention time of data 1 under the condition 3 was 176.3 ⁇ 8, while the retention time of data 1 under the condition 1 was 17.63 x 10 6 s (approximately 200 days) and the retention time of data 1 under the condition 2 was 1.763 x 10 6 s (approximately 20 days).
  • the channel region of the diode-connected transistor 601 is formed using an oxide semiconductor layer, data 1 can be held for a significantly long period or time.
  • FIG 21 shows the results obtained by measuring the off-state current of the transistor with a channel width Woi 1 m.
  • the horizontal axis represents a gate voltage VG and the vertical axis represents a drain current ID.
  • the drain voltage VD is +l V or +lO V and the gate voltage VG is within the range of -5 V to -20 V, the off-state current of the transistor
  • the off-state current of the transistor in which the i-type or substantially i-type oxide semiconductor layer was used more accurately is less than or equal to 1 x lO -12 A.
  • the results obtained by measuring more accurate off-state current (the value less than or equal to the detection limit of measurement equipment in the above measurement), with the use of an element for characteristic evaluation, will be described.
  • the measurement system 800 includes a capacitor 802, a transistor 804, a transistor 805, a transistor 806, and a transistor 808.
  • the transistor in which the i-type or substantially i-type oxide semiconductor layer was used for the channel region was used as each of the transistors 804, 805, and 806.
  • one of a source terminal and a drain terminal of the transistor 804, one of terminals of the capacitor 802, and one of a source terminal and a drain terminal of the transistor 805 are connected to a power source (for supplying V2).
  • the other of the source terminal and the drain terminal of the transistor 804, one of a source terminal and a drain terminal of the transistor 808, the other of the terminals of the capacitor 802, and a gate terminal of the transistor 805 are connected to one another.
  • the other of the source terminal and the drain terminal of the transistor 808, one of a source terminal and a drain terminal of the transistor 806, and a gate terminal of the transistor 806 are connected to a power source (for supplying VI).
  • the other of the source terminal and the drain terminal of the transistor 805 and the other of the source terminal and the drain terminal of the transistor 806 are connected to each other, and the node serves as an output terminal Vout.
  • a potential Vext_b2 for controlling an on state and an off state of the transistor 804 is supplied to a gate terminal of the transistor 804.
  • a potential Vext bl for controlling an on state and an off state of the transistor 808 is supplied to a gate terminal of the transistor 808.
  • a potential Vout is output from the output terminal.
  • the potential Vext bl for turning on the transistor 808 is input to the gate terminal of the transistor 808, and the potential VI is supplied to the node A that is a node connected to the other of the source terminal and the drain terminal of the transistor 804 (that is, the node connected to one of the source terminal and the drain terminal of the transistor 808, the other of the terminals of the capacitor 802, and the gate terminal of the transistor 805).
  • the potential VI is set to, for example, high.
  • the transistor 804 is off.
  • the potential Vext bl for turning off the transistor 808 is input to the gate terminal of the transistor 808, so that the transistor 808 is turned off.
  • the potential VI is set to low.
  • the transistor 804 is off.
  • the potential V2 is the same as the potential VI.
  • the initialization period is completed.
  • a potential difference is generated between the node A and one of the source terminal and the drain terminal of the transistor 804.
  • a potential difference is generated between the node A and the other of the source terminal and the drain terminal of the transistor 808. Accordingly, a small amount of electric charge flows through the transistor 804 and the transistor 808. That is, the off-state current is generated.
  • the potential (that is, V2) of one of the source terminal and the drain terminal of the transistor 804 and the potential (that is, VI) of the other of the source terminal and the drain terminal of the transistor 808 are fixed to be low.
  • the potential of the node A is not fixed (the node A is in a floating state) in the measurement period. Accordingly, electric charge flows through the transistor 804, and the amount of electric charge stored in the node A varies as time passes.
  • the potential of the node A varies depending on the variation in the amount of electric charge stored in the node A. In other words, the output potential Vout of the output terminal also varies.
  • FIG 23 illustrates details of the relation between potentials in the initialization period in which the potential difference is applied and in the following measurement period (timing chart).
  • the potential Vext_b2 is set to a potential (high potential) at which the transistor 804 is turned on.
  • the potential of the node A comes to be V2, that is, a low potential (VSS).
  • the potential Vext_b2 is set to a potential (low potential) at which the transistor 804 is turned off, whereby the transistor 804 is turned off.
  • the potential Vext bl is set to a potential (high potential) at which the transistor 808 is turned on.
  • the potential of the node A comes to be VI, that is, a high potential (VDD).
  • the potential Vext bl is set to a potential at which the transistor 808 is turned off. Accordingly, the node A is brought into a floating state and the initialization period is completed.
  • the potential VI and the potential V2 are individually set to potentials at which electric charge flow to or from the node A.
  • the potential VI and the potential V2 are low potentials (VSS). Note that at the timing of measuring the output potential Vout, it is necessary to operate an output circuit; thus, VI is set to a high potential (VDD) temporarily in some cases.
  • VDD high potential
  • the amount of electric charge stored in the node A varies as time passes, which changes the potential of the node A.
  • the potential of the gate terminal of the transistor 805 varies; thus, the output potential Vout of the output terminal also varies as time passes.
  • V A F(Vout)
  • Electric charge QA of the node A can be expressed by the following equation with the use of the potential VA of the node A, capacitance CA connected to the node A, and a constant (const).
  • the capacitance CA connected to the node A is the sum of the capacitance of the capacitor 802 and other capacitance.
  • the current LA of the node A can be obtained from the capacitance CA connected to the node A and the output potential Vout of the output terminal.
  • leakage current off-state current
  • the transistor 804, the transistor 805, the transistor 806, and the transistor 808 were fabricated using a highly purified oxide semiconductor with a channel length L of 10 ⁇ and a channel width W of 50 ⁇ .
  • capacitance values of capacitors 802a, 802b, and 802c were 100 fF, lpF, and 3pF, respectively.
  • the potential VI was basically set to VSS and set to VDD only in a period of 100 msec every 10 to 300 seconds, and Vout was measured. Further, At which was used in calculation of current / which flowed through the element was approximately 30000 sec.
  • FIG 24 shows the relation between elapsed time Time and the output potential Vout in the current measurement. According to FIG 24, the potential varies as time passes.
  • FIG 25 shows the off-state current at room temperature (25 °C) calculated based on the above current measurement.
  • FIG 25 shows the relation between a source-drain voltage V and an off-state current /. According to FIG 25, it is found that the off-state current was approximately 40 ⁇ / ⁇ under the condition that the source-drain voltage was 4 V. In addition, it is found that the off-state current was less than or equal to 10 ⁇ / ⁇ under the condition that the source-drain voltage was 3.1 V. Note that 1 zA represents 10 -21 A.
  • FIG 26 shows the off-state current in an environment at a temperature of 85 °C, which was calculated based on the above current measurement.
  • FIG 26 shows the relation between the source-drain voltage V and the off-state current / in an environment at a temperature of 85 °C. According to FIG 26, it is found that the off-state current was less than or equal to 100 ⁇ / ⁇ under the condition that the source-drain voltage was 3.1 V.
  • the off-state current can be sufficiently low in the transistor in which the i-type or substantially i-type oxide semiconductor layer was used for the channel region.
  • the off-state current is also sufficiently low in the diode-connected transistors 102, 112, 122, and 132 in each of which the i-type or substantially i-type oxide semiconductor layer is used for the channel region as described in Embodiments 1 to 3.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
  • Dram (AREA)
  • Non-Volatile Memory (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
PCT/JP2010/073903 2010-01-29 2010-12-28 Semiconductor memory device Ceased WO2011093003A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020137013992A KR101299256B1 (ko) 2010-01-29 2010-12-28 반도체 기억 장치
KR1020127022100A KR101800850B1 (ko) 2010-01-29 2010-12-28 반도체 기억 장치
KR1020177033130A KR101893904B1 (ko) 2010-01-29 2010-12-28 반도체 기억 장치
KR1020187024377A KR101948707B1 (ko) 2010-01-29 2010-12-28 반도체 기억 장치

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010-019386 2010-01-29
JP2010019386 2010-01-29

Publications (1)

Publication Number Publication Date
WO2011093003A1 true WO2011093003A1 (en) 2011-08-04

Family

ID=44319002

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2010/073903 Ceased WO2011093003A1 (en) 2010-01-29 2010-12-28 Semiconductor memory device

Country Status (5)

Country Link
US (1) US8507907B2 (enExample)
JP (13) JP2011176294A (enExample)
KR (4) KR101800850B1 (enExample)
TW (1) TWI538169B (enExample)
WO (1) WO2011093003A1 (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9817032B2 (en) 2012-05-23 2017-11-14 Semiconductor Energy Laboratory Co., Ltd. Measurement device
US10158026B2 (en) 2012-04-13 2018-12-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device including oxide semiconductor stacked layers
US12206370B2 (en) 2019-06-28 2025-01-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device including high frequency amplifier circuit, electronic component, and electronic device
US12336224B2 (en) 2011-11-25 2025-06-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BR9205972A (pt) 1991-05-06 1994-08-02 Ivhs Technologies Inc Sistema de radar do veículo, filtro de persistência e ambiência de alvo, circuito de desacentuação de espectro de doppler e processo para desacentuar o espectro de doppler geral
CN102742001B (zh) 2010-02-05 2017-03-22 株式会社半导体能源研究所 半导体装置
WO2011096277A1 (en) 2010-02-05 2011-08-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of driving semiconductor device
CN102725842B (zh) 2010-02-05 2014-12-03 株式会社半导体能源研究所 半导体器件
WO2011096264A1 (en) * 2010-02-05 2011-08-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of driving semiconductor device
JP5923248B2 (ja) 2010-05-20 2016-05-24 株式会社半導体エネルギー研究所 半導体装置
US8582348B2 (en) 2010-08-06 2013-11-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for driving semiconductor device
US8422272B2 (en) 2010-08-06 2013-04-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and driving method thereof
JP5727892B2 (ja) 2010-08-26 2015-06-03 株式会社半導体エネルギー研究所 半導体装置
US8922236B2 (en) 2010-09-10 2014-12-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor memory device and method for inspecting the same
US8767443B2 (en) 2010-09-22 2014-07-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor memory device and method for inspecting the same
US9048142B2 (en) 2010-12-28 2015-06-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP6001900B2 (ja) * 2011-04-21 2016-10-05 株式会社半導体エネルギー研究所 信号処理回路
JP6013682B2 (ja) 2011-05-20 2016-10-25 株式会社半導体エネルギー研究所 半導体装置の駆動方法
JP6091083B2 (ja) 2011-05-20 2017-03-08 株式会社半導体エネルギー研究所 記憶装置
US8575993B2 (en) 2011-08-17 2013-11-05 Broadcom Corporation Integrated circuit with pre-heating for reduced subthreshold leakage
US8802493B2 (en) * 2011-09-13 2014-08-12 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of oxide semiconductor device
WO2013042562A1 (en) * 2011-09-22 2013-03-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US20130082764A1 (en) * 2011-09-30 2013-04-04 Broadcom Corporation Apparatus and method to combine pin functionality in an integrated circuit
JP5888929B2 (ja) * 2011-10-07 2016-03-22 株式会社半導体エネルギー研究所 半導体装置
TWI536388B (zh) * 2012-01-12 2016-06-01 Sharp Kk Semiconductor memory circuits and devices
US9208826B2 (en) * 2012-03-30 2015-12-08 Sharp Kabushiki Kaisha Semiconductor storage device with two control lines
WO2013153853A1 (ja) * 2012-04-12 2013-10-17 シャープ株式会社 半導体記憶装置
JP6250955B2 (ja) 2012-05-25 2017-12-20 株式会社半導体エネルギー研究所 半導体装置の駆動方法
US9104708B2 (en) * 2012-09-07 2015-08-11 Magnet Systems, Inc. Managing activities over time in an activity graph
US9318484B2 (en) * 2013-02-20 2016-04-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2014195243A (ja) 2013-02-28 2014-10-09 Semiconductor Energy Lab Co Ltd 半導体装置
JP6405100B2 (ja) * 2013-03-08 2018-10-17 株式会社半導体エネルギー研究所 半導体装置
JP6068748B2 (ja) * 2013-03-13 2017-01-25 株式会社半導体エネルギー研究所 半導体装置
US9612795B2 (en) 2013-03-14 2017-04-04 Semiconductor Energy Laboratory Co., Ltd. Data processing device, data processing method, and computer program
JP6357363B2 (ja) * 2013-06-26 2018-07-11 株式会社半導体エネルギー研究所 記憶装置
US9349418B2 (en) 2013-12-27 2016-05-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for driving the same
SG11201606647PA (en) * 2014-03-14 2016-09-29 Semiconductor Energy Lab Co Ltd Circuit system
WO2016079639A1 (ja) * 2014-11-20 2016-05-26 株式会社半導体エネルギー研究所 半導体装置、回路基板および電子機器
JP6689062B2 (ja) 2014-12-10 2020-04-28 株式会社半導体エネルギー研究所 半導体装置
US9633710B2 (en) * 2015-01-23 2017-04-25 Semiconductor Energy Laboratory Co., Ltd. Method for operating semiconductor device
US10008502B2 (en) 2016-05-04 2018-06-26 Semiconductor Energy Laboratory Co., Ltd. Memory device
US10685983B2 (en) 2016-11-11 2020-06-16 Semiconductor Energy Laboratory Co., Ltd. Transistor, semiconductor device, and electronic device
KR20220003115A (ko) 2019-06-24 2022-01-07 엘지전자 주식회사 루마 맵핑 및 크로마 스케일링 기반 비디오 또는 영상 코딩
JP6753986B2 (ja) * 2019-07-04 2020-09-09 株式会社半導体エネルギー研究所 半導体装置
EP4006005A4 (en) 2019-07-24 2025-01-01 Osaka University Alkane dehydrogenation catalyst, and hydrogen production method using same
JP7583722B2 (ja) 2019-08-09 2024-11-14 株式会社半導体エネルギー研究所 記憶装置
DE102020133486B4 (de) 2020-05-28 2024-08-29 Taiwan Semiconductor Manufacturing Co. Ltd. Nichtflüchtiger speicher mit doppelter ansteuerung
US11716862B2 (en) 2020-05-28 2023-08-01 Taiwan Semiconductor Manufacturing Company, Ltd. Non-volatile memory with dual gated control
KR102868054B1 (ko) * 2021-01-14 2025-10-01 삼성전자주식회사 전원 변조기 및 이를 포함하는 무선 통신 장치

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1084092A (ja) * 1996-09-09 1998-03-31 Toshiba Corp 半導体集積回路
JPH11126491A (ja) * 1997-08-20 1999-05-11 Fujitsu Ltd 半導体記憶装置
JP2001028443A (ja) * 1999-05-13 2001-01-30 Hitachi Ltd 半導体装置およびその製造方法
JP2002082656A (ja) * 2000-09-06 2002-03-22 Hitachi Ltd 画像表示装置およびその駆動方法
JP2002538572A (ja) * 1999-02-22 2002-11-12 インフィネオン テクノロジーズ アクチエンゲゼルシャフト 自己増幅型ダイナミックメモリセルを具備したメモリセル装置の駆動方法
JP2002368226A (ja) * 2001-06-11 2002-12-20 Sharp Corp 半導体装置、半導体記憶装置及びその製造方法、並びに携帯情報機器
JP2007103918A (ja) * 2005-09-06 2007-04-19 Canon Inc アモルファス酸化物膜をチャネル層に用いた電界効果型トランジスタ、アモルファス酸化物膜をチャネル層に用いた電界効果型トランジスタの製造方法及びアモルファス酸化物膜の製造方法
JP2008042067A (ja) * 2006-08-09 2008-02-21 Canon Inc 酸化物半導体膜のドライエッチング方法

Family Cites Families (137)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0053878B1 (en) 1980-12-08 1985-08-14 Kabushiki Kaisha Toshiba Semiconductor memory device
JPS628396A (ja) * 1985-07-03 1987-01-16 Hitachi Ltd 情報保持回路
US4763181A (en) 1986-12-08 1988-08-09 Motorola, Inc. High density non-charge-sensing DRAM cell
JPH088342B2 (ja) * 1989-11-27 1996-01-29 三菱電機株式会社 半導体集積回路装置
JP2775040B2 (ja) 1991-10-29 1998-07-09 株式会社 半導体エネルギー研究所 電気光学表示装置およびその駆動方法
JP3227917B2 (ja) * 1993-07-26 2001-11-12 ソニー株式会社 増幅型ｄｒａｍ用メモリセルおよびその製造方法
JP3501416B2 (ja) 1994-04-28 2004-03-02 忠弘 大見 半導体装置
JPH08147968A (ja) * 1994-09-19 1996-06-07 Mitsubishi Electric Corp ダイナミックメモリ
US5691935A (en) * 1995-07-13 1997-11-25 Douglass; Barry G. Memory element and method of operation thereof
DE69635107D1 (de) 1995-08-03 2005-09-29 Koninkl Philips Electronics Nv Halbleiteranordnung mit einem transparenten schaltungselement
JPH09162304A (ja) * 1995-12-12 1997-06-20 Mitsubishi Electric Corp 半導体記憶装置
JP3625598B2 (ja) 1995-12-30 2005-03-02 三星電子株式会社 液晶表示装置の製造方法
JP4103968B2 (ja) 1996-09-18 2008-06-18 株式会社半導体エネルギー研究所 絶縁ゲイト型半導体装置
JP4170454B2 (ja) 1998-07-24 2008-10-22 Ｈｏｙａ株式会社 透明導電性酸化物薄膜を有する物品及びその製造方法
JP4040215B2 (ja) 1999-07-19 2008-01-30 株式会社東芝 不揮発性半導体メモリの制御方法
TW527604B (en) 1998-10-05 2003-04-11 Toshiba Corp A memory systems
JP2000150861A (ja) 1998-11-16 2000-05-30 Tdk Corp 酸化物薄膜
JP3276930B2 (ja) 1998-11-17 2002-04-22 科学技術振興事業団 トランジスタ及び半導体装置
TW461096B (en) * 1999-05-13 2001-10-21 Hitachi Ltd Semiconductor memory
JP3327250B2 (ja) 1999-05-14 2002-09-24 日本電気株式会社 半導体記憶装置
TW460731B (en) 1999-09-03 2001-10-21 Ind Tech Res Inst Electrode structure and production method of wide viewing angle LCD
JP4089858B2 (ja) 2000-09-01 2008-05-28 国立大学法人東北大学 半導体デバイス
KR20020038482A (ko) 2000-11-15 2002-05-23 모리시타 요이찌 박막 트랜지스터 어레이, 그 제조방법 및 그것을 이용한표시패널
JP3997731B2 (ja) 2001-03-19 2007-10-24 富士ゼロックス株式会社 基材上に結晶性半導体薄膜を形成する方法
JP2002289859A (ja) 2001-03-23 2002-10-04 Minolta Co Ltd 薄膜トランジスタ
US6768668B2 (en) 2001-06-12 2004-07-27 Infineon Technologies Aktiengesellschaft Converting volatile memory to non-volatile memory
JP3925839B2 (ja) 2001-09-10 2007-06-06 シャープ株式会社 半導体記憶装置およびその試験方法
JP4090716B2 (ja) 2001-09-10 2008-05-28 雅司 川崎 薄膜トランジスタおよびマトリクス表示装置
JP4498669B2 (ja) 2001-10-30 2010-07-07 株式会社半導体エネルギー研究所 半導体装置、表示装置、及びそれらを具備する電子機器
US7061014B2 (en) 2001-11-05 2006-06-13 Japan Science And Technology Agency Natural-superlattice homologous single crystal thin film, method for preparation thereof, and device using said single crystal thin film
JP4164562B2 (ja) 2002-09-11 2008-10-15 独立行政法人科学技術振興機構 ホモロガス薄膜を活性層として用いる透明薄膜電界効果型トランジスタ
JP2002319682A (ja) * 2002-01-04 2002-10-31 Japan Science & Technology Corp トランジスタ及び半導体装置
JP4083486B2 (ja) 2002-02-21 2008-04-30 独立行政法人科学技術振興機構 ＬｎＣｕＯ（Ｓ，Ｓｅ，Ｔｅ）単結晶薄膜の製造方法
US7049190B2 (en) 2002-03-15 2006-05-23 Sanyo Electric Co., Ltd. Method for forming ZnO film, method for forming ZnO semiconductor layer, method for fabricating semiconductor device, and semiconductor device
JP3933591B2 (ja) 2002-03-26 2007-06-20 淳二 城戸 有機エレクトロルミネッセント素子
CN1452180A (zh) * 2002-04-15 2003-10-29 力旺电子股份有限公司 串接电容以增加崩溃抵抗力的闪速存储器充电电路
US7339187B2 (en) 2002-05-21 2008-03-04 State Of Oregon Acting By And Through The Oregon State Board Of Higher Education On Behalf Of Oregon State University Transistor structures
JP2004022625A (ja) 2002-06-13 2004-01-22 Murata Mfg Co Ltd 半導体デバイス及び該半導体デバイスの製造方法
US7105868B2 (en) 2002-06-24 2006-09-12 Cermet, Inc. High-electron mobility transistor with zinc oxide
US7067843B2 (en) 2002-10-11 2006-06-27 E. I. Du Pont De Nemours And Company Transparent oxide semiconductor thin film transistors
JP4166105B2 (ja) 2003-03-06 2008-10-15 シャープ株式会社 半導体装置およびその製造方法
JP2004273732A (ja) 2003-03-07 2004-09-30 Sharp Corp アクティブマトリクス基板およびその製造方法
JP4108633B2 (ja) 2003-06-20 2008-06-25 シャープ株式会社 薄膜トランジスタおよびその製造方法ならびに電子デバイス
US7262463B2 (en) 2003-07-25 2007-08-28 Hewlett-Packard Development Company, L.P. Transistor including a deposited channel region having a doped portion
US7282782B2 (en) 2004-03-12 2007-10-16 Hewlett-Packard Development Company, L.P. Combined binary oxide semiconductor device
US7297977B2 (en) 2004-03-12 2007-11-20 Hewlett-Packard Development Company, L.P. Semiconductor device
US7145174B2 (en) 2004-03-12 2006-12-05 Hewlett-Packard Development Company, Lp. Semiconductor device
EP2413366B1 (en) 2004-03-12 2017-01-11 Japan Science And Technology Agency A switching element of LCDs or organic EL displays
US7211825B2 (en) 2004-06-14 2007-05-01 Yi-Chi Shih Indium oxide-based thin film transistors and circuits
JP2006100760A (ja) 2004-09-02 2006-04-13 Casio Comput Co Ltd 薄膜トランジスタおよびその製造方法
US7285501B2 (en) 2004-09-17 2007-10-23 Hewlett-Packard Development Company, L.P. Method of forming a solution processed device
KR100670134B1 (ko) * 2004-10-08 2007-01-16 삼성에스디아이 주식회사 전류 구동형 디스플레이 소자의 데이터 구동 장치
US7298084B2 (en) 2004-11-02 2007-11-20 3M Innovative Properties Company Methods and displays utilizing integrated zinc oxide row and column drivers in conjunction with organic light emitting diodes
CN101057339B (zh) 2004-11-10 2012-12-26 佳能株式会社 无定形氧化物和场效应晶体管
US7791072B2 (en) 2004-11-10 2010-09-07 Canon Kabushiki Kaisha Display
JP5053537B2 (ja) * 2004-11-10 2012-10-17 キヤノン株式会社 非晶質酸化物を利用した半導体デバイス
US7453065B2 (en) 2004-11-10 2008-11-18 Canon Kabushiki Kaisha Sensor and image pickup device
US7863611B2 (en) * 2004-11-10 2011-01-04 Canon Kabushiki Kaisha Integrated circuits utilizing amorphous oxides
CA2585063C (en) 2004-11-10 2013-01-15 Canon Kabushiki Kaisha Light-emitting device
US7868326B2 (en) 2004-11-10 2011-01-11 Canon Kabushiki Kaisha Field effect transistor
US7829444B2 (en) 2004-11-10 2010-11-09 Canon Kabushiki Kaisha Field effect transistor manufacturing method
US7579224B2 (en) 2005-01-21 2009-08-25 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a thin film semiconductor device
TWI445178B (zh) 2005-01-28 2014-07-11 半導體能源研究所股份有限公司 半導體裝置，電子裝置，和半導體裝置的製造方法
TWI562380B (en) 2005-01-28 2016-12-11 Semiconductor Energy Lab Co Ltd Semiconductor device, electronic device, and method of manufacturing semiconductor device
US7858451B2 (en) 2005-02-03 2010-12-28 Semiconductor Energy Laboratory Co., Ltd. Electronic device, semiconductor device and manufacturing method thereof
US7948171B2 (en) 2005-02-18 2011-05-24 Semiconductor Energy Laboratory Co., Ltd. Light emitting device
US20060197092A1 (en) 2005-03-03 2006-09-07 Randy Hoffman System and method for forming conductive material on a substrate
US8681077B2 (en) 2005-03-18 2014-03-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, and display device, driving method and electronic apparatus thereof
WO2006105077A2 (en) 2005-03-28 2006-10-05 Massachusetts Institute Of Technology Low voltage thin film transistor with high-k dielectric material
US7645478B2 (en) 2005-03-31 2010-01-12 3M Innovative Properties Company Methods of making displays
US8300031B2 (en) * 2005-04-20 2012-10-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising transistor having gate and drain connected through a current-voltage conversion element
JP4999351B2 (ja) * 2005-04-20 2012-08-15 株式会社半導体エネルギー研究所 半導体装置及び表示装置
JP2006344849A (ja) 2005-06-10 2006-12-21 Casio Comput Co Ltd 薄膜トランジスタ
US7691666B2 (en) 2005-06-16 2010-04-06 Eastman Kodak Company Methods of making thin film transistors comprising zinc-oxide-based semiconductor materials and transistors made thereby
US7402506B2 (en) 2005-06-16 2008-07-22 Eastman Kodak Company Methods of making thin film transistors comprising zinc-oxide-based semiconductor materials and transistors made thereby
US7507618B2 (en) 2005-06-27 2009-03-24 3M Innovative Properties Company Method for making electronic devices using metal oxide nanoparticles
KR100711890B1 (ko) 2005-07-28 2007-04-25 삼성에스디아이 주식회사 유기 발광표시장치 및 그의 제조방법
JP2007059128A (ja) 2005-08-23 2007-03-08 Canon Inc 有機ｅｌ表示装置およびその製造方法
JP5116225B2 (ja) 2005-09-06 2013-01-09 キヤノン株式会社 酸化物半導体デバイスの製造方法
JP4850457B2 (ja) 2005-09-06 2012-01-11 キヤノン株式会社 薄膜トランジスタ及び薄膜ダイオード
JP2007073705A (ja) 2005-09-06 2007-03-22 Canon Inc 酸化物半導体チャネル薄膜トランジスタおよびその製造方法
JP4280736B2 (ja) 2005-09-06 2009-06-17 キヤノン株式会社 半導体素子
JP5064747B2 (ja) 2005-09-29 2012-10-31 株式会社半導体エネルギー研究所 半導体装置、電気泳動表示装置、表示モジュール、電子機器、及び半導体装置の作製方法
EP3614442A3 (en) 2005-09-29 2020-03-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having oxide semiconductor layer and manufactoring method thereof
JP5037808B2 (ja) 2005-10-20 2012-10-03 キヤノン株式会社 アモルファス酸化物を用いた電界効果型トランジスタ、及び該トランジスタを用いた表示装置
KR101117948B1 (ko) 2005-11-15 2012-02-15 가부시키가이샤 한도오따이 에네루기 켄큐쇼 액정 디스플레이 장치 제조 방법
TWI292281B (en) 2005-12-29 2008-01-01 Ind Tech Res Inst Pixel structure of active organic light emitting diode and method of fabricating the same
US7867636B2 (en) 2006-01-11 2011-01-11 Murata Manufacturing Co., Ltd. Transparent conductive film and method for manufacturing the same
JP4977478B2 (ja) 2006-01-21 2012-07-18 三星電子株式会社 ＺｎＯフィルム及びこれを用いたＴＦＴの製造方法
US7576394B2 (en) 2006-02-02 2009-08-18 Kochi Industrial Promotion Center Thin film transistor including low resistance conductive thin films and manufacturing method thereof
US7977169B2 (en) 2006-02-15 2011-07-12 Kochi Industrial Promotion Center Semiconductor device including active layer made of zinc oxide with controlled orientations and manufacturing method thereof
KR20070101595A (ko) 2006-04-11 2007-10-17 삼성전자주식회사 ＺｎＯ ＴＦＴ
TWI325165B (en) 2006-04-20 2010-05-21 Ememory Technology Inc Method for operating a single-poly single-transistor non-volatile memory cell
US20070252928A1 (en) 2006-04-28 2007-11-01 Toppan Printing Co., Ltd. Structure, transmission type liquid crystal display, reflection type display and manufacturing method thereof
JP4614148B2 (ja) * 2006-05-25 2011-01-19 富士電機ホールディングス株式会社 酸化物半導体及び薄膜トランジスタの製造方法
WO2007142167A1 (en) * 2006-06-02 2007-12-13 Kochi Industrial Promotion Center Semiconductor device including an oxide semiconductor thin film layer of zinc oxide and manufacturing method thereof
JP5028033B2 (ja) 2006-06-13 2012-09-19 キヤノン株式会社 酸化物半導体膜のドライエッチング方法
JP4609797B2 (ja) 2006-08-09 2011-01-12 Ｎｅｃ液晶テクノロジー株式会社 薄膜デバイス及びその製造方法
JP2008052766A (ja) 2006-08-22 2008-03-06 Sony Corp 半導体メモリデバイス
JP4332545B2 (ja) 2006-09-15 2009-09-16 キヤノン株式会社 電界効果型トランジスタ及びその製造方法
JP5164357B2 (ja) 2006-09-27 2013-03-21 キヤノン株式会社 半導体装置及び半導体装置の製造方法
JP4274219B2 (ja) 2006-09-27 2009-06-03 セイコーエプソン株式会社 電子デバイス、有機エレクトロルミネッセンス装置、有機薄膜半導体装置
JP4932415B2 (ja) * 2006-09-29 2012-05-16 株式会社半導体エネルギー研究所 半導体装置
US7622371B2 (en) 2006-10-10 2009-11-24 Hewlett-Packard Development Company, L.P. Fused nanocrystal thin film semiconductor and method
JP2008134625A (ja) * 2006-10-26 2008-06-12 Semiconductor Energy Lab Co Ltd 半導体装置、表示装置及び電子機器
US7772021B2 (en) 2006-11-29 2010-08-10 Samsung Electronics Co., Ltd. Flat panel displays comprising a thin-film transistor having a semiconductive oxide in its channel and methods of fabricating the same for use in flat panel displays
JP2008140684A (ja) 2006-12-04 2008-06-19 Toppan Printing Co Ltd カラーｅｌディスプレイおよびその製造方法
US8058675B2 (en) * 2006-12-27 2011-11-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic device using the same
KR101303578B1 (ko) 2007-01-05 2013-09-09 삼성전자주식회사 박막 식각 방법
US8207063B2 (en) 2007-01-26 2012-06-26 Eastman Kodak Company Process for atomic layer deposition
JP2008211185A (ja) * 2007-02-02 2008-09-11 Semiconductor Energy Lab Co Ltd 記憶素子及び半導体装置
KR100851215B1 (ko) 2007-03-14 2008-08-07 삼성에스디아이 주식회사 박막 트랜지스터 및 이를 이용한 유기 전계 발광표시장치
JP5197058B2 (ja) * 2007-04-09 2013-05-15 キヤノン株式会社 発光装置とその作製方法
US7795613B2 (en) 2007-04-17 2010-09-14 Toppan Printing Co., Ltd. Structure with transistor
KR101325053B1 (ko) 2007-04-18 2013-11-05 삼성디스플레이 주식회사 박막 트랜지스터 기판 및 이의 제조 방법
KR20080094300A (ko) 2007-04-19 2008-10-23 삼성전자주식회사 박막 트랜지스터 및 그 제조 방법과 박막 트랜지스터를포함하는 평판 디스플레이
KR101334181B1 (ko) 2007-04-20 2013-11-28 삼성전자주식회사 선택적으로 결정화된 채널층을 갖는 박막 트랜지스터 및 그제조 방법
CN101663762B (zh) 2007-04-25 2011-09-21 佳能株式会社 氧氮化物半导体
JP5542296B2 (ja) * 2007-05-17 2014-07-09 株式会社半導体エネルギー研究所 液晶表示装置、表示モジュール及び電子機器
JP4989309B2 (ja) * 2007-05-18 2012-08-01 株式会社半導体エネルギー研究所 液晶表示装置
US8803781B2 (en) * 2007-05-18 2014-08-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and display device
KR101345376B1 (ko) 2007-05-29 2013-12-24 삼성전자주식회사 ＺｎＯ 계 박막 트랜지스터 및 그 제조방법
US7935964B2 (en) * 2007-06-19 2011-05-03 Samsung Electronics Co., Ltd. Oxide semiconductors and thin film transistors comprising the same
KR101402189B1 (ko) * 2007-06-22 2014-06-02 삼성전자주식회사 Ｚｎ 산화물계 박막 트랜지스터 및 Ｚｎ 산화물의 식각용액
US8354674B2 (en) 2007-06-29 2013-01-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device wherein a property of a first semiconductor layer is different from a property of a second semiconductor layer
JPWO2009075281A1 (ja) * 2007-12-13 2011-04-28 出光興産株式会社 酸化物半導体を用いた電界効果型トランジスタ及びその製造方法
JP5215158B2 (ja) * 2007-12-17 2013-06-19 富士フイルム株式会社 無機結晶性配向膜及びその製造方法、半導体デバイス
JP5121478B2 (ja) 2008-01-31 2013-01-16 株式会社ジャパンディスプレイウェスト 光センサー素子、撮像装置、電子機器、およびメモリー素子
KR100963003B1 (ko) * 2008-02-05 2010-06-10 삼성모바일디스플레이주식회사 박막 트랜지스터, 그의 제조 방법 및 박막 트랜지스터를구비하는 평판 표시 장치
JP2009237558A (ja) * 2008-03-05 2009-10-15 Semiconductor Energy Lab Co Ltd 半導体装置の駆動方法
JP5305696B2 (ja) * 2008-03-06 2013-10-02 キヤノン株式会社 半導体素子の処理方法
KR101468591B1 (ko) * 2008-05-29 2014-12-04 삼성전자주식회사 산화물 반도체 및 이를 포함하는 박막 트랜지스터
JP4623179B2 (ja) 2008-09-18 2011-02-02 ソニー株式会社 薄膜トランジスタおよびその製造方法
JP5451280B2 (ja) 2008-10-09 2014-03-26 キヤノン株式会社 ウルツ鉱型結晶成長用基板およびその製造方法ならびに半導体装置
JP5781720B2 (ja) 2008-12-15 2015-09-24 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
JP2012164686A (ja) * 2009-06-16 2012-08-30 Sharp Corp 光センサおよび表示装置
KR101669476B1 (ko) * 2009-10-30 2016-10-26 가부시키가이샤 한도오따이 에네루기 켄큐쇼 논리 회로 및 반도체 장치

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1084092A (ja) * 1996-09-09 1998-03-31 Toshiba Corp 半導体集積回路
JPH11126491A (ja) * 1997-08-20 1999-05-11 Fujitsu Ltd 半導体記憶装置
JP2002538572A (ja) * 1999-02-22 2002-11-12 インフィネオン テクノロジーズ アクチエンゲゼルシャフト 自己増幅型ダイナミックメモリセルを具備したメモリセル装置の駆動方法
JP2001028443A (ja) * 1999-05-13 2001-01-30 Hitachi Ltd 半導体装置およびその製造方法
JP2002082656A (ja) * 2000-09-06 2002-03-22 Hitachi Ltd 画像表示装置およびその駆動方法
JP2002368226A (ja) * 2001-06-11 2002-12-20 Sharp Corp 半導体装置、半導体記憶装置及びその製造方法、並びに携帯情報機器
JP2007103918A (ja) * 2005-09-06 2007-04-19 Canon Inc アモルファス酸化物膜をチャネル層に用いた電界効果型トランジスタ、アモルファス酸化物膜をチャネル層に用いた電界効果型トランジスタの製造方法及びアモルファス酸化物膜の製造方法
JP2008042067A (ja) * 2006-08-09 2008-02-21 Canon Inc 酸化物半導体膜のドライエッチング方法

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12336224B2 (en) 2011-11-25 2025-06-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US10158026B2 (en) 2012-04-13 2018-12-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device including oxide semiconductor stacked layers
US10559699B2 (en) 2012-04-13 2020-02-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US10872981B2 (en) 2012-04-13 2020-12-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising an oxide semiconductor
US11355645B2 (en) 2012-04-13 2022-06-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising stacked oxide semiconductor layers
US11929437B2 (en) 2012-04-13 2024-03-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising various thin-film transistors
US12414335B2 (en) 2012-04-13 2025-09-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising conductive layers functioning as first and second gate electrodes of a transistor
US9817032B2 (en) 2012-05-23 2017-11-14 Semiconductor Energy Laboratory Co., Ltd. Measurement device
US12206370B2 (en) 2019-06-28 2025-01-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device including high frequency amplifier circuit, electronic component, and electronic device

Also Published As

Publication number Publication date
JP2016171331A (ja) 2016-09-23
KR20170129287A (ko) 2017-11-24
KR101893904B1 (ko) 2018-08-31
JP2015084422A (ja) 2015-04-30
KR101800850B1 (ko) 2017-11-23
TW201143032A (en) 2011-12-01
JP2017147459A (ja) 2017-08-24
JP6979499B2 (ja) 2021-12-15
JP7522907B2 (ja) 2024-07-25
JP5931998B2 (ja) 2016-06-08
TWI538169B (zh) 2016-06-11
JP2024133246A (ja) 2024-10-01
JP2021002680A (ja) 2021-01-07
JP2011176294A (ja) 2011-09-08
JP2022016531A (ja) 2022-01-21
JP2025118998A (ja) 2025-08-13
KR20120125635A (ko) 2012-11-16
JP5123440B1 (ja) 2013-01-23
JP5426796B2 (ja) 2014-02-26
JP2024026413A (ja) 2024-02-28
KR101299256B1 (ko) 2013-08-22
KR20130064150A (ko) 2013-06-17
US20110186837A1 (en) 2011-08-04
KR20180097794A (ko) 2018-08-31
JP7407879B2 (ja) 2024-01-04
JP6130954B2 (ja) 2017-05-17
US8507907B2 (en) 2013-08-13
JP2013016836A (ja) 2013-01-24
JP6772327B2 (ja) 2020-10-21
JP2013258411A (ja) 2013-12-26
JP7111879B2 (ja) 2022-08-02
JP2019135780A (ja) 2019-08-15
JP7688208B2 (ja) 2025-06-03
KR101948707B1 (ko) 2019-02-15
JP2022137287A (ja) 2022-09-21

Similar Documents

Publication Publication Date Title
JP7688208B2 (ja) 半導体装置
JP2023100741A (ja) 半導体装置
US8582349B2 (en) Semiconductor device
CN102714208B (zh) 半导体装置
WO2011086846A1 (en) Semiconductor device
WO2011052396A1 (en) Semiconductor device
WO2011096277A1 (en) Semiconductor device and method of driving semiconductor device
WO2011105310A1 (en) Semiconductor device
WO2011102228A1 (en) Semiconductor device and driving method of semiconductor device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10844757

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 20127022100

Country of ref document: KR

Kind code of ref document: A

122 Ep: pct application non-entry in european phase

Ref document number: 10844757

Country of ref document: EP

Kind code of ref document: A1