WO2011030454A1 - ダイオード領域とigbt領域を有する半導体基板を備える半導体装置 - Google Patents
ダイオード領域とigbt領域を有する半導体基板を備える半導体装置 Download PDFInfo
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- WO2011030454A1 WO2011030454A1 PCT/JP2009/066000 JP2009066000W WO2011030454A1 WO 2011030454 A1 WO2011030454 A1 WO 2011030454A1 JP 2009066000 W JP2009066000 W JP 2009066000W WO 2011030454 A1 WO2011030454 A1 WO 2011030454A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 89
- 239000000758 substrate Substances 0.000 title claims abstract description 41
- 210000000746 body region Anatomy 0.000 claims abstract description 29
- 238000002955 isolation Methods 0.000 claims description 72
- 239000012535 impurity Substances 0.000 claims description 17
- 238000000926 separation method Methods 0.000 abstract description 37
- 230000003071 parasitic effect Effects 0.000 description 18
- 238000011084 recovery Methods 0.000 description 13
- 230000005684 electric field Effects 0.000 description 7
- 239000013078 crystal Substances 0.000 description 6
- 230000007547 defect Effects 0.000 description 6
- 239000000969 carrier Substances 0.000 description 5
- 239000002245 particle Substances 0.000 description 3
- 230000006798 recombination Effects 0.000 description 3
- 238000005215 recombination Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
- H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
- H01L27/0652—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
- H01L27/0664—Vertical bipolar transistor in combination with diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
- H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
Definitions
- the technology described in this specification relates to a semiconductor device including a semiconductor substrate in which a diode region and an IGBT region are formed.
- Patent Document 1 discloses a semiconductor device including a semiconductor substrate in which a diode region and an IGBT region are formed.
- a p-type region is formed in a boundary region between the diode region and the IGBT region.
- the p-type region is formed in a range from the upper surface of the semiconductor substrate to a depth deeper than the lower end of the anode region and the lower end of the body region.
- the p-type region is in contact with the anode region and the body region.
- the deep p-type region is connected to the anode electrode through the anode region, and is connected to the emitter electrode through the body region.
- a semiconductor device having a diode and an IGBT as in Patent Document 1 is used in a state where an anode electrode of the diode and an emitter electrode of the IGBT are conducted. That is, when a forward voltage is applied between the anode electrode and the cathode electrode, the emitter electrode also has a high potential in the same manner as the anode electrode.
- the anode electrode and the emitter electrode become high potential, so that the deep p-type region also becomes high potential.
- a parasitic diode is formed by the deep p-type region, the drift region, and the cathode region.
- a lifetime control region may be formed in the drift region of the diode (hereinafter referred to as the diode drift region).
- the lifetime control region is a region in which the lifetime of carriers is shortened by forming crystal defects and the like.
- the lifetime control region is formed in the diode drift region of the semiconductor device of Patent Document 1.
- a parasitic diode is formed in the semiconductor device of Patent Document 1.
- most of the carriers in the diode drift region disappear in the lifetime control region due to recombination in the diode region. Therefore, a high reverse current does not flow in the diode region.
- a reverse current also flows through the parasitic diode. Since the reverse current flowing through the parasitic diode does not pass through the lifetime control region, the reverse current flowing through the parasitic diode becomes large. The reverse current generated by the parasitic diode increases the loss during the reverse recovery operation.
- the present specification provides a semiconductor device having a diode and an IGBT, which is unlikely to generate a reverse current during a reverse recovery operation of the diode.
- the semiconductor device disclosed in this specification includes a semiconductor substrate in which a diode region and an IGBT region are formed.
- An anode region, a diode drift region, and a cathode region are formed in the diode region.
- the anode region is p-type and is formed in a range including the upper surface of the semiconductor substrate.
- the diode drift region is n-type and is formed below the anode region.
- the cathode region is n-type, has an n-type impurity concentration higher than that of the diode drift region, and is formed in a range below the diode drift region including the lower surface of the semiconductor substrate.
- an emitter region In the IGBT region, an emitter region, a body region, an IGBT drift region, a collector region, and a gate electrode are formed.
- the emitter region is n-type and is formed in a range including the upper surface of the semiconductor substrate.
- the body region is p-type and is formed in a range including the upper surface of the semiconductor substrate and a range below the emitter region.
- the IGBT drift region is n-type, is formed below the body region, and is separated from the emitter region by the body region.
- the collector region is p-type and is formed in a range below the IGBT drift region including the lower surface of the semiconductor substrate.
- the gate electrode faces the body region in a range separating the emitter region and the IGBT drift region via an insulating film.
- a lifetime control region is formed in the diode drift region.
- the carrier lifetime in the lifetime control region is shorter than the carrier lifetime in the diode drift region outside the lifetime control region.
- the diode drift region and the IGBT drift region are continuous in the boundary region.
- a first separation region, a second separation region, and an n-type region are formed in the boundary region.
- the first isolation region is p-type and is formed in a range from the upper surface of the semiconductor substrate to a depth deeper than the lower end of the anode region and the lower end of the body region, and is in contact with the anode region.
- the second isolation region is p-type, and is formed in a range from the upper surface of the semiconductor substrate to a depth deeper than the lower end of the anode region and the lower end of the body region, and is in contact with the body region.
- the n-type region is formed between the first separation region and the second separation region, and separates the first separation region and the second separation region.
- the first separation region and the second separation region are formed in the boundary region. That is, two deep p layers separated from each other are formed in the boundary region.
- the first isolation region and the second isolation region can suppress the concentration of the electric field on the gate electrode or body region of the IGBT near the boundary region. Further, the reverse current of the diode in the diode region is suppressed by the lifetime control region. Further, since the second isolation region in contact with the body region is separated from the cathode region of the diode region, almost no reverse current flows in the second isolation region during the reverse recovery operation of the diode in the diode region.
- the reverse current flowing through the boundary region is smaller than that of a semiconductor device in which one deep p-type region (p-type region in contact with both the anode region and the body region) is formed in the boundary region. Become. Therefore, in this semiconductor device, a reverse current hardly flows during the reverse recovery operation of the diode.
- a third isolation region is formed between the first isolation region and the second isolation region.
- the third isolation region is p-type and is formed in a range from the upper surface of the semiconductor substrate to a depth deeper than the lower end of the anode region and the lower end of the body region, and the first isolation region and the second isolation region are formed by the n-type region. Separated from the area.
- the first isolation region, the second isolation region, and the third isolation region can suppress the concentration of the electric field on the gate electrode or body region of the IGBT near the boundary region. Moreover, since the third separation region is separated from the first separation region and the second separation region, no reverse current flows through the third separation region. As described above, since the boundary region is formed by the structure including the third separation region where the reverse current does not flow, the reverse current in the boundary region can be further suppressed.
- the end of the lifetime control region on the IGBT region side is preferably located below the first isolation region.
- the reverse current flowing in the first separation region can be reduced.
- FIG. 1 is a longitudinal sectional view of a semiconductor device according to a first embodiment.
- the semiconductor device 10 includes a semiconductor substrate 12 and a metal layer, an insulating layer, and the like formed on the upper surface and the lower surface of the semiconductor substrate 12.
- a diode region 20 and an IGBT region 40 are formed in the semiconductor substrate 12.
- An anode electrode 22 is formed on the upper surface of the semiconductor substrate 12 in the diode region 20.
- An emitter electrode 42 is formed on the upper surface of the semiconductor substrate 12 in the IGBT region 40.
- a common electrode 60 is formed on the entire lower surface of the semiconductor substrate 12.
- an anode layer 26 In the diode region 20, an anode layer 26, a diode drift layer 28, and a cathode layer 30 are formed.
- the anode layer 26 is p-type.
- the anode layer 26 includes an anode contact region 26a and a low concentration anode layer 26b.
- the anode contact region 26 a is formed in an island shape in a range including the upper surface of the semiconductor substrate 12.
- the anode contact region 26a has a high impurity concentration.
- the anode contact region 26 a is ohmically connected to the anode electrode 22.
- the low concentration anode layer 26b is formed on the lower side and the side of the anode contact region 26a and covers the anode contact region 26a.
- the impurity concentration of the low concentration anode layer 26b is lower than that of the anode contact region 26a.
- the position of the lower end of the anode layer 26 is shallower than the position of the lower end of the gate electrode 54 described later.
- the diode drift layer 28 is formed below the anode layer 26.
- the diode drift layer 28 is n-type.
- the diode drift layer 28 includes a drift layer 28a and a buffer layer 28b.
- the drift layer 28 a is formed below the anode layer 26.
- the drift layer 28a has a low impurity concentration.
- the buffer layer 28b is formed below the drift layer 28a.
- the buffer layer 28b has a higher impurity concentration than the drift layer 28a.
- the cathode layer 30 is formed below the diode drift layer 28.
- the cathode layer 30 is formed in a range including the lower surface of the semiconductor substrate 12.
- the cathode layer 30 is n-type and has a high impurity concentration.
- the cathode layer 30 is ohmically connected to the common electrode 60.
- a diode is formed by the anode layer 26, the diode drift layer 28, and the cathode layer 30.
- the diode formed in the diode region 20 is referred to as a diode 20.
- an emitter region 44 In the IGBT region 40, an emitter region 44, a body layer 48, an IGBT drift layer 50, a collector layer 52, a gate electrode 54, and the like are formed.
- a plurality of trenches are formed on the upper surface of the semiconductor substrate 12 in the IGBT region 40.
- a gate insulating film 56 is formed on the inner surface of each trench.
- a gate electrode 54 is formed inside each trench. The upper surface of the gate electrode 54 is covered with an insulating film 58. The gate electrode 54 is insulated from the emitter electrode 42.
- the emitter region 44 is formed in an island shape in a range including the upper surface of the semiconductor substrate 12.
- the emitter region 44 is formed in a range in contact with the gate insulating film 56.
- the emitter region 44 is n-type and has a high impurity concentration.
- the emitter region 44 is ohmically connected to the emitter electrode 42.
- the body layer 48 is p-type.
- the body layer 48 includes a body contact region 48a and a low concentration body layer 48b.
- the body contact region 48 a is formed in an island shape in a range including the upper surface of the semiconductor substrate 12.
- the body contact region 48 a is formed between the two emitter regions 44.
- the body contact region 48a has a high impurity concentration.
- the body contact region 48 a is ohmically connected to the emitter electrode 42.
- the low concentration body layer 48b is formed under the emitter region 44 and the body contact region 48a.
- the low concentration body layer 48 b is formed in a shallower range than the lower end of the gate electrode 54.
- the impurity concentration of the low-concentration body layer 48b is lower than that of the body contact region 48a.
- the emitter region 44 is separated from the IGBT drift layer 50 by the low-concentration body layer 48b.
- the gate electrode 54 is opposed to the low-concentration body layer 48 b in a range separating the emitter region 44 and the IGBT drift layer 50 through the gate insulating film 56.
- the IGBT drift layer 50 is formed below the body layer 48.
- the IGBT drift layer 50 is n-type.
- the IGBT drift layer 50 includes a drift layer 50a and a buffer layer 50b.
- the drift layer 50 a is formed below the body layer 48.
- the drift layer 50a has a low impurity concentration.
- the drift layer 50 a has substantially the same impurity concentration as the diode drift layer 28.
- the drift layer 50a is connected to the drift layer 28a in a boundary region 70 described later.
- the drift layer 28a and the drift layer 50a may be collectively referred to as the drift layer 90.
- the buffer layer 50b is formed below the drift layer 50a.
- the buffer layer 50b has a higher impurity concentration than the drift layer 50a.
- the buffer layer 50b is connected to the drift layer 28b in a boundary region 70 described later.
- the collector layer 52 is formed below the IGBT drift layer 50.
- the collector layer 52 is formed in a range including the lower surface of the semiconductor substrate 12.
- the collector layer 52 is p-type and has a high impurity concentration.
- the collector layer 52 is ohmically connected to the common electrode 60.
- the collector layer 52 is adjacent to the cathode layer 30. The boundary between the collector layer 52 and the cathode layer 30 is located under a separation region 72 described later.
- an IGBT is formed by the emitter region 44, the body layer 48, the IGBT drift layer 50, the collector layer 52, and the gate electrode 54.
- a boundary region 70 exists between the diode region 20 and the IGBT region 40.
- Two separation regions 72 and 74 are formed in the boundary region 70.
- the isolation regions 72 and 74 are formed in a range from the upper surface of the semiconductor substrate 12 to a depth deeper than the lower end of the anode layer 26 and the lower end of the body layer 48. More specifically, the isolation regions 72 and 74 are formed in a range from the upper surface of the semiconductor substrate 12 to a depth deeper than the lower end of the gate electrode 54.
- the separation region 72 is in contact with the anode layer 26.
- the isolation region 72 is p-type.
- the impurity concentration of the isolation region 72 is higher than that of the low concentration anode layer 26b and the low concentration body layer 48b.
- the isolation region 74 is in contact with the body layer 26.
- the isolation region 74 is p-type.
- the impurity concentration of the isolation region 74 is higher than that of the low concentration anode layer 26b and the low concentration body layer 48b.
- a drift layer 90 exists between the isolation region 72 and the isolation region 74.
- the isolation region 72 and the isolation region 74 are isolated from each other by the drift layer 90.
- a depletion layer extends from the isolation regions 72 and 74 into the drift layer 90 below it. Thereby, electric field concentration in the vicinity of the boundary region 70 is suppressed.
- the isolation regions 72 and 74 are formed to a depth deeper than the lower end of the gate electrode 54, the concentration of the electric field on the gate electrode 54 near the isolation region 70 is suppressed.
- the diode drift layer 28 and the IGBT drift layer 50 are continuous.
- the cathode layer 30 in the diode region 20 extends into the boundary region 70, and the collector layer 52 in the IGBT region 40 extends into the boundary region 70.
- the cathode layer 30 is in contact with the collector layer 52 below the separation region 72.
- the cross-sectional structure of the boundary region 70 shown in FIG. 1 extends along the boundary between the diode region 20 and the IGBT region 40.
- a carrier lifetime control region 39 is formed in the diode drift layer 28.
- the carrier lifetime control region 39 there are crystal defects formed by implanting charged particles into the semiconductor substrate 12.
- the crystal defect density in the carrier lifetime control region 39 is extremely higher than that of the surrounding diode drift layer 28.
- the carrier lifetime control region 39 has a depth near the anode layer 26 and is deeper than the lower end of the separation region 72.
- Reference numeral 39 a indicates an end of the carrier lifetime control region 39 on the IGBT region 40 side. Outside the end portion 39a (on the IGBT region 40 side), crystal defects are distributed along the depth direction (vertical direction in FIG. 1). This is because when the charged particles are implanted, the implantation depth of the charged particles changes in the vicinity of the outer periphery of the opening of the mask.
- the crystal defects distributed along the depth direction have a low density and hardly affect the characteristics of the semiconductor device 10.
- An end 39 a of the carrier lifetime control region 39 is located below the separation region 72. That is, the end 39 a of the carrier lifetime control region 39 extends along the separation region 72.
- a parasitic diode (hereinafter referred to as a first parasitic diode) is formed by the anode layer 26, the isolation region 72, the drift layer 90, and the cathode layer 30.
- a forward voltage is applied, the first parasitic diode is turned on, and a current flows from the anode electrode 22 toward the common electrode 60 also in the path indicated by the arrow 102 in FIG.
- a parasitic diode (hereinafter referred to as a second parasitic diode) is also formed by the body contact region 48a, the isolation region 72, the drift layer 90, and the cathode layer 30.
- a forward voltage is applied and the emitter electrode 42 becomes a high potential
- a current flows from the emitter electrode 42 toward the common electrode 60 through a path indicated by an arrow 104 in FIG.
- the separation region 74 is separated from the separation region 72, thereby increasing the distance from the separation region 74 to the cathode region 30. For this reason, the current flowing through the path indicated by the arrow 104 is extremely small.
- the diode 20 When the voltage applied to the diode 20 is switched from the forward voltage to the reverse voltage, the diode 20 performs a reverse recovery operation. That is, holes that existed in the diode drift layer 28 when the forward voltage is applied are discharged to the anode electrode 22, and electrons that existed in the diode drift layer 28 when the forward voltage is applied are discharged to the common electrode 60. As a result, a reverse current flows through the diode 20 in the direction opposite to the arrow 100 in FIG. The reverse current decays in a short time, and thereafter, the current flowing through the diode 20 becomes substantially zero.
- the crystal defects in the carrier lifetime control region 39 function as carrier recombination centers. Therefore, during the reverse recovery operation, many of the carriers in the diode drift layer 28 disappear by recombination in the carrier lifetime control region 39. Therefore, the reverse current flowing through the diode 20 is small.
- a reverse current flows through the first parasitic diode. That is, a reverse current flows in the direction opposite to the arrow 102 in FIG.
- the carrier lifetime control region 39 is formed under the separation region 72. For this reason, the reverse current flowing through the first parasitic diode passes through the carrier lifetime control region 39. For this reason, most of the carriers disappear in the lifetime control area 39. Therefore, the reverse current flowing through the first parasitic diode is also small.
- a reverse current flows through the second parasitic diode. That is, a reverse current flows in the reverse direction of the arrow 104 in FIG.
- the current flowing through the second parasitic diode when a forward voltage is applied is extremely small. For this reason, during the reverse recovery operation of the diode 20, there are very few carriers present in the current path (arrow 104) of the second parasitic diode. Therefore, the reverse current flowing through the second parasitic diode is extremely small.
- the isolation region 74 is isolated from the isolation region 72, the reverse current flowing through the isolation region 74 is extremely small. Thereby, it is suppressed that a loss arises by a reverse current.
- the lifetime control region 39 is formed in the drift layer 90 below the isolation region 72. Thereby, the reverse current flowing through the separation region 72 is suppressed. Therefore, the loss caused by the reverse current is further suppressed.
- the width of the boundary region 70 of the semiconductor device 110 according to the second embodiment is substantially equal to the width of the boundary region 70 of the semiconductor device 10 according to the first embodiment.
- the width of the isolation region 72 and the width of the isolation region 74 are smaller than those of the semiconductor device 10 of the first embodiment, and the isolation region is located between the isolation region 72 and the isolation region 74. 76 is formed.
- Other configurations of the semiconductor device 10 of the second embodiment are the same as those of the semiconductor device 10 of the first embodiment.
- the isolation region 76 is formed in a range from the upper surface of the semiconductor substrate 12 to a depth deeper than the lower end of the gate electrode 54.
- the isolation region 76 is p-type.
- the impurity concentration of the isolation region 76 is higher than that of the low concentration anode layer 26b and the low concentration body layer 48b.
- the upper surface of the isolation region 76 is covered with an insulating layer 78.
- a drift layer 90 exists between the isolation region 76 and the isolation region 72.
- the isolation region 76 and the isolation region 72 are isolated from each other by the drift layer 90.
- a drift layer 90 exists between the isolation region 76 and the isolation region 74.
- the isolation region 76 and the isolation region 74 are separated from each other by the drift layer 90.
- the isolation regions 72, 74, and 76 prevent the electric field from concentrating on the gate electrode 54 and the body layer 48 in the vicinity of the boundary region 70.
- the isolation region 76 is surrounded by the drift region 90. For this reason, when a forward voltage is applied to the diode 20, the isolation region 76 does not become a current path. Therefore, no reverse current flows through the isolation region 76 even during the reverse recovery operation of the diode 20. Further, since the separation region 76 is formed, the widths of the separation regions 72 and 74 are reduced. The isolation region 72 is less likely to flow reverse current due to the reduced width. Further, since the separation region 74 has a small width and a longer distance to the cathode region 30, the reverse current is less likely to flow. Therefore, the reverse current is less likely to flow in the semiconductor device 110 of the second embodiment than in the semiconductor device 10 of the first embodiment.
- a plurality of isolation regions are provided in the boundary region. Thereby, the electric field concentration in the vicinity of the boundary region is suppressed, and the reverse current is prevented from flowing in the boundary region.
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Abstract
Description
第1実施例に係る半導体装置について説明する。
図1に示すように、半導体装置10は、半導体基板12と、半導体基板12の上面及び下面に形成されている金属層及び絶縁層等を備えている。半導体基板12には、ダイオード領域20とIGBT領域40が形成されている。
半導体装置10のダイオード20の動作について説明する。ダイオード20に電流を流す際には、ダイオード20に順電圧が印加される。すなわち、アノード電極22と共通電極60の間に、アノード電極22がプラスとなる電圧が印加される。なお、半導体装置10は、アノード電極22とエミッタ電極42とを導通させた状態で使用される。したがって、ダイオード20に順電圧を印加すると、エミッタ電極42の電位がアノード電極22と略同じ電位に上昇する。順電圧が印加されると、ダイオード20がオンする。すなわち、図1の矢印100に示すように、アノード電極22から、アノード層26、ダイオードドリフト層28、及び、カソード層30を経由して、共通電極60に向かって電流が流れる。
次に、第2実施例の半導体装置110について説明する。第2実施例の半導体装置110の境界領域70の幅は、第1実施例の半導体装置10の境界領域70の幅と略等しい。第2実施例の半導体装置110では、分離領域72の幅と分離領域74の幅が、第1実施例の半導体装置10よりも小さくなっており、分離領域72と分離領域74の間に分離領域76が形成されている。第2実施例の半導体装置10のその他の構成は、第1実施例の半導体装置10と等しい。
Claims (3)
- ダイオード領域とIGBT領域が形成されている半導体基板を備える半導体装置であって、
ダイオード領域には、
p型であり、半導体基板の上面を含む範囲に形成されているアノード領域と、
n型であり、アノード領域の下側に形成されているダイオードドリフト領域と、
n型であり、ダイオードドリフト領域よりn型不純物濃度が高く、半導体基板の下面を含むダイオードドリフト領域の下側の範囲に形成されているカソード領域、
が形成されており、
IGBT領域には、
n型であり、半導体基板の上面を含む範囲に形成されているエミッタ領域と、
p型であり、半導体基板の上面を含む範囲及びエミッタ領域の下側の範囲に形成されているボディ領域と、
n型であり、ボディ領域の下側に形成されており、ボディ領域によってエミッタ領域から分離されているIGBTドリフト領域と、
p型であり、半導体基板の下面を含むIGBTドリフト領域の下側の範囲に形成されているコレクタ領域と、
エミッタ領域とIGBTドリフト領域を分離している範囲のボディ領域に絶縁膜を介して対向しているゲート電極、
が形成されており、
ダイオードドリフト領域内には、ライフタイム制御領域が形成されており、
ライフタイム制御領域のキャリアライフタイムは、ライフタイム制御領域外のダイオードドリフト領域のキャリアライフタイムより短く、
ダイオードドリフト領域とIGBTドリフト領域は、ダイオード領域とIGBT領域の間の境界領域において連続しており、
境界領域には、
p型であり、半導体基板の上面からアノード領域の下端及びボディ領域の下端より深い深さまでの範囲に形成されており、アノード領域と接している第1分離領域と、
p型であり、半導体基板の上面からアノード領域の下端及びボディ領域の下端より深い深さまでの範囲に形成されており、ボディ領域と接している第2分離領域と、
n型であり、第1分離領域と第2分離領域の間に形成されており、第1分離領域と第2分離領域を分離しているn型領域
が形成されている、
ことを特徴とする半導体装置。 - 第1分離領域と第2分離領域の間に、p型であり、半導体基板の上面からアノード領域の下端及びボディ領域の下端より深い深さまでの範囲に形成されており、前記n型領域によって第1分離領域及び第2分離領域から分離されている第3分離領域が形成されていることを特徴とする請求項1に記載の半導体装置。
- ライフタイム制御領域のIGBT領域側の端部が、第1分離領域の下に位置していることを特徴とする請求項1または2に記載の半導体装置。
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PCT/JP2009/066000 WO2011030454A1 (ja) | 2009-09-14 | 2009-09-14 | ダイオード領域とigbt領域を有する半導体基板を備える半導体装置 |
DE112009004065.9T DE112009004065B4 (de) | 2009-09-14 | 2009-09-14 | Halbleitereinrichtung mit einem Halbleitersubstrat einschließlich eines Diodenbereichs und eines IGBT-Bereichs |
JP2011530711A JP5282823B2 (ja) | 2009-09-14 | 2009-09-14 | ダイオード領域とigbt領域を有する半導体基板を備える半導体装置 |
CN200980159079.XA CN102414817B (zh) | 2009-09-14 | 2009-09-14 | 具备具有二极管区和igbt区的半导体基板的半导体装置 |
US13/242,072 US8330185B2 (en) | 2009-09-14 | 2011-09-23 | Semiconductor device having semiconductor substrate including diode region and IGBT region |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8299496B2 (en) | 2009-09-07 | 2012-10-30 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device having semiconductor substrate including diode region and IGBT region |
US8334193B2 (en) | 2009-12-15 | 2012-12-18 | Toyota Jidosha Kabushiki Kaisha | Method of manufacturing semiconductor device |
US20140217465A1 (en) * | 2011-08-30 | 2014-08-07 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device |
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Publication number | Priority date | Publication date | Assignee | Title |
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DE112010005443B4 (de) * | 2010-04-02 | 2019-03-14 | Toyota Jidosha Kabushiki Kaisha | Halbleitervorrichtung mit einem Halbleitersubstrat mit einem Diodenbereich und einem IGBT-Bereich sowie Verfahren zu dessen Herstellung |
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JP6119593B2 (ja) * | 2013-12-17 | 2017-04-26 | トヨタ自動車株式会社 | 半導体装置 |
JP6181597B2 (ja) * | 2014-04-28 | 2017-08-16 | トヨタ自動車株式会社 | 半導体装置及び半導体装置の製造方法 |
CN105161527B (zh) * | 2015-06-26 | 2018-03-02 | 成都成电知力微电子设计有限公司 | 利用一种表面耐压层结构的绝缘栅双极型器件 |
JP6588774B2 (ja) * | 2015-09-02 | 2019-10-09 | 株式会社東芝 | 半導体装置 |
JP6281548B2 (ja) * | 2015-09-17 | 2018-02-21 | トヨタ自動車株式会社 | 半導体装置 |
JP6588363B2 (ja) * | 2016-03-09 | 2019-10-09 | トヨタ自動車株式会社 | スイッチング素子 |
EP3324443B1 (en) * | 2016-11-17 | 2019-09-11 | Fuji Electric Co., Ltd. | Semiconductor device |
JP6780709B2 (ja) * | 2016-12-16 | 2020-11-04 | 富士電機株式会社 | 半導体装置および製造方法 |
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Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1041510A (ja) * | 1996-05-22 | 1998-02-13 | Fuji Electric Co Ltd | 温度検知部内蔵型バイポーラ半導体素子およびその製造方法 |
JPH10326897A (ja) * | 1997-03-25 | 1998-12-08 | Hitachi Ltd | 電流検出セル付トレンチゲート半導体装置 |
JPH1117179A (ja) * | 1997-06-24 | 1999-01-22 | Toshiba Corp | 半導体装置 |
JP2005317751A (ja) * | 2004-04-28 | 2005-11-10 | Mitsubishi Electric Corp | 逆導通型半導体素子とその製造方法 |
JP2008192737A (ja) * | 2007-02-02 | 2008-08-21 | Denso Corp | 半導体装置 |
JP2008211148A (ja) * | 2007-02-28 | 2008-09-11 | Fuji Electric Device Technology Co Ltd | 半導体装置およびその製造方法 |
JP2008235405A (ja) * | 2007-03-19 | 2008-10-02 | Denso Corp | 半導体装置 |
JP2009170670A (ja) * | 2008-01-16 | 2009-07-30 | Toyota Motor Corp | 半導体装置とその半導体装置を備えている給電装置の駆動方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3321185B2 (ja) * | 1990-09-28 | 2002-09-03 | 株式会社東芝 | 高耐圧半導体装置 |
GB9216953D0 (en) * | 1992-08-11 | 1992-09-23 | Philips Electronics Uk Ltd | A semiconductor component |
US6180966B1 (en) | 1997-03-25 | 2001-01-30 | Hitachi, Ltd. | Trench gate type semiconductor device with current sensing cell |
JP4761644B2 (ja) | 2001-04-18 | 2011-08-31 | 三菱電機株式会社 | 半導体装置 |
WO2010143288A1 (ja) | 2009-06-11 | 2010-12-16 | トヨタ自動車株式会社 | 半導体装置 |
WO2011027473A1 (ja) | 2009-09-07 | 2011-03-10 | トヨタ自動車株式会社 | ダイオード領域とigbt領域を有する半導体基板を備える半導体装置 |
-
2009
- 2009-09-14 JP JP2011530711A patent/JP5282823B2/ja not_active Expired - Fee Related
- 2009-09-14 CN CN200980159079.XA patent/CN102414817B/zh active Active
- 2009-09-14 DE DE112009004065.9T patent/DE112009004065B4/de active Active
- 2009-09-14 WO PCT/JP2009/066000 patent/WO2011030454A1/ja active Application Filing
-
2011
- 2011-09-23 US US13/242,072 patent/US8330185B2/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1041510A (ja) * | 1996-05-22 | 1998-02-13 | Fuji Electric Co Ltd | 温度検知部内蔵型バイポーラ半導体素子およびその製造方法 |
JPH10326897A (ja) * | 1997-03-25 | 1998-12-08 | Hitachi Ltd | 電流検出セル付トレンチゲート半導体装置 |
JPH1117179A (ja) * | 1997-06-24 | 1999-01-22 | Toshiba Corp | 半導体装置 |
JP2005317751A (ja) * | 2004-04-28 | 2005-11-10 | Mitsubishi Electric Corp | 逆導通型半導体素子とその製造方法 |
JP2008192737A (ja) * | 2007-02-02 | 2008-08-21 | Denso Corp | 半導体装置 |
JP2008211148A (ja) * | 2007-02-28 | 2008-09-11 | Fuji Electric Device Technology Co Ltd | 半導体装置およびその製造方法 |
JP2008235405A (ja) * | 2007-03-19 | 2008-10-02 | Denso Corp | 半導体装置 |
JP2009170670A (ja) * | 2008-01-16 | 2009-07-30 | Toyota Motor Corp | 半導体装置とその半導体装置を備えている給電装置の駆動方法 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8299496B2 (en) | 2009-09-07 | 2012-10-30 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device having semiconductor substrate including diode region and IGBT region |
US8334193B2 (en) | 2009-12-15 | 2012-12-18 | Toyota Jidosha Kabushiki Kaisha | Method of manufacturing semiconductor device |
US20140217465A1 (en) * | 2011-08-30 | 2014-08-07 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device |
US9379224B2 (en) * | 2011-08-30 | 2016-06-28 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device |
JP7405020B2 (ja) | 2020-06-29 | 2023-12-26 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
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US8330185B2 (en) | 2012-12-11 |
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JPWO2011030454A1 (ja) | 2013-02-04 |
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