WO2010101016A1 - 炭化珪素半導体装置の製造方法 - Google Patents
炭化珪素半導体装置の製造方法 Download PDFInfo
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- WO2010101016A1 WO2010101016A1 PCT/JP2010/052153 JP2010052153W WO2010101016A1 WO 2010101016 A1 WO2010101016 A1 WO 2010101016A1 JP 2010052153 W JP2010052153 W JP 2010052153W WO 2010101016 A1 WO2010101016 A1 WO 2010101016A1
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- epitaxial layer
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- silicon carbide
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 229910010271 silicon carbide Inorganic materials 0.000 title claims description 97
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims description 94
- 238000004519 manufacturing process Methods 0.000 title claims description 51
- 238000000034 method Methods 0.000 title claims description 41
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 230000007547 defect Effects 0.000 abstract description 41
- 239000013078 crystal Substances 0.000 abstract description 36
- 230000005012 migration Effects 0.000 abstract description 19
- 238000013508 migration Methods 0.000 abstract description 19
- 239000007789 gas Substances 0.000 description 13
- ATUOYWHBWRKTHZ-UHFFFAOYSA-N Propane Chemical compound CCC ATUOYWHBWRKTHZ-UHFFFAOYSA-N 0.000 description 10
- 239000012535 impurity Substances 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
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- 230000007423 decrease Effects 0.000 description 5
- 239000001294 propane Substances 0.000 description 5
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- 238000005530 etching Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
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- 238000000206 photolithography Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000003763 carbonization Methods 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- SLLGVCUQYRMELA-UHFFFAOYSA-N chlorosilicon Chemical compound Cl[Si] SLLGVCUQYRMELA-UHFFFAOYSA-N 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000003795 desorption Methods 0.000 description 1
- BUMGIEFFCMBQDG-UHFFFAOYSA-N dichlorosilicon Chemical compound Cl[Si]Cl BUMGIEFFCMBQDG-UHFFFAOYSA-N 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
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- 229910052698 phosphorus Inorganic materials 0.000 description 1
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- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 description 1
- 239000005052 trichlorosilane Substances 0.000 description 1
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- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
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- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
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- H01L29/7395—Vertical transistors, e.g. vertical IGBT
Definitions
- the present invention relates to a method of manufacturing a silicon carbide (hereinafter referred to as “SiC”) semiconductor device.
- SiC silicon carbide
- step flow growth by inclining the wafer, the reactive species attached to the crystal surface diffuse on the terrace and are sequentially taken in from the reactive species that have reached the step, and a flat surface morphology is obtained.
- the wafer is inclined from the (0001) plane of the substrate toward the [11-20] direction. The above inclination angle is referred to as “off angle”, and so far, a general off angle is 8 degrees for 4H—SiC substrates and 3.5 degrees for 6H—SiC.
- Patent Document 1 epitaxial growth is performed on a 4H—SiC substrate having an off angle of 8 degrees in the [11-20] direction from the (0001) plane of the substrate, and further on the epitaxial layer generated thereby. It has been proposed to reduce the density of Basal Plane dislocations inherited from the SiC substrate by increasing the growth temperature and performing epitaxial growth.
- the terrace width increases, and the reaction species cannot reach the step and remain on the terrace to become a nucleus.
- the probability of two-dimensional nuclear growth starting from that nucleus increases. To do.
- the migration length of the reactive species on the terrace is shortened, so that crystal defects due to poor migration of the reactive species on the terrace surface are likely to occur.
- the terrace width greatly increases with respect to the migration length of the reactive species as the off angle decreases. Therefore, the reactive species stay on the terrace and form nuclei easily, and the probability of occurrence of crystal defects starting from the nuclei increases. In particular, these crystal defects are more likely to occur near the interface between the substrate in the initial stage of growth and the epitaxial layer formed thereon than during the growth.
- an effective method is to increase the growth temperature and increase the migration length of the reactive species.
- the present invention has been made to solve the above-mentioned problems newly recognized in an SiC substrate having an off angle of 5 degrees or less, and is caused by a bunching step and a migration failure.
- the main object of the present invention is to obtain a method for manufacturing a silicon carbide semiconductor device that includes an epitaxial layer with few crystal defects or that can widen the process margin (also referred to as a process window) of the epitaxial layer.
- a method of manufacturing a silicon carbide semiconductor device includes a step of growing a first epitaxial layer on a main surface of a silicon carbide semiconductor substrate having an off angle, and an upper surface of the first epitaxial layer. And a step of growing the second epitaxial layer in contact with the upper surface of the first epitaxial layer at a growth temperature lower than the growth temperature of the first epitaxial layer.
- the subject matter of the present invention it is possible to generate an epitaxial film on a SiC substrate having an off angle while suppressing the occurrence of a bunching step and having few crystal defects caused by a defective migration of reactive species. . That is, the above-described crystal defects are suppressed by epitaxially growing the first epitaxial layer at a high temperature, and the height of the bunching step is increased by growing the second epitaxial layer at a temperature lower than the growth temperature of the first epitaxial layer. To reduce. Thereby, both the height of the bunching step and the crystal defect density starting from the migration failure can be reduced.
- FIG. 1 is a longitudinal sectional view showing a structure of a vertical n-channel SiC-MOSFET as an example of a semiconductor element structure of an SiC semiconductor device manufactured by the method of manufacturing an SiC semiconductor device according to the first embodiment.
- FIG. 6 is a longitudinal sectional view showing a method for manufacturing a vertical n-channel SiC-MOSFET according to the present embodiment.
- FIG. 6 is a longitudinal sectional view showing a method for manufacturing a vertical n-channel SiC-MOSFET according to the present embodiment.
- FIG. 6 is a longitudinal sectional view showing a method for manufacturing a vertical n-channel SiC-MOSFET according to the present embodiment.
- FIG. 6 is a longitudinal sectional view showing a method for manufacturing a vertical n-channel SiC-MOSFET according to the present embodiment.
- FIG. 6 is a longitudinal sectional view showing a method for manufacturing a vertical n-channel SiC-MOSFET according to the present embodiment.
- FIG. 6 is a longitudinal sectional view showing a method for manufacturing a vertical n-channel SiC-MOSFET according to the present embodiment. It is a longitudinal cross-sectional view showing a method for manufacturing a vertical n-channel SiC-MOSFET according to the present embodiment.
- FIG. 6 is a longitudinal sectional view showing a method for manufacturing a vertical n-channel SiC-MOSFET according to the present embodiment.
- FIG. 6 is a longitudinal sectional view showing a method for manufacturing a vertical n-channel SiC-MOSFET according to the present embodiment.
- FIG. 1 It is the figure showing the temperature profile in a reaction furnace until producing the 1st drift layer and 2nd drift layer which were shown by FIG. It is a figure which shows the crystal defect observed from the migration defect observed. It is a figure which shows the crystal defect observed from the migration defect observed. It is a figure which shows the crystal defect observed from the migration defect observed. It is the figure showing the temperature profile in a reaction furnace until producing the 1st drift layer and 2nd drift layer which were shown by FIG. It is a longitudinal cross-sectional view which shows the structure of the SiC Schottky diode which was produced by the manufacturing method which concerns on Embodiment 2, and has an SiC substrate with an off angle of 5 degrees or less.
- FIG. 1 SiC Schottky diode
- FIG. 10 is a longitudinal sectional view showing a structure of a SiC-MOSFET having a SiC substrate with an off angle of 5 degrees or less, created by the manufacturing method according to the third embodiment.
- FIG. 10 is a longitudinal sectional view showing a structure of a SiC-MOSFET having a SiC substrate with an off angle of 5 degrees or less, created by the manufacturing method according to the fourth embodiment. It is a figure which shows the relationship between the growth temperature of an epitaxial layer, and the height of a bunching step. It is the figure which showed the relationship between the growth temperature of an epitaxial layer, and the crystal defect density resulting from a migration defect.
- the feature of the method of manufacturing the SiC semiconductor device according to the present embodiment is that when the drift layer of the SiC semiconductor element (vertical MOSFET or IGBT) is formed, the first epitaxial film (first drift layer) is formed. A first drift layer is formed by growth, and a second epitaxial film (second drift layer) is grown on the first drift layer at a temperature lower than the growth temperature of the first epitaxial film. Is to form.
- FIG. 1 A vertical n-channel SiC-MOSFET is shown in a longitudinal sectional view of FIG. 1 as an example of a semiconductor element structure of an SiC semiconductor device manufactured by the method of manufacturing an SiC semiconductor device according to the present embodiment.
- the reference numerals indicate the following components. That is, 1 is an n-type (corresponding to the first conductivity type) SiC substrate having an off angle of 5 degrees or less (for example, an off angle of 4 degrees), and 2 is an epitaxial growth layer made of n-type SiC.
- first epitaxial layer 3 is a second drift layer (second epitaxial layer) made of n-type SiC obtained by epitaxial growth under a growth temperature lower than the growth temperature of the first drift layer 2 4 is a p-type (second conductivity type) base region (well region), 5 is an n-type source region, 6 is a gate insulating film, 7 is a gate electrode, 8 is a source electrode, and 9 is a drain electrode. , Respectively. Therefore, the drift layer in the vertical n-channel SiC-MOSFET of FIG.
- FIGS. 2 to 9 are longitudinal sectional views showing a method of manufacturing the SiC semiconductor device according to the present embodiment, specifically, a method of manufacturing a vertical n-channel SiC-MOSFET.
- a method for manufacturing an SiC semiconductor device according to the present embodiment will be described with reference to FIGS.
- a first drift layer 2 made of n-type SiC is formed thereon as a first epitaxial film, and 2) on the upper surface of the first drift layer 2 and on the upper surface of the first drift layer 2 In contact therewith, the second drift layer 3 is formed as a second epitaxial film by an epitaxial crystal growth method under a growth temperature lower than the growth temperature of the first drift layer 2 (FIG. 2).
- Such a series of epitaxial crystal growth steps correspond to the core part of the present embodiment, and will be described in detail later.
- FIG. 3 shows the longitudinal sectional structure of the element after the mask is removed.
- the impurity whose conductivity type is p-type in the second drift layer 3 include boron (B) and aluminum (Al).
- FIG. 4 shows a longitudinal sectional structure of the element after the mask is removed.
- the n-type impurity include phosphorus (P) and nitrogen (N).
- FIG. 5 shows a longitudinal sectional structure of the element after the heat treatment.
- the gate insulating film 6 is formed by thermal oxidation or deposition. Then, after forming a gate electrode 7 on the gate insulating film 6, the gate electrode 7 is patterned as shown in FIG. In the gate electrode 7, the pair of base regions 4 and the pair of source regions 5 are located below both ends of the electrode 7, and a part of the second drift layer 3 located between the pair of base regions 4 is the portion of the electrode 7. It is patterned into a shape that is located directly under the center.
- the remaining part of the gate insulating film 6 on each source region 5 is removed by photolithography technique and etching technique (FIG. 8), and after removal, the source electrode 8 is formed on the part where the source region 5 is exposed. And patterning (FIG. 9). Thereafter, the drain electrode 9 is formed on the back surface side of the SiC substrate 1, thereby completing the main part of the element structure as shown in FIG.
- FIG. 10 is a view showing a temperature profile in the reaction furnace until the first drift layer 2 and the second drift layer 3 shown in FIG. 1 are produced.
- the horizontal axis represents the elapsed time
- the vertical axis represents the temperature in the reactor.
- a carrier gas (H 2 ) is flowed into the reaction furnace, and the temperature rise is started.
- gases of monosilane (SiH 4 ), propane (C 3 H 8 ), and nitrogen (N 2 ) are introduced into the reaction furnace.
- epitaxial growth is started.
- the first epitaxial layer 2 is grown from time t1 to time t2 when a predetermined time has elapsed. Thereafter, the temperature in the reactor is lowered to the growth temperature T2 ( ⁇ T1) of the second epitaxial layer 3.
- the epitaxial growth of the second epitaxial layer 3 is performed within a predetermined time from the time t3 when the temperature in the reactor falls to the growth temperature T2 until the time t4. Then, at the time t4 when the predetermined time has elapsed, the temperature in the reaction furnace is lowered.
- FIG. 11 typical ones (observation results) as crystal defects starting from migration failure are shown in FIG. 11, FIG. 12 and FIG.
- Each of the crystal defects shown in FIGS. 11 to 13 has a triangular shape in plan view.
- the crystal defects shown in FIG. 11 have dents of several tens to several hundreds of nm in the depth direction, and some of the crystal defects shown in FIG. 12 have dents in the depth direction.
- the crystal defect shown in FIG. 13 has a structure in which the entire triangular shape is recessed by several tens of nm in the depth direction.
- a crystal defect based on a migration failure occurs at the interface between the upper surface (main surface) of the SiC substrate having an off angle of 5 degrees or less and the epitaxial film epitaxially grown thereon.
- the density of the crystal defects strongly depends on the film formation conditions of the first epitaxial film. For example, when the first epitaxial film is grown at a growth temperature of 1600 ° C. and then the second epitaxial film is grown at a growth temperature of 1550 ° C., the density of the crystal defects is as follows: The density of the crystal defects is about 1/10 when the epitaxial film is grown at a growth temperature of 1550 ° C. consistently.
- the height of the bunching step when the two-layer epitaxial film is grown under the above growth temperature conditions, the epitaxial film growth is consistently performed at a growth temperature of 1600 ° C. The height of the bunching step is suppressed to about 1 ⁇ 2.
- the above example is a case where the first epitaxial film having a thickness of about 0.5 ⁇ m is laminated on the main surface of the SiC substrate having an off angle of 5 degrees or less.
- the thickness of the first-layer epitaxial film is about 0.2 ⁇ m
- the first-layer epitaxial film of about 0.5 ⁇ m is formed on the SiC substrate with respect to the height of the bunching step.
- the crystal defect density is about 1/3 compared with the crystal defect density when epitaxial growth is consistently performed at a growth temperature of 1550 ° C. Stay on. Nevertheless, even if the thickness of the first epitaxial film is thinner than about 0.5 ⁇ m, the effect of reducing the density of crystal defects can be obtained. On the other hand, in the case where the film thickness of the first epitaxial film is thick, the crystal defect density is sufficiently reduced, but particularly when the film thickness of the first epitaxial film exceeds 1.0 ⁇ m, It is considered that the surface roughness becomes remarkable before the growth of the second-layer epitaxial film, and the height of the bunching step is increased. Considering the above viewpoints, it can be said that the thickness of the first epitaxial film is desirably a value in the range of 0.3 ⁇ m to 0.8 ⁇ m.
- the rate of temperature decrease is desirably set to a value in the range of 5 ° C./min to 30 ° C./min.
- the results of growing the first and second epitaxial films with the C / Si ratio fixed between the first epitaxial film and the second epitaxial film are shown.
- the C / Si ratio of the first epitaxial film is made higher than that of the first epitaxial film
- the C / Si ratio of the first epitaxial film is made higher than that of the first epitaxial film.
- monosilane (SiH 4 ), propane (C 3 H 8 ), and nitrogen are grown during the growth, for example, the growth rate of the second epitaxial film is increased compared to the growth rate of the first epitaxial film.
- the gas flow rate or flow rate ratio of (N 2 ) may be changed.
- the impurity concentration of the SiC substrate is 5 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3
- the impurity concentration of the epitaxial layer serving as the drift layer is 5 ⁇ 10 15 cm depending on the application. It is generally about ⁇ 3 to 5 ⁇ 10 16 cm ⁇ 3 . Therefore, a difference in impurity concentration of 1 ⁇ 10 2 cm ⁇ 3 occurs at the interface between the main surface of the SiC substrate and the epitaxial layer thereon.
- the first epitaxial film is formed on the main surface of the SiC substrate at the growth temperature T1, and the second epitaxial film is continuously formed thereon at the growth temperature T2 ( ⁇ T1).
- the effect of the first epitaxial film functioning as a buffer layer for relaxing the impurity concentration difference of 1 ⁇ 10 2 cm ⁇ 3 is also expected. I can do it.
- the temperature in the reactor is lowered (T1 ⁇ T2) while the growth gas is kept flowing.
- the flow rate of the growth gas may be reduced during this temperature drop period.
- the flow of the growth gas is interrupted during the temperature drop period between the time t2 and the time t3, and the temperature in the reactor
- the propane gas may be cooled before epitaxial growth of the first drift layer 2 (time t01 in FIG. 14) for the purpose of alleviating C desorption from the main surface or the surface of the SiC substrate. May be allowed to flow into the reactor.
- the inflow of monosilane and nitrogen gas is shut off within the period between the growth completion time t2 of the first drift layer 2 and the growth disclosure time t3 of the second drift layer 3, and only propane gas is supplied into the reactor. It may be left as it is.
- the growth temperature of the first epitaxial layer is a temperature at which there are few crystal defects due to poor migration of reactive species and the height of the bunching step is relatively small.
- the growth temperature of the second epitaxial layer is desirably a temperature at which the height of the bunching step is reduced.
- FIG. 18 is a diagram showing the relationship between the growth temperature of the epitaxial layer and the height of the bunching step
- FIG. 19 is a diagram showing the relationship between the growth temperature of the epitaxial layer and the crystal defect density caused by migration failure.
- the growth thickness of the epitaxial layer is about 2 ⁇ m.
- 18 and 19 it can be seen that both the crystal defect density due to migration failure and the bunching step height are small when the growth temperature of the epitaxial layer is in the range of 1550 ° C. to 1650 ° C. It can also be seen that the height of the bunching step is small at a value in the range of 1450 ° C. or more and 1550 ° C. or less.
- the growth temperature of the first epitaxial layer is preferably 1550 ° C. or higher and 1650 ° C. or lower, more preferably 1570 ° C. or higher and 1620 ° C. or lower.
- the growth temperature of the second epitaxial layer is preferably 1450 ° C. or higher and 1550 ° C. or lower, and more preferably 1470 ° C. or higher and 1520 ° C. or lower.
- the direction of the off-angle of the SiC substrate is the ⁇ 11-29> direction.
- the same effect can be obtained when the off angle direction is, for example, the ⁇ 1-100> direction, or when the off angle is formed on the other surface of the SiC substrate.
- an n-type epitaxial layer on an n-type SiC substrate having an off angle of 5 degrees or less is assumed, but if the SiC substrate has an off angle of 5 degrees or less, 1) In each case of forming a p-type epitaxial layer on an n-type SiC substrate, 2) forming a p-type epitaxial layer on a p-type SiC substrate, or 3) forming an n-type epitaxial layer on a p-type SiC substrate.
- the same effect can be obtained by similarly applying the manufacturing method for forming the drift layer composed of the two epitaxial layers under the condition where the growth temperature is T1> T2.
- the drift layer of the semiconductor device when the drift layer of the semiconductor device is formed by the epitaxial layer on the main surface of the SiC substrate in which the off angle of 5 degrees or less is formed, the migration of reactive species is performed.
- the density of crystal defects due to defects can be reduced, and the height of the bunching step can be suppressed to be relatively small.
- the growth temperature of the second epitaxial layer is lower than the growth temperature of the first epitaxial layer, the thermal uniformity is improved and the epitaxial layer thickness and the carrier concentration in-plane distribution are improved. Furthermore, the margin for epitaxial growth between wafers or lots can be increased.
- drift layers 2 and 3 manufactured by the manufacturing method according to the present embodiment, carrier scattering in the channel portion in the SiC semiconductor device can be suppressed.
- FIG. 15 is a longitudinal sectional view showing the structure of a SiC Schottky diode (hereinafter referred to as “SIC-SBD”) according to the present embodiment. A method for manufacturing the SiC-SBD of FIG. 15 will be described below.
- SIC-SBD SiC Schottky diode
- the n-type first epitaxial layer 2 is epitaxially grown at the growth temperature T1.
- the growth temperature T2 is lower than the growth temperature T1 of the first epitaxial layer 2 (see FIG. 10 or FIG. 14).
- the n-type second epitaxial layer 3 is epitaxially grown, and then the surface of the same layer 3 is sacrificial oxidized.
- a photoresist patterning mask (not shown) having a desired pattern is formed on the surface of the n-type second epitaxial layer 3 in order to produce the termination structure 14 for increasing the breakdown voltage.
- impurity ions are implanted from above the mask to form an ion implantation layer that finally becomes the termination structure 14 in the n-type second epitaxial layer 3.
- the mask and the sacrificial oxide film are removed.
- an activation annealing process for activating the implanted impurity atoms is performed to form a p-type (second conductivity type) termination structure 14.
- an ohmic electrode 15 for ohmic junction is formed on the back surface of the SiC substrate, and a Schottky electrode 16 for Schottky junction is formed on the substrate surface composed of the surface of the second epitaxial layer 3 and the surface of the termination structure 14.
- the height of the bunching step is suppressed to be small, and the density of crystal defects due to poor migration of raw materials is reduced.
- the SiC-SBD having the epitaxial layer (2 + 3) is completed.
- FIG. 16 is a longitudinal sectional view showing a structure of a SiC-MOSFET having a SiC substrate having an off angle of 5 degrees or less, which is produced by the manufacturing method according to the present embodiment.
- the SiC-MOSFET in FIG. 16 is structurally different from the SiC-MOSFET in FIG. 1 in that the drift layer is composed of one epitaxial layer 3 and the source region 5 is formed in the surface of the p-type base region 4.
- Two n-type first and second epitaxial layers 10 and 11 are arranged on the surface portion that is not formed and on the surface of the drift layer 3 sandwiched between the opposing surface portions of the pair of base regions 4. It is a point that has been established.
- the first and second epitaxial layers 10 and 11 form a channel portion of the SiC-MOSFET.
- the purpose of the present embodiment is to suppress the height of the bunching step in the first and second epitaxial layers 10 and 11 on the surface of the drift layer 3, and further, the density of the defect lattice caused by the interface between the epitaxial layers. It is to propose a manufacturing method for reducing the above. Hereinafter, the manufacturing method according to the present embodiment will be described with reference to FIG.
- the first drift layer 2 is formed in the processing steps until the n-type source region 5 is formed by activation annealing of ions implanted in the p-type base region 4 in the drift layer 3. Except for the steps to be performed, the process is the same as the process described in the first embodiment. After that, after the activation of the implanted ions, sacrificial oxidation is performed to form the n-type first epitaxial layer 10, and then the first epitaxial layer 10 is directly over and in contact with the surface of the layer 10. The n-type second epitaxial layer 11 is epitaxially grown at a growth temperature lower than the growth temperature of the first epitaxial layer 10.
- a resist mask (not shown) is formed on the first and second epitaxial layers 10 and 11, and the first and second epitaxial layers 10 and 11 are removed except for a portion to become a channel.
- the channel portion has a pair of base region 4 and source region 5 located below both ends of the channel portion, and the portion of the drift layer 3 sandwiched between the opposing base regions 4 is the center of the channel portion. It is patterned into a shape that is located immediately below.
- the gate insulating film 6 is formed by thermal oxidation or deposition.
- a gate electrode 7 is formed directly on the gate insulating film 6 and then patterned.
- a pair of base region 4 and source region 5 are located below both ends of the electrode 7, and a part of the drift layer 3 sandwiched between the opposing base regions 4 is a central portion of the electrode 7. It is patterned into a shape that is located below.
- the remaining part of the gate insulating film 6 on each source region 5 is removed by a photolithography technique and an etching technique, and after the removal, a source electrode 8 is formed on the part where the source region 5 is exposed. Pattern. Further, the drain electrode 9 is formed on the back surface of the SiC substrate 1. The main part of the element structure as shown in FIG. 16 is completed through the above processing steps.
- the first and second epitaxial layers 10 and 11 are formed under the condition of (growth temperature T1 of the first epitaxial layer 10)> (growth temperature T2 of the second epitaxial layer 11). Since the epitaxial growth is performed on the upper surface of the drift layer 3, 1) the density of lattice defects starting from the interface between the drift layer 3, which is an epitaxial layer, and the first epitaxial layer 10 can be reduced; There is an advantage that the height of the bunching step can be suppressed in the two epitaxial layers 11.
- the first and second drift layers 2 and 3 described in the first embodiment can also be applied to the present embodiment. . Thereby, the effect of the first embodiment described above can also be obtained synergistically.
- FIG. 17 is a longitudinal sectional view showing a structure of a SiC-MOSFET having a SiC substrate having an off angle of 5 degrees or less, which is produced by the manufacturing method according to the present embodiment.
- two n-type first and second epitaxial layers 10 and 11 are grown on the drift layer 3 with a carrier concentration different from that of the drift layer 3.
- the second epitaxial layers 10 and 11 are configured as a channel portion of the present SiC-MOSFET.
- the main purpose of the present embodiment is to suppress the height of the bunching step in the first and second epitaxial layers 10 and 11 on the surface of the drift layer 3, and further to provide a defect lattice caused by the interface between the epitaxial layers.
- the object is to propose a manufacturing method for reducing the density.
- the n-type first epitaxial layer 12 is epitaxially grown at a growth temperature T1 with a carrier concentration different from that of the drift layer 3.
- the second epitaxial layer 13 is formed by performing epitaxial growth on the upper surface of the first epitaxial layer 12 at a growth temperature T2 lower than the growth temperature T1 of the first epitaxial layer 12 so as to be in contact with the upper surface.
- the main part of the element structure as shown in FIG. 17 is completed by performing the same process as that after the formation of the drift layer of the first embodiment.
- the first and second epitaxial layers 12 and 13 are drifted under the condition of (growth temperature T1 of first epitaxial layer 12)> (growth temperature T2 of second epitaxial layer 13). Since the epitaxial growth is performed on the upper surface of the layer 3, the density of lattice defects starting from the interface between the drift layer 3 as the epitaxial layer and the first epitaxial layer 12 can be reduced, and 2) the second There is an advantage that the height of the bunching step can be suppressed in the epitaxial layer 13.
- the first and second drift layers 2 and 3 described in the first embodiment can also be applied to the present embodiment. . Thereby, the effect of the first embodiment described above can also be obtained synergistically.
- 1 n-type (corresponding to the first conductivity type) SiC substrate 2 first drift layer made of n-type SiC, 3 second made of n-type SiC epitaxially grown at a lower growth temperature than the first drift layer Drift layer, 4 p-type (corresponding to the second conductivity type) base layer, 5 n-type source region, 6 gate insulating film, 7 gate electrode, 8 source electrode, 9 drain electrode, 10 n-type SiC 1st epitaxial layer, 11 2nd epitaxial layer made of SiC epitaxially grown at a lower growth temperature than the 1st epitaxial layer, 1st epitaxial layer made of 12 n-type SiC, 13 lower than the 1st epitaxial layer A second epitaxial layer made of n-type SiC epitaxially grown at the growth temperature, 14 termination structure, 15 o Mick electrode, 16 Schottky electrode.
Abstract
Description
本実施の形態に係るSiC半導体装置の製造方法の特徴点は、SiC半導体素子(縦型MOSFET又はIGBT等)のドリフト層を作る際に、第1層目のエピタキシャル膜(第1ドリフト層)を成長させて第1ドリフト層を形成し、その上に第1層目のエピタキシャル膜の成長温度よりも低い温度で第2層目のエピタキシャル膜(第2ドリフト層)を成長させることによって当該ドリフト層を形成する点にある。
図15は、本実施の形態に係るSiCショットキダイオード(以下「SIC-SBD」と言う。)の構造を示す縦断面図である。以下に、図15のSiC-SBDの製造方法について記載する。
図16は、本実施の形態に係る製造方法により作成された、オフ角が5度以下のSiC基板を有するSiC-MOSFETの構造を示す縦断面図である。図16のSiC-MOSFETが図1のSiC-MOSFETと構造上相違する点は、ドリフト層が1層のエピタキシャル層3より成り、p型のベース領域4の表面の内でソース領域5が形成されていない表面部分上と、一対のベース領域4の対向する当該表面部分同士で挟まれたドリフト層3の表面上とに、2層のn型の第1及び第2エピタキシャル層10,11が配設されている点である。図16に於いては、第1及び第2エピタキシャル層10,11がSiC-MOSFETのチャネル部を成す。
図17は、本実施の形態に係る製造方法により作成された、オフ角が5度以下のSiC基板を有するSiC-MOSFETの構造を示す縦断面図である。図17に示されるSiC-MOSFETでは、ドリフト層3上にドリフト層3とは異なるキャリア濃度で2層のn型の第1及び第2エピタキシャル層10,11を成長させ、これらn型の第1及び第2エピタキシャル層10,11を本SiC-MOSFETのチャネル部として構成している。本実施の形態の主目的は、ドリフト層3の表面上の第1及び第2エピタキシャル層10,11内のバンチングステップの高さを抑制する、さらにはエピタキシャル層同士の界面に起因する欠陥格子の密度を低減化するための製造方法を提案することにある。
Claims (9)
- オフ角を有する炭化珪素半導体基板(1)の主面上に、第1エピタキシャル層(2,10,12)を成長させる工程と、
前記第1エピタキシャル層の上面上であって且つ前記第1エピタキシャル層の前記上面と接して、前記第1エピタキシャル層の成長温度よりも低い成長温度で第2エピタキシャル層(2,11,13)を成長させる工程とを、
備えることを特徴とする、
炭化珪素半導体装置の製造方法。 - 請求項1記載の炭化珪素半導体装置の製造方法であって、
前記炭化珪素半導体基板の前記オフ角は5度以下である、
炭化珪素半導体装置の製造方法。 - 請求項1記載の炭化珪素半導体装置の製造方法であって、
前記第1エピタキシャル層は、前記炭化珪素半導体基板の前記主面と接してエピタキシャル成長されることを特徴とする、
炭化珪素半導体装置の製造方法。 - 請求項3記載の炭化珪素半導体装置の製造方法であって、
前記第1及び第2エピタキシャル層は、当該炭化珪素半導体装置のドリフト層(2,3)として用いられる、
炭化珪素半導体装置の製造方法。 - 請求項3記載の炭化珪素半導体装置の製造方法であって、
前記第2エピタキシャル層上にショットキー接合する電極(16)を形成する工程をさらに備える、
炭化珪素半導体装置の製造方法。 - 請求項1記載の炭化珪素半導体装置の製造方法であって、
前記第1エピタキシャル層(10)は、前記炭化珪素半導体基板の前記主面と接して配設されたエピタキシャル層であるドリフト層の上面と接してエピタキシャル成長されることを特徴とする、
炭化珪素半導体装置の製造方法。 - 請求項6記載の炭化珪素半導体装置の製造方法であって、
前記第1及び第2エピタキシャル層は、当該炭化珪素半導体装置のチャネル部(10,11,12,13)として用いられる、
炭化珪素半導体装置の製造方法。 - 請求項1記載の炭化珪素半導体装置の製造方法であって、
前記第1エピタキシャル層の成長温度は、1570℃以上1620℃以下である、
炭化珪素半導体装置の製造方法。 - 請求項1記載の炭化珪素半導体装置の製造方法であって、
前記第2エピタキシャル層の成長温度は、1470℃以上1520℃以下である、
炭化珪素半導体装置の製造方法。
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JP2015213102A (ja) * | 2014-05-01 | 2015-11-26 | 信越半導体株式会社 | エピタキシャルウェーハの製造方法 |
WO2015170500A1 (ja) * | 2014-05-08 | 2015-11-12 | 三菱電機株式会社 | SiCエピタキシャルウエハおよび炭化珪素半導体装置の製造方法 |
JPWO2015170500A1 (ja) * | 2014-05-08 | 2017-04-20 | 三菱電機株式会社 | SiCエピタキシャルウエハおよび炭化珪素半導体装置の製造方法 |
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JP2017183589A (ja) * | 2016-03-31 | 2017-10-05 | 住友電気工業株式会社 | 炭化珪素半導体基板および半導体装置の製造方法 |
JP2018006384A (ja) * | 2016-06-27 | 2018-01-11 | 昭和電工株式会社 | SiCエピタキシャルウェハの製造方法 |
JP2020178141A (ja) * | 2019-04-03 | 2020-10-29 | 住友電気工業株式会社 | 半導体装置 |
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DE112010000953T5 (de) | 2012-07-26 |
JPWO2010101016A1 (ja) | 2012-09-06 |
JP5393772B2 (ja) | 2014-01-22 |
DE112010000953B4 (de) | 2017-08-24 |
CN102341893A (zh) | 2012-02-01 |
KR20110116203A (ko) | 2011-10-25 |
US20110312161A1 (en) | 2011-12-22 |
US8569106B2 (en) | 2013-10-29 |
CN102341893B (zh) | 2015-03-25 |
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