WO2009081723A1 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
WO2009081723A1
WO2009081723A1 PCT/JP2008/072314 JP2008072314W WO2009081723A1 WO 2009081723 A1 WO2009081723 A1 WO 2009081723A1 JP 2008072314 W JP2008072314 W JP 2008072314W WO 2009081723 A1 WO2009081723 A1 WO 2009081723A1
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WIPO (PCT)
Prior art keywords
connection conductor
semiconductor chip
circuit pattern
insulating resin
semiconductor device
Prior art date
Application number
PCT/JP2008/072314
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English (en)
French (fr)
Inventor
Junji Tsuruoka
Kazuo Aoki
Masaki Ono
Katsuhiko Yoshihara
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Fuji Electric Device Technology Co., Ltd.
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Publication date
Application filed by Fuji Electric Device Technology Co., Ltd. filed Critical Fuji Electric Device Technology Co., Ltd.
Priority to JP2009547019A priority Critical patent/JP5183642B2/ja
Priority to CN2008801209553A priority patent/CN101933139B/zh
Priority to DE112008003425.7T priority patent/DE112008003425B4/de
Publication of WO2009081723A1 publication Critical patent/WO2009081723A1/ja
Priority to US12/801,603 priority patent/US8710666B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Definitions

  • the present invention relates to a semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor) and a PIM (Power Integrated Module), and a manufacturing method thereof.
  • a semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor) and a PIM (Power Integrated Module)
  • FIG. 9 is a cross-sectional view of a main part of a conventional semiconductor device.
  • a conventional assembly process of the semiconductor device will be described.
  • the back surface copper foil 3 and the copper base 1 of the insulated circuit board composed of the back surface copper foil 3, the ceramic 4, the circuit pattern 5 and the circuit pattern 6 are joined by the solder 2, and the circuit pattern 5 and the semiconductor chip 8 are joined by the solder 7.
  • the semiconductor chip 8 is a switching element such as an IGBT or FWD (Free Wheeling Diode).
  • solder joints are performed in a single heating step. Thereafter, an emitter electrode (not shown) on the upper portion of the semiconductor chip 8 and the circuit pattern 6 are connected by a bonding wire 9 (such as an aluminum wire) by ultrasonic vibration.
  • a bonding wire 9 such as an aluminum wire
  • the terminal case 10 in which the external terminal 11 is insert-molded and the copper base 1 are heat-bonded with a silicone adhesive (not shown).
  • the circuit pattern 5 and the external terminal 11 and the circuit pattern 6 and the external terminal 11 are spot laser welded.
  • the laser beam irradiation position in the laser welding is above the external terminal 11.
  • a resin (not shown) is filled to cover the surface of the semiconductor chip 8. In this way, a conventional semiconductor device is manufactured.
  • Patent Document 1 a semiconductor element mounting substrate formed by bonding a substrate on which a wiring pattern for mounting a semiconductor element is formed and a lead by laser, and a leading end portion of the lead to be bonded to an electrode pad of the substrate Is formed thinner than other portions of the lead.
  • Patent Document 2 a resin sealing body, a first semiconductor chip and a second semiconductor chip which are located inside the resin sealing body and have electrodes formed on the front and back surfaces, and the resin sealing A first lead that extends over the inside and outside of the stopper and is electrically connected to the electrode of the first semiconductor chip, the first lead, and the inside and outside of the resin sealing body.
  • the laser welding shown in FIG. 9 is performed before the resin 17 is coated.
  • circuit patterns 5 and 6 (including wiring patterns not shown) formed on the insulating substrate (ceramics 4) by the spattered spatter 21 are short-circuited, or bonding wires 9 are bonded.
  • the wiring such as is cut (fused), or the semiconductor chip 8 is damaged.
  • the spatter is scattered, resulting in poor insulation of the insulating substrate, short circuit between circuit patterns, disconnection of the wire wiring, physical damage to the semiconductor chip (melting marks, fine scratches, micro cracks, etc.) and the electrical properties of the semiconductor chip. Cause poor electrical characteristics (short circuit, etc.).
  • An object of the present invention is to solve the above-mentioned problems and prevent a spatter generated by laser welding from adhering to a circuit pattern or a semiconductor chip, thereby preventing deterioration of electrical characteristics and its manufacture. It is to provide a method.
  • a circuit pattern formed on an insulating substrate, a semiconductor chip fixed on the circuit pattern, a connection conductor fixed to at least one of the circuit pattern or the semiconductor chip, and a welded portion of the connection conductor The circuit pattern, an insulating resin covering the semiconductor chip, and an external terminal for supplying a main current to the main electrode of the semiconductor chip and joining the welded portion of the connection conductor by laser welding.
  • connection conductor An upper insulating resin that covers the exposed portion of the connection conductor and the external terminal is provided on the insulating resin.
  • the upper insulating resin covering the exposed portion of the connection conductor, the external terminal, and the external connection conductor is provided on the insulating resin.
  • the semiconductor chip has one or a plurality of signal electrodes in addition to the main electrode, and the insulating resin covers at least a bonding wire that connects the signal electrode and a signal terminal led out to the outside. It is good to be.
  • connection conductor may have a bent structure in which the fixed surface and the welded portion are positioned with a space therebetween.
  • the circuit pattern, a coating step of coating the semiconductor chip with an insulating resin, and subsequent to the coating step, an external terminal for supplying a main current to the main electrode of the semiconductor chip is laser welded to the welding portion of the connection conductor
  • a semiconductor comprising: a step of joining an external connection conductor by laser welding; and a filling step of filling an upper insulating resin covering the exposed portion of the connection conductor, the external terminal, and the external connection conductor on the insulating resin. It is set as the manufacturing method of an apparatus.
  • the insulating resin is a curable resin
  • the covering step includes a step of curing the curable resin, and a removing step of removing foreign matters on the surface of the insulating resin before the filling step.
  • the insulating resin and the upper layer insulating resin are curable resins, and the semiconductor device manufacturing method includes a curing step of simultaneously curing the insulating resin and the upper layer insulating resin after the filling step.
  • At least a part of signal terminals that conduct to the signal electrodes of the semiconductor chip or bonding wires that conduct to the signal terminals are covered with the insulating resin.
  • the filling of the insulating resin is performed in two portions, the first filling is performed below the upper surface of the lower member to be laser welded, laser welding is performed in that state, and then further addition is performed.
  • Filling the insulation resin can cause physical damage (scratches, cracks, cutting, etc.) to circuit patterns, semiconductor chips, and bonding wires even when spatter is scattered during laser welding. Therefore, it is possible to prevent deterioration of electrical characteristics (decrease in breakdown voltage, non-conduction due to disconnection).
  • FIG. 1 is a cross-sectional view of main parts of a semiconductor device according to a first embodiment of the present invention.
  • the principal part sectional view showing the modification of the semiconductor device of the 1st example.
  • the principal part sectional drawing which shows another modification of the semiconductor device of 1st Example.
  • FIGS. 2A and 2B are cross-sectional views of a main part manufacturing process illustrating a method for manufacturing the semiconductor device of FIG. 1, in which FIGS. It is a block diagram of the A section when the distance between the terminal case and the connection conductor is large, in which FIG. (A) is a diagram when the external terminal is extended, and (b) is a diagram when the external connection conductor is used. Sectional drawing of the principal part of the semiconductor device of 2nd Example of this invention.
  • FIG. 1 is a cross-sectional view of main parts of a semiconductor device according to a first embodiment of the present invention.
  • the principal part sectional view showing the modification of the semiconductor device of the 1st example.
  • FIG. 4 is a configuration diagram of a semiconductor device according to a third embodiment of the present invention, in which (a) is a cross-sectional view of the main part and (b) is a cross-sectional view of the main part taken along line YY of (a).
  • FIG. 10 is a main part configuration diagram of a semiconductor device according to a fourth embodiment of the present invention, where (a) is a main part sectional view, (b) is a main part sectional view taken along line YY of (a), and (c).
  • (d) is principal part sectional drawing from which the structure of C part of (a) differs. Sectional drawing of the principal part of the conventional semiconductor device. The figure which shows a mode that a spatter disperses.
  • FIG. 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment of the present invention.
  • the basic structure is the same as that of the conventional semiconductor device shown in FIG. 9 except that the connection conductor 14 is inserted between the circuit pattern 5 and the external terminal 11 and between the circuit pattern 6 and the external terminal 11. This is the point.
  • a backside copper foil 3 and copper of an insulating circuit board comprising a ceramic 4 (insulating substrate), a backside copper foil 3 formed on the back side of the ceramics 4, and a circuit pattern 5 and a circuit pattern 6 formed on the front side of the ceramics 4.
  • the base 1 is joined with the solder 2, and the circuit pattern 5 and the semiconductor chip 8 are joined with the solder 7. Further, the block-shaped connection conductor 14 is joined to the circuit pattern 5 and the circuit pattern 6 with the solder 13.
  • the joining by the solder 2 and the solder 13 may be ultrasonic joining.
  • an emitter electrode (not shown) on the top of the semiconductor chip 8 and the circuit pattern 6 are connected by a bonding wire 9 (aluminum wire or the like) by ultrasonic vibration.
  • a bonding wire 9 aluminum wire or the like
  • the terminal case 10 in which the external terminals 11 are insert-molded and the copper base 1 are heat-bonded with a silicone adhesive (not shown).
  • the resin 17a is filled so that the upper surface P of the connection conductor 14 is exposed and the bonding wire 9 is buried (see FIG. 4A).
  • connection conductor 14 and the external terminal 11 are spot laser welded.
  • the laser beam irradiation position in the laser welding is above the external terminal 11.
  • a metal that can be easily joined to the circuit pattern and easily welded to the external terminal 11 is selected.
  • a metal that is easy to laser weld to the connection conductor 14 is selected. From the viewpoint of flowing the main current to the outside, it is desirable that the conductivity is good, and copper or a copper alloy is preferable. Further, nickel plating or the like may be applied to the surface in consideration of bondability.
  • the external terminal 11 is irradiated with a laser, and the external terminal 11 and the connection conductor 14 are welded at the welded portion 12.
  • the external terminal 11 is melted by laser irradiation, and a part of the external terminal 11 is spattered 21 and scattered.
  • the scattered spatter adheres onto the resin 17a.
  • the resin 17b is filled as an upper layer insulating resin (see FIG. 4B).
  • the resin 17a and the resin 17b are silicone gel or epoxy resin, and both are resins of the same material.
  • the resin 17a may remain in a liquid state during laser welding or may be in a cured state. Further, both resins may be made of different materials.
  • a step of removing the spatter 21 adhering to the resin 17a may be added. For example, air is blown onto the resin 17a to remove the spatter 21. If the resin 17a is cured before the laser irradiation, it becomes easy to remove the spatter 21 by air or the like.
  • the spatter 21 adheres onto the resin 17a, and the resin 17a serves as a mask, so that the spatter 21 does not reach the circuit pattern 5, the circuit pattern 6, etc., the semiconductor chip 8, and the bonding wire 9, so that they are not damaged.
  • spatter 21 prevents physical damage (scratches, cracking, cutting, etc.) to the circuit patterns 5, 6, the semiconductor chip 8, and the bonding wire 9. It is possible to prevent deterioration of electrical characteristics (decrease in breakdown voltage, non-conduction due to disconnection).
  • FIG. 2 shows a modification of the semiconductor device of the first embodiment.
  • FIGS. 1A and 1B show cross-sections of main parts in the order of processes.
  • the semiconductor chip 8 has one or a plurality of signal electrodes on the main surface of the semiconductor chip 8 on which the main electrode is disposed.
  • a signal bonding wire 90 for connecting the signal electrode to the signal terminal 11 ′ is connected. As shown in FIG. 5A, at least a part of the signal terminal 11 'that conducts to the signal electrode of the semiconductor chip 8 or a bonding wire 90 that conducts to the signal terminal 11' is covered with a resin 17a.
  • the bonding wires 9 for flowing the main current are usually thicker than the bonding wires 90 connected to the signal electrodes, and a plurality of bonding wires 9 are connected to one main electrode.
  • the thickness and number of the bonding wires 9 are selected depending on the magnitude of the current flowing through the main electrode or the magnitude of the current that can be passed per bonding wire.
  • a thin wire is used for the bonding wire 90 connected to the signal electrode because a large current does not flow and the signal electrode is small as in the bonding wire 9 connected to the main electrode.
  • the resin 17a desirably covers all the bonding wires. Since the bonding wire 9 through which the main current flows is thicker and more rigid than the bonding wire 90 connected to the signal electrode, it is less susceptible to the impact of the sputter 21 than the bonding wire 90 connected to the signal electrode. In addition, since a plurality of adjacent bonding wires 9 are connected in parallel, even if the sputter 21 adheres to the bonding wires 9, it is not easily affected by a short circuit.
  • the filling height of the resin 17a is at least a height that covers the bonding wire 90 connected to the signal electrode. .
  • the position H of the welded portion 12 is determined so as to have this height, as shown in FIG. 2, the height of the semiconductor device can be reduced.
  • the bonding wire 90 connected to the signal electrode can be reliably protected from the sputter 21.
  • the connecting conductor 14 is joined to the surface of the circuit pattern 5 and the surface of the circuit pattern 6 with the solder 13 as described above.
  • the solder bonding between the connection conductor 14 and the circuit pattern 5 and the circuit pattern 6 can be performed in the same process as the solder bonding between the copper base 1 and the back surface copper foil and the solder bonding between the circuit pattern 5 and the semiconductor chip 8. .
  • the connecting conductor 14 can be soldered without newly increasing the soldering process.
  • the external terminal 11 and the connection conductor 14 are spot laser welded.
  • the thickness of the connection conductor 14 used here is equal to or greater than the thickness of the external terminal 11, so that the circuit pattern 5 and the circuit pattern 6 of the insulated circuit board where the welded portion 12 is located below the connection conductor 14 or a circuit (not shown). Without reaching a circuit pattern such as wiring, stable and strong joining by laser welding with high reliability can be realized.
  • FIG. 3 shows another modification of the semiconductor device of the first embodiment.
  • FIG. 3 shows a cross-sectional view of the main part of the semiconductor device around the signal terminal 11 ′.
  • the copper base 1 is not displayed.
  • the signal terminal 11 ′ molded (sealed) integrally with the terminal case 10 and the signal electrode of the semiconductor chip 8 are electrically connected directly through the bonding wire 90. Has been.
  • a circuit pattern 5 ′ different from the circuit pattern 5 is provided on the ceramic 4 and the circuit pattern 5 ′ and the signal electrode of the semiconductor chip 8 are directly connected to the bonding wire. 90 is electrically connected. Then, the signal terminal 11 ′ formed integrally with the terminal case 10 and the circuit pattern 5 ′ are electrically connected through the bonding wire 91.
  • the signal terminal 11 ′ may be joined to the circuit pattern 5 ′ via the solder 13. Then, the signal terminal 11 ′ and the signal electrode of the semiconductor chip 8 may be electrically connected directly through the bonding wire 90.
  • FIG. 4 is a process for explaining the manufacturing method of the semiconductor device of FIG. 1, and FIG. 4A and FIG. 4B are cross-sectional views of the main part manufacturing process shown in the order of the processes. The process is described with reference to FIG.
  • the spatter 21 generated during laser welding adheres to the surface of the resin 17a and does not adhere to the circuit patterns 5 and 6 and the semiconductor chip 8. As a result, deterioration of electrical characteristics is prevented. After that, since the resin 17b is filled, the sputter 21 is mixed into the resin 17 at the interface between the resin 17a and the resin 17b, and the spatter 21 is scattered at this interface.
  • FIGS. 5A and 5B are configuration diagrams of part A when the distance between the terminal case and the connection conductor is large.
  • FIG. 5A is a diagram in the case where the external terminal is extended
  • FIG. 5B is a diagram in which the external connection conductor is used.
  • FIG. As shown in the figure, when the distance between the terminal case 10 and the connection conductor 14 is large, the external terminal 11 is extended to the connection conductor 14 as shown in FIG. Thus, the external connection conductor 19 may be used to bridge the external terminal 11 and the connection conductor 14.
  • FIG. 6 is a cross-sectional view of the main part of the semiconductor device according to the second embodiment of the present invention.
  • the shape of the connection conductor for spot laser welding with the external terminal 11 is a U-shaped connection conductor 15.
  • the U-shape is referred to because it is a shape in which the letter “U” is tilted sideways.
  • the surface solder-bonded to the circuit pattern 5 and the surface (P) to be welded at the welded portion 12 are connected to each other with a portion (connecting portion) rising from the circuit pattern surface with a space therebetween.
  • connection conductor 15 U-shaped
  • the upper flat plate portion P bends and the connecting conductor 15 and the external terminal 11 are firmly adhered to each other on the laser welding surface, and good laser welding can be performed.
  • the U-shaped upper flat plate portion a melts and penetrates through the center of the welded portion 12 during laser welding. Holes may be formed. In that case, the laser beam is irradiated to the U-shaped lower flat plate portion b through the through hole.
  • the energy of the laser beam is weakened and the lower flat plate portion b of the U shape is not melted.
  • the U-shaped connection conductor 15 it is possible to prevent the welded portion 12 from reaching the circuit pattern 5 and the circuit pattern 6 of the insulated circuit board. Therefore, it is possible to realize stable and strong bonding by highly reliable laser welding.
  • the resin 17a is filled so as to cover the bonding wire 9 below the surface (upper surface P) of the U-shaped upper flat plate portion before laser welding as in the first embodiment, and laser welding is performed.
  • the resin 17b is filled again on the resin 17a.
  • FIGS. 7A and 7B are configuration diagrams of a semiconductor device according to a third embodiment of the present invention.
  • FIG. 7A is a cross-sectional view of the main part, and FIG. 7B is cut along the YY line of FIG. It is principal part sectional drawing.
  • the difference from the case of FIG. 1 and FIG. 6 is that the shape of the connection conductor is an ⁇ -type connection conductor 16 having an ⁇ shape.
  • the term “ ⁇ type” is used because it resembles a letter with a shape of ⁇ .
  • the surface that is solder-bonded to the circuit pattern 5 and the surface (P) that is welded by the welded portion 12 are connected by a portion (connecting portion) that rises from the circuit pattern surface with a space therebetween.
  • the ⁇ -type connection conductor 16 is fixed to the external terminal 11 with a welded portion 12 by laser welding. Before this laser welding, the resin 17a is filled so as to be positioned below the upper flat surface (upper surface P) of the ⁇ -type connecting conductor 16. This prevents damage and defects due to the spatter 21. After the laser welding, the resin 17b is filled on the resin 17a.
  • the ⁇ -type connection conductor 16 is joined to the circuit pattern 5 and the circuit pattern 6 by the solder 13. Similarly in this case, the thin circuit pattern 5 and the circuit pattern 6 and the thick external terminal 11 are not welded, and the thick ⁇ -type connection conductor 16 is inserted between them, which is the same as the case where the U-shaped connection conductor is inserted. In addition, it is possible to prevent the welded portion 12 from reaching the circuit pattern 5 and the circuit pattern 6 of the insulated circuit board. Therefore, it is possible to realize stable and strong bonding by highly reliable laser welding. In this case, the thickness of the ⁇ -type connection conductor 16 is equal to or greater than the thickness of the external terminal 11.
  • connection conductor 14 bonded to the circuit pattern or the semiconductor chip and the surface to be laser-welded.
  • a similar effect can be obtained by providing a space in the space and positioning the space on the extension of the optical path of the laser beam.
  • a part of the side wall of the cylinder or the quadrangular column may be cut to form a slit-like opening (not shown).
  • a square pipe having a square shape in section may be cut, one surface may be soldered to the circuit pattern 5 or the circuit pattern 6, and the external terminal 11 may be spot laser welded to the opposite surface.
  • This square pipe can be prepared inexpensively because it is only necessary to cut a long pipe. Further, since the cross section is a square shape, there is a gap on the extension of the optical path of the laser beam, and the same effect can be obtained.
  • FIGS. 8A and 8B are main part configuration diagrams of a semiconductor device according to a fourth embodiment of the present invention.
  • FIG. 8A is a cross-sectional view of the main part
  • FIG. 8B is a YY line of FIG. Cross-sectional view of the cut main part
  • FIG. 10C is a cross-sectional view of the main part in which the structure of the B part in FIG. 11A is different
  • FIG. 14D is a main part in which the structure of the C part of FIG. It is sectional drawing.
  • This figure shows a case where two semiconductor chips are connected by an ⁇ -type connection conductor 20 and the ⁇ -type connection conductor 20 and the external connection conductor 19 (lead frame) are laser-welded.
  • FIG. 8A is a cross-sectional view of the main part
  • FIG. 8B is a YY line of FIG.
  • FIG. 10C is a cross-sectional view of the main part in which the structure
  • FIG. 2B shows a state in which two semiconductor chips 8 (for example, an IGBT chip and a diode chip) are fixed by solder 13 at two feet of the ⁇ -type connecting conductor 20.
  • FIG. 3C shows the case where the external terminal is embedded in the terminal case and the portion connected to the bonding wire 9 is exposed from the terminal case 10.
  • a normal case structure has a structure as shown in FIG.
  • the ⁇ -type connection conductor 20 is fixed to the external connection conductor 19 (a metal plate or lead frame connected to the external terminal 11) with a welded portion 12 by laser welding.
  • the resin 17a is filled so as to be positioned below the upper flat surface (upper surface P) of the ⁇ -type connecting conductor 20. This prevents damage and defects due to the spatter 21.
  • the resin 17b is filled on the resin 17a.
  • a pad 22 (such as a gate pad) formed on the external terminal 11 and the ceramic 4 is connected by a bonding wire 9, and the bonding wire 9 is buried in a resin 17a.
  • the external connection conductor 19 connects the ⁇ -type connection conductor 20 and the external terminal 11, but the external connection conductor 19 is not used as shown in FIG. You may extend to the mold connection conductor 20 and connect the ⁇ connection conductor 20 directly with the external terminal 11.
  • connection conductor 14 U-shaped connection conductor 15, ⁇ -type connection conductors 16 and 20, and connection conductors such as a square pipe (not shown) may be a low electrical resistance material (a material having a high electrical conductivity). It is preferable to use a copper / copper alloy. In addition, although an aluminum wire is bonded to the upper side of the semiconductor chip 8, there is a case of wiring by a lead frame.
  • the wavelength of the laser beam used for the spot laser welding is preferably 0.19 ⁇ m to 10.6 ⁇ m.

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Abstract

　レーザ溶接で発生するスパッタが回路パターンや半導体チップに付着するのを防止して、電気的特性の劣化を防ぐことができる半導体装置およびその製造方法を提供する。 　セラミックス（４）上に形成した銅箔に接続導体（１４）をはんだ（１３）で固着し、この接続導体（１４）の上部面（Ｐ）より低く樹脂（１７ａ）を充填してレーザ溶接し、その後で樹脂（１７ｂ）を充填することでレーザ溶接で発生するスパッタ（２１）が回路パターン（５），（６）や半導体チップ（８）に付着するのを防止する。それによって電気的特性劣化を防止することができる。

Description

半導体装置およびその製造方法
　この発明は、ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）やＰＩＭ（Ｐｏｗｅｒ　Ｉｎｔｅｇｒａｔｅｄ　Ｍｏｄｕｌｅ）などの半導体装置およびその製造方法に関する。
　図９は、従来の半導体装置の要部断面図である。従来の半導体装置の組立て工程について説明する。裏面銅箔３、セラミックス４、回路パターン５および回路パターン６からなる絶縁回路基板の裏面銅箔３と銅ベース１をはんだ２により接合し、回路パターン５と半導体チップ８をはんだ７により接合する。半導体チップ８はスイッチング素子であるＩＧＢＴやＦＷＤ（Ｆｒｅｅ　Ｗｈｅｅｌｉｎｇ　Ｄｉｏｄｅ）などである。
　通常、これらのはんだ接合は、１回の加熱工程にて行われる。この後、半導体チップ８の上部の図示しないエミッタ電極と回路パターン６とを超音波振動にてボンディングワイヤ９（アルミワイヤなど）にて接続する。
　次に、外部端子１１がインサート成型された端子ケース１０と銅ベース１とを図示しないシリコーン系接着剤にて加熱接着する。この後、回路パターン５と外部端子１１および回路パターン６と外部端子１１とをスポットレーザ溶接する。この場合のレーザ溶接におけるレーザ光の照射位置は、外部端子１１の上側である。その後、図示しない樹脂を充填し半導体チップ８の表面を被覆する。このようにして、従来の半導体装置を作製する。
　また、特許文献１において、半導体素子を搭載するための配線パターンを形成した基板とリードとをレーザにより接合してなる半導体素子搭載用基板であって、基板の電極パッドと接合するリードの先端部分がリードの他の部分より薄く形成されていることが開示されている。
　また、特許文献２において、樹脂封止体と、前記樹脂封止体内部に位置し、表裏面のうち表面に電極が形成された第１の半導体チップおよび第２の半導体チップと、前記樹脂封止体の内外に亘って延在し、前記第１の半導体チップの電極に電気的に接続される第１のリードと、前記第１のリードと、前記樹脂封止体の内外に亘って延在し、前記第２の半導体チップの電極に電気的に接続される第２のリードとを有する半導体装置の製造方法であって、前記第１のリード、第２のリードの各々を重ね合わせた状態で前記樹脂封止体を形成した後、前記第１のリード、第２のリードの各々をレーザ溶接することで、飛び散ったスパッタが半導体チップの回路形成面に飛来するのを防止することが開示されている。
特開平７－９４８４５号公報 特開２００６－７４０７３号公報
　前記の図９に示すレーザ溶接は、樹脂１７を被覆する前に行う。このレーザ溶接を行うと、図１０に示すように、飛散したスパッタ２１が絶縁基板（セラミックス４）に形成した回路パターン５、６（図示しない配線パターンも含む）などを短絡したり、ボンディングワイヤ９などの配線を切断（溶断）したり、半導体チップ８を損傷したりする。
　つまりスパッタが飛散することで、絶縁基板の絶縁不良、回路パターン同士の短絡、ワイヤ配線の断線、半導体チップへの物理的なダメージ（溶融痕、微細なキズ、マイクロクラックなど）および半導体チップの電気的特性不良（短絡など）を起こす。
　この発明の目的は、前記の課題を解決して、レーザ溶接で発生するスパッタが回路パターンや半導体チップに付着するのを防止して、電気的特性の劣化を防ぐことができる半導体装置およびその製造方法を提供することにある。
　前記の目的を達成するために、
　（１）絶縁基板上に形成された回路パターンと、前記回路パターン上に固着された半導体チップと、前記回路パターンもしくは前記半導体チップの少なくとも一方に固着された接続導体と、前記接続導体の溶接部を露出させ、前記回路パターン、前記半導体チップを被覆した絶縁樹脂と、前記半導体チップの主電極に主電流を流し、前記接続導体の前記溶接部にレーザ溶接で接合された外部端子と、からなる構成とする。
　（２）前記絶縁樹脂上に、前記接続導体の露出部と前記外部端子を被覆する上層絶縁樹脂を備えた構成とする。
　（３）絶縁基板上に形成された回路パターンと、前記回路パターン上に固着された半導体チップと、前記回路パターンもしくは前記半導体チップの少なくとも一方に固着された接続導体と、前記接続導体の溶接部を露出させ、前記回路パターン、前記半導体チップを被覆した絶縁樹脂と、前記半導体チップの主電極に主電流を流す外部端子と、該外部端子と前記接続導体の前記溶接部とにそれぞれレーザ溶接で接合された外部接続導体と、からなる構成とする。
　（４）前記絶縁樹脂上に、前記接続導体の露出部と前記外部端子と前記外部接続導体とを被覆する上層絶縁樹脂を備えた構成とする。
　（５）前記半導体チップは、前記主電極の他に１または複数の信号電極を有し、前記絶縁樹脂は、少なくとも前記信号電極と外部に導出する信号端子とを接続するボンディングワイヤを被覆しているとよい。
　（６）前記接続導体は、前記固着した面と前記溶接部とが、空間を隔てて位置する屈曲構造であるとよい。
　（７）絶縁基板上に形成された回路パターンに半導体チップを固着する工程と、前記回路パターンもしくは前記半導体チップの少なくとも一方に接続導体を固着する工程と、前記接続導体の溶接部を露出させ、前記回路パターン、前記半導体チップを絶縁樹脂にて被覆する被覆工程と、前記被覆工程に続いて、前記半導体チップの主電極に主電流を流す外部端子を、前記接続導体の前記溶接部にレーザ溶接で接合する工程と、前記絶縁樹脂上に、前記接続導体の露出部と前記外部端子を被覆する上層絶縁樹脂を充填する充填工程と、を含む半導体装置の製造方法とする。
　（８）絶縁基板上に形成された回路パターンに半導体チップを固着する工程と、前記回路パターンもしくは前記半導体チップの少なくとも一方に接続導体を固着する工程と、前記接続導体の溶接部を露出させ、前記回路パターン、前記半導体チップを絶縁樹脂にて被覆する被覆工程と、前記被覆工程に続いて、前記半導体チップの主電極に主電流を流す外部端子と、前記接続導体の前記溶接部とにそれぞれ外部接続導体をレーザ溶接で接合する工程と、前記絶縁樹脂上に、前記接続導体の露出部と前記外部端子と前記外部接続導体とを被覆する上層絶縁樹脂を充填する充填工程と、を含む半導体装置の製造方法とする。
　（９）前記絶縁樹脂は、硬化性樹脂であって、前記被覆工程は、前記硬化性樹脂を硬化させる工程を含み、前記充填工程の前に、前記絶縁樹脂の表面の異物を除去する除去工程を有する半導体装置の製造方法とする。
　（１０）前記絶縁樹脂および上層絶縁樹脂は、硬化性樹脂であって、前記充填工程に続いて、前記絶縁樹脂および前記上層絶縁樹脂を同時に硬化する硬化工程を有する半導体装置の製造方法とする。
　（１１）前記半導体チップの信号電極に導通する信号端子の少なくとも一部もしくは前記信号端子に導通するボンディングワイヤを、前記絶縁樹脂により被覆する。
　この発明によれば、絶縁樹脂の充填を２度に分けて行い、一回目の充填をレーザ溶接する下の部材の上部面より下になるようにし、その状態でレーザ溶接し、その後さらに追加の絶縁樹脂を充填することで、レーザ溶接時に発生するスパッタの飛散があっても、このスパッタにより回路パターンや半導体チップおよびボンディングワイヤなどが物理的な損傷（キズ、ワレ、切断など）を受けることがなく、電気的特性の劣化（耐圧低下、断線による非導通）を防止できる。
　本発明の上記および他の目的、特徴および利点は本発明の例として好ましい実施の形態を表す添付の図面と関連した以下の説明により明らかになるであろう。
この発明の第１実施例の半導体装置の要部断面図。 第１実施例の半導体装置の変形例を示す要部断面図。 第１実施例の半導体装置の別の変形例を示す要部断面図。 図１の半導体装置の製造方法を示す図であり、（ａ）および（ｂ）は工程順に示した要部製造工程断面図。 端子ケースと接続導体の距離が大きい場合のＡ部の構成図であり、同図（ａ）は外部端子を伸ばした場合の図、同図（ｂ）は外部接続導体を用いた場合の図。 この発明の第２実施例の半導体装置の要部断面図。 この発明の第３実施例の半導体装置の構成図であり、（ａ）は要部断面図、（ｂ）は（ａ）のＹ－Ｙ線で切断した要部断面図。 この発明の第４実施例の半導体装置の要部構成図であり、（ａ）は要部断面図、（ｂ）は（ａ）のＹ－Ｙ線で切断した要部断面図、（ｃ）は（ａ）のＢ部の構造が異なる要部断面図、（ｄ）は（ａ）のＣ部の構造が異なる要部断面図。 従来の半導体装置の要部断面図。 スパッタが飛散する様子を示す図。
　実施の形態を以下の実施例で説明する。尚、従来技術の図９の部位と同一部位には同一符号を付した。
　＜実施例１＞
　図１は、この発明の第１実施例の半導体装置の要部断面図である。基本的な構造は、図９に示した従来の半導体装置と同じだが、異なるのは、回路パターン５と外部端子１１との間および回路パターン６と外部端子１１との間に接続導体１４を挿入している点である。
　セラミックス４（絶縁基板）と、このセラミックス４の裏側に形成された裏面銅箔３と、セラミックス４の表側に形成された回路パターン５および回路パターン６からなる絶縁回路基板の裏面銅箔３と銅ベース１をはんだ２により接合し、回路パターン５と半導体チップ８をはんだ７により接合する。また、ブロック状の接続導体１４を回路パターン５および回路パターン６とをはんだ１３で接合する。このはんだ２およびはんだ１３による接合は超音波接合であっても構わない。
　次に、半導体チップ８の上部の図示しないエミッタ電極と回路パターン６とを超音波振動にてボンディングワイヤ９（アルミワイヤなど）にて接続する。
　次に、外部端子１１がインサート成型された端子ケース１０と銅ベース１とを図示しないシリコーン系接着剤にて加熱接着する。この後、接続導体１４の上部面Ｐが露出しボンディングワイヤ９が埋没するように樹脂１７ａを充填する（図４（ａ）参照）。
　その後、接続導体１４と外部端子１１とをスポットレーザ溶接する。この場合のレーザ溶接におけるレーザ光の照射位置は、外部端子１１の上側である。接続導体１４には、回路パターンと接合しやすく、外部端子１１とレーザ溶接しやすい金属を、外部端子１１は接続導体１４とのレーザ溶接しやすい金属をそれぞれ選択する。外部へ主電流を流す観点から、導電性がよいことが望ましく、銅または銅合金が好適である。また、それぞれ接合性を勘案して表面にニッケルめっきなどを施してもよい。
　外部端子１１にレーザを照射して外部端子１１と接続導体１４を溶接部１２にて溶接する。レーザの照射によって、外部端子１１が溶融しその一部がスパッタ２１となって飛散する。飛散したスパッタは樹脂１７ａ上に付着する。その後、さらに上層の絶縁樹脂として樹脂１７ｂを充填する（図４（ｂ）参照）。前記の樹脂１７ａと樹脂１７ｂはシリコーンゲルやエポキシ樹脂であり、両者で同一材質の樹脂である。樹脂１７ａはレーザ溶接時に液状のままであっても、硬化させた状態であってもよい。また、両者の樹脂は異なった材質であっても構わない。
　樹脂１７ｂを充填する前に、樹脂１７ａ上に付着したスパッタ２１を除去する工程を加えてもよい。例えば、樹脂１７ａ上にエアーを吹き付けて、スパッタ２１を除去する。レーザ照射の前に樹脂１７ａを硬化させておくとエアーなどによってスパッタ２１を除去するのが容易となる。
　このようにして、本発明の半導体装置を作製する。スパッタ２１が樹脂１７ａ上に付着し、この樹脂１７ａがマスクとなり回路パターン５、回路パターン６などや半導体チップ８上およびボンディングワイヤ９にスパッタ２１が到達しないため、これらに損傷を与えることはない。
　つまり、レーザ溶接時にスパッタ２１が発生し飛散しても、このスパッタ２１により回路パターン５、６や半導体チップ８およびボンディングワイヤ９が物理的な損傷（キズ、ワレ、切断など）を受けることを防止でき、電気的特性の劣化（耐圧低下、断線による非導通）を防止できる。
　ここで、回路パターン５に、ＩＧＢＴなどの１または複数の信号電極を有する半導体チップ８を実装した変形例について説明する。
　図２に第１実施例の半導体装置の変形例を示す。ここで、図（ａ）および図（ｂ）には工程順の要部断面が示されている。
　半導体チップ８は、主電極のほかに、前記主電極が配置されている半導体チップ８の主面に、１または複数の信号電極を有している。そして、前記主電極を回路パターン６へ接続して主電流を流すボンディングワイヤ９とは別に、前記信号電極を、信号端子１１’と接続する信号用のボンディングワイヤ９０が接続される。そして、図（ａ）に示すように、半導体チップ８の信号電極に導通する信号端子１１’の少なくとも一部、もしくは前記信号端子１１’に導通するボンディングワイヤ９０が樹脂１７ａにより被覆されている。
　主電流を流すボンディングワイヤ９は、通常、信号電極に接続するボンディングワイヤ９０より太く、１つの主電極に対して複数本接続される。ボンディングワイヤ９の太さならびに本数は、主電極に流れる電流の大きさまたはボンディングワイヤ１本あたりに通流可能な電流の大きさによって選択する。
　信号電極に接続するボンディングワイヤ９０には、主電極に接続されるボンディングワイヤ９のように大きな電流が流れることがなく、また信号電極も小さいため、細いワイヤが用いられる。
　ボンディングワイヤに対するスパッタ２１の影響を防ぐためには、前記樹脂１７ａは、すべてのボンディングワイヤを覆うのが望ましい。
　主電流を流すボンディングワイヤ９は、信号電極に接続するボンディングワイヤ９０より太く剛性も大きいため、信号電極に接続するボンディングワイヤ９０に比べてスパッタ２１の衝突の影響を受けにくい。また、近接するボンディングワイヤ９は複数本並列に接続されたものであるため、スパッタ２１がボンディングワイヤ９に付着しても、短絡の影響も受けにくい。
　ボンディングワイヤ９のループ高は、ワイヤの剛性の違いから信号電極に接続するボンディングワイヤ９０より高いため、前記樹脂１７ａの充填高さを、少なくとも、信号電極に接続するボンディングワイヤ９０を覆う高さとする。この高さとなるように、前記溶接部１２の位置Ｈを決定すると、図２に示すように、半導体装置の高さを低くすることができる。また、信号電極に接続するボンディングワイヤ９０をスパッタ２１から確実に保護することもできる。
　前記の接続導体１４は、回路パターン５表面および回路パターン６表面に前述したようにはんだ１３にて接合されている。この接続導体１４と回路パターン５および回路パターン６とのはんだ接合は、銅ベース１と裏面銅箔とのはんだ接合、回路パターン５と半導体チップ８とのはんだ接合と同じ工程で実施することができる。
　すなわち、新たにはんだ接合工程を増やすことなく、接続導体１４をはんだ接合することができる。
　接続導体１４を絶縁回路基板の回路パターン５および回路パターン６にはんだ接合した後、外部端子１１と接続導体１４とをスポットレーザ溶接する。ここで用いる接続導体１４の厚さは、外部端子１１の厚さ以上とすることで、溶接部１２が接続導体１４の下に位置する絶縁回路基板の回路パターン５および回路パターン６や図示しない回路配線などの回路パターンに到達することなく、信頼性の高いレーザ溶接による安定した強固な接合が実現できる。
　また、この信号端子１１’を含めた半導体装置の形態においては、図３に示す形態であってもよい。
　図３は第１実施例の半導体装置の別の変形例を示す。図３では、信号端子１１’周辺の半導体装置の要部断面図が示されている。尚、図３において、銅ベース１は、表示されていない。
　例えば、図（ａ）に示すように、端子ケース１０に一体的に成型（封止）された信号端子１１’と半導体チップ８の信号電極とが、直接的にボンディングワイヤ９０を通じて電気的に接続されている。
　また、図（ｂ）に示すように、セラミックス４上に、回路パターン５とは別の回路パターン５’を設け、当該回路パターン５’と半導体チップ８の信号電極とが、直接的にボンディングワイヤ９０を通じて電気的に接続されている。そして、端子ケース１０に一体的に成型された信号端子１１’と回路パターン５’とがボンディングワイヤ９１を通じて電気的に接続されている。
　また、図（ｃ）に示すように、回路パターン５’にはんだ１３を介して、信号端子１１’を接合してもよい。そして、信号端子１１’と半導体チップ８の信号電極とを直接的にボンディングワイヤ９０を通じて電気的に接続してもよい。
　このような半導体装置の形態であってもよい。
　図４は、図１の半導体装置の製造方法を説明する工程であり、同図（ａ）、同図（ｂ）は工程順に示した要部製造工程断面図である。工程の説明は前記の図１で行っている。
　レーザ溶接する前に樹脂１７ａを充填するので、レーザ溶接時に発生するスパッタ２１は樹脂１７ａの表面に付着し、回路パターン５，６や半導体チップ８へは付着しない。そのため電気的特性の劣化が防止される。また、その後、樹脂１７ｂを充填するのでスパッタ２１が樹脂１７に混入するのは樹脂１７ａと樹脂１７ｂの界面となり、スパッタ２１はこの界面に散在することになる。
　図５は、端子ケースと接続導体の距離が大きい場合のＡ部の構成図であり、同図（ａ）は外部端子を伸ばした場合の図、同図（ｂ）は外部接続導体を用いた場合の図である。図に示すように、端子ケース１０と接続導体１４の間の距離が大きい場合には、同図（ａ）で示すように外部端子１１を接続導体１４まで伸ばすか、同図（ｂ）で示すように外部接続導体１９で外部端子１１と接続導体１４を橋渡しをすればよい。
　＜実施例２＞
　図６は、この発明の第２実施例の半導体装置の要部断面図である。図１の場合との差異は、外部端子１１とスポットレーザ溶接を行う接続導体の形状がＵ字型の接続導体１５としている点である。ここで、Ｕ字型と称したのは、「Ｕ」の文字を横に倒した形状であるためである。回路パターン５にはんだ接合する面と、溶接部１２で溶接する面（Ｐ）とが回路パターン面より立ち上がる部分（連結部）によって空間を隔てて連結された形状である。接続導体１５をＵ字形状とすることで、レーザ溶接の際、上側に位置する外部接続導体（リードフレーム）で下側に位置するＵ字型接続導体１５の上部平板部（上部面Ｐ）を押さえ込むことにより上部平板部Ｐがたわんでレーザ溶接面において、接続導体１５と外部端子１１とがしっかりと密着して良好なレーザ溶接ができる。
　また、Ｕ字型接続導体１５の厚みおよびこれらの材料の表面状態やレーザパワーに変動が生じた場合、レーザ溶接時にＵ字型の上部の平板部ａが溶融しその溶接部１２の中心に貫通孔が形成されることがある。その場合、この貫通孔を介してレーザ光がＵ字型の下側の平板部ｂに照射される。
　しかし、Ｕ字型の下側の平板部ｂにはレーザ光の焦点が結ばないためレーザ光のエネルギーが弱まりＵ字型の下側の平板部ｂは溶融しない。このように、Ｕ字型接続導体１５を挿入することで、絶縁回路基板の回路パターン５および回路パターン６への溶接部１２の到達を防止することができる。そのため、信頼性の高いレーザ溶接による安定した強固な接合を実現することができる。
　この場合も第１実施例と同様にレーザ溶接する前に樹脂１７ａをＵ字型の上側の平板部の表面（上部面Ｐ）より下で、ボンディングワイヤ９を被覆するように充填し、レーザ溶接が終わった後で再度樹脂１７ａ上に樹脂１７ｂを充填する。こうすることで、レーザ溶接時に発生するスパッタ２１が絶縁基板の回路パターン（回路パターン５や回路パターン６や図示しない回路配線パターン）や半導体チップ８表面に付着したり、ボンディングワイヤ９を切断することが防止される。
　＜実施例３＞
　図７は、この発明の第３実施例の半導体装置の構成図であり、同図（ａ）は要部断面図、同図（ｂ）は同図（ａ）のＹ－Ｙ線で切断した要部断面図である。図１および図６の場合との差異は、接続導体の形状をΩ型としたΩ型接続導体１６とした点である。Ω型と称したのは形状がΩの文字に似ているためである。回路パターン５にはんだ接合する面と、溶接部１２で溶接する面（Ｐ）とが、回路パターン面より立ち上がる部分（連結部）によって、空間を隔てて連結された形状である。Ω型接続導体１６は外部端子１１とレーザ溶接による溶接部１２で固着される。このレーザ溶接する前に樹脂１７ａをΩ型接続導体１６の上側の平坦部表面（上部面Ｐ）より下に位置するように充填する。これによってスパッタ２１による損傷や不良を防止する。レーザ溶接後、樹脂１７ａ上に樹脂１７ｂを充填する。
　このΩ型接続導体１６は、はんだ１３により回路パターン５および回路パターン６と接合されている。この場合も同様に、薄い回路パターン５および回路パターン６と厚い外部端子１１とを溶接せず、間に厚いΩ型接続導体１６を挿入することで、Ｕ字型接続導体を挿入した場合と同様に、絶縁回路基板の回路パターン５および回路パターン６への溶接部１２の到達を防止することができる。そのため、信頼性の高いレーザ溶接による安定した強固な接合を実現することができる。この場合のΩ型接続導体１６の厚さは、外部端子１１の厚さ以上とする。
　前記の第２、第３実施例で示したＵ字型やΩ型に限らず、図示しないが、接続導体１４の回路パターンや半導体チップに接合される面と、レーザ溶接される面との間に空間を設け、この空間をレーザ光の光路の延長上に位置するようにすることで同様の効果が得られる。また、円筒や四角柱の側壁の一部が切れて図示しないスリット状の開口部が形成されていても構わない。
　あるいは、断面が□字状の角状のパイプを切断し、一方の面を回路パターン５あるいは回路パターン６にはんだ接合し、対向する面に外部端子１１をスポットレーザ溶接する構成としてもよい。
　この角状のパイプは長尺のパイプを切断するだけでよいので安価に用意することができる。また、断面が□字状なのでレーザ光の光路の延長上に空隙があり、同様の効果が得られる。
　＜実施例４＞
　図８は、この発明の第４実施例の半導体装置の要部構成図であり、同図（ａ）は要部断面図、同図（ｂ）は同図（ａ）のＹ－Ｙ線で切断した要部断面図、同図（ｃ）は同図（ａ）のＢ部の構造が異なる要部断面図、同図（ｄ）は同図（ａ）のＣ部の構造が異なる要部断面図である。この図は２個の半導体チップをΩ型接続導体２０で接続し、そのΩ型接続導体２０と外部接続導体１９（リードフレーム）をレーザ溶接した場合の図である。同図（ｂ）はΩ型接続導体２０は２本の足元に２個の半導体チップ８（例えば、ＩＧＢＴチップとダイオードチップなど）がそれぞれはんだ１３で固着している状態を示している。同図（ｃ）は端子ケースに外部端子が埋め込まれボンディングワイヤ９と接続する箇所が端子ケース１０から露出している場合である。通常のケース構造は同図（ｃ）のような構造をしている。
　また、Ω型接続導体２０は外部接続導体１９（外部端子１１と接続する金属板やリードフレームのこと）とレーザ溶接による溶接部１２で固着される。このレーザ溶接する前に樹脂１７ａをΩ型接続導体２０の上側の平坦部表面（上部面Ｐ）より下に位置するように充填する。これによってスパッタ２１による損傷や不良を防止する。レーザ溶接後、樹脂１７ａ上に樹脂１７ｂを充填する。外部端子１１とセラミックス４に形成されるパッド２２（ゲート用パッドなど）はボンディングワイヤ９で接続され、このボンディングワイヤ９は樹脂１７ａに埋没している。
　同図（ａ）では外部接続導体１９でΩ型接続導体２０と外部端子１１を接続しているが、同図（ｄ）で示すように外部接続導体１９を用いないで、外部端子１１をΩ型接続導体２０まで伸ばし、外部端子１１で直接Ω型接続導体２０を接続しても構わない。
　尚、前記の接続導体１４、Ｕ字型接続導体１５，Ω型接続導体１６、２０および図示しない角状のパイプなどの接続導体の材質としては、低電気抵抗材（電気伝導率の大きな材料）である銅・銅合金を用いるとよい。また、前記半導体チップ８の上側にはアルミワイヤがボンディングされているが、リードフレームによる配線などの場合もある。
　また、前記のスポットレーザ溶接に用いるレーザ光の波長は０．１９μｍ～１０．６μｍであるとよい。
　上記については単に本発明の原理を示すものである。さらに、多数の変形、変更が当業者にとって可能であり、本発明は上記に示し、説明した正確な構成および応用例に限定されるものではなく、対応するすべての変形例および均等物は、添付の請求項およびその均等物による本発明の範囲とみなされる。
符号の説明
　１　銅ベース
　２、７、１３　はんだ
　３　裏面銅箔
　４　セラミックス（絶縁基板）
　５、５’、６　回路パターン
　８　半導体チップ
　９　ボンディングワイヤ（アルミワイヤ）
　１０　端子ケース
　１１　外部端子
　１１’　信号端子
　１２　溶接部
　１４　接続導体
　１５　Ｕ字型接続導体
　１７、１７ａ、１７ｂ　樹脂
　１９　外部接続導体
　２０　Ω型接続導体
　２１　スパッタ
　２２　パッド
　９０、９１　ボンディングワイヤ
　Ｐ　上部面

Claims (11)

  1. 　絶縁基板上に形成された回路パターンと、
    　前記回路パターン上に固着された半導体チップと、
    　前記回路パターンもしくは前記半導体チップの少なくとも一方に固着された接続導体と、
    　前記接続導体の溶接部を露出させ、前記回路パターン、前記半導体チップを被覆した絶縁樹脂と、
    　前記半導体チップの主電極に主電流を流し、前記接続導体の前記溶接部にレーザ溶接で接合された外部端子と、
    　からなることを特徴とする半導体装置。
  2. 　前記絶縁樹脂上に、前記接続導体の露出部と前記外部端子を被覆する上層絶縁樹脂を備えたことを特徴とする請求の範囲第１項に記載の半導体装置。
  3. 　絶縁基板上に形成された回路パターンと、
    　前記回路パターン上に固着された半導体チップと、
    　前記回路パターンもしくは前記半導体チップの少なくとも一方に固着された接続導体と、
    　前記接続導体の溶接部を露出させ、前記回路パターン、前記半導体チップを被覆した絶縁樹脂と、
    　前記半導体チップの主電極に主電流を流す外部端子と、
    　該外部端子と前記接続導体の前記溶接部とにそれぞれレーザ溶接で接合された外部接続導体と、
    　からなることを特徴とする半導体装置。
  4. 　前記絶縁樹脂上に、前記接続導体の露出部と前記外部端子と前記外部接続導体とを被覆する上層絶縁樹脂を備えたことを特徴とする請求の範囲第３項に記載の半導体装置。
  5. 　前記半導体チップは、前記主電極の他に１または複数の信号電極を有し、前記絶縁樹脂は、少なくとも前記信号電極と外部に導出する信号端子とを接続するボンディングワイヤを被覆していることを特徴とする請求の範囲第１項または第３項に記載の半導体装置。
  6. 　前記接続導体は、前記固着した面と前記溶接部とを、空間を隔てて位置する屈曲構造であることを特徴とする請求の範囲第１項または第３項に記載の半導体装置。
  7. 　絶縁基板上に形成された回路パターンに半導体チップを固着する工程と、
    　前記回路パターンもしくは前記半導体チップの少なくとも一方に接続導体を固着する工程と、
    　前記接続導体の溶接部を露出させ、前記回路パターン、前記半導体チップを絶縁樹脂にて被覆する被覆工程と、
    　前記被覆工程に続いて、前記半導体チップの主電極に主電流を流す外部端子を、前記接続導体の前記溶接部にレーザ溶接で接合する工程と、
    　前記絶縁樹脂上に、前記接続導体の露出部と前記外部端子を被覆する上層絶縁樹脂を充填する充填工程と、
    　を含むことを特徴とする半導体装置の製造方法。
  8. 　絶縁基板上に形成された回路パターンに半導体チップを固着する工程と、
    　前記回路パターンもしくは前記半導体チップの少なくとも一方に接続導体を固着する工程と、
    　前記接続導体の溶接部を露出させ、前記回路パターン、前記半導体チップを絶縁樹脂にて被覆する被覆工程と、
    　前記被覆工程に続いて、前記半導体チップの主電極に主電流を流す外部端子と、前記接続導体の前記溶接部とにそれぞれ外部接続導体をレーザ溶接で接合する工程と、
    　前記絶縁樹脂上に、前記接続導体の露出部と前記外部端子と前記外部接続導体とを被覆する上層絶縁樹脂を充填する充填工程と、
    　を含むことを特徴とする半導体装置の製造方法。
  9. 　前記絶縁樹脂は、硬化性樹脂であって、前記被覆工程は、前記硬化性樹脂を硬化させる工程を含み、前記充填工程の前に、前記絶縁樹脂の表面の異物を除去する除去工程を有することを特徴とする請求の範囲第７項または第８項に記載の半導体装置の製造方法。
  10. 　前記絶縁樹脂および上層絶縁樹脂は、硬化性樹脂であって、前記充填工程に続いて、前記絶縁樹脂および前記上層絶縁樹脂を同時に硬化する硬化工程を有することを特徴とする請求の範囲第７項または第８項に記載の半導体装置の製造方法。
  11. 　前記半導体チップの信号電極に導通する信号端子の少なくとも一部もしくは前記信号端子に導通するボンディングワイヤを、前記絶縁樹脂により被覆することを特徴とする請求の範囲第７項または第８項に記載の半導体装置の製造方法。
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