WO2009081723A1 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
- Publication number
- WO2009081723A1 WO2009081723A1 PCT/JP2008/072314 JP2008072314W WO2009081723A1 WO 2009081723 A1 WO2009081723 A1 WO 2009081723A1 JP 2008072314 W JP2008072314 W JP 2008072314W WO 2009081723 A1 WO2009081723 A1 WO 2009081723A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- connection conductor
- semiconductor chip
- circuit pattern
- insulating resin
- semiconductor device
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 117
- 238000000034 method Methods 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000004020 conductor Substances 0.000 claims abstract description 102
- 229920005989 resin Polymers 0.000 claims abstract description 93
- 239000011347 resin Substances 0.000 claims abstract description 93
- 238000003466 welding Methods 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims description 15
- 239000011248 coating agent Substances 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 8
- 238000005304 joining Methods 0.000 claims description 7
- 229910000679 solder Inorganic materials 0.000 abstract description 17
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 16
- 239000011889 copper foil Substances 0.000 abstract description 7
- 230000006866 deterioration Effects 0.000 abstract description 5
- 229910010293 ceramic material Inorganic materials 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 10
- 229910052802 copper Inorganic materials 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- 239000000919 ceramic Substances 0.000 description 8
- 230000004048 modification Effects 0.000 description 6
- 238000012986 modification Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 238000007789 sealing Methods 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 239000013464 silicone adhesive Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/3754—Coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4846—Connecting portions with multiple bonds on the same bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4901—Structure
- H01L2224/4903—Connectors having different sizes, e.g. different diameters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/842—Applying energy for connecting
- H01L2224/8421—Applying energy for connecting with energy being in the form of electromagnetic radiation
- H01L2224/84214—Applying energy for connecting with energy being in the form of electromagnetic radiation using a laser
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/84801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Definitions
- the present invention relates to a semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor) and a PIM (Power Integrated Module), and a manufacturing method thereof.
- a semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor) and a PIM (Power Integrated Module)
- FIG. 9 is a cross-sectional view of a main part of a conventional semiconductor device.
- a conventional assembly process of the semiconductor device will be described.
- the back surface copper foil 3 and the copper base 1 of the insulated circuit board composed of the back surface copper foil 3, the ceramic 4, the circuit pattern 5 and the circuit pattern 6 are joined by the solder 2, and the circuit pattern 5 and the semiconductor chip 8 are joined by the solder 7.
- the semiconductor chip 8 is a switching element such as an IGBT or FWD (Free Wheeling Diode).
- solder joints are performed in a single heating step. Thereafter, an emitter electrode (not shown) on the upper portion of the semiconductor chip 8 and the circuit pattern 6 are connected by a bonding wire 9 (such as an aluminum wire) by ultrasonic vibration.
- a bonding wire 9 such as an aluminum wire
- the terminal case 10 in which the external terminal 11 is insert-molded and the copper base 1 are heat-bonded with a silicone adhesive (not shown).
- the circuit pattern 5 and the external terminal 11 and the circuit pattern 6 and the external terminal 11 are spot laser welded.
- the laser beam irradiation position in the laser welding is above the external terminal 11.
- a resin (not shown) is filled to cover the surface of the semiconductor chip 8. In this way, a conventional semiconductor device is manufactured.
- Patent Document 1 a semiconductor element mounting substrate formed by bonding a substrate on which a wiring pattern for mounting a semiconductor element is formed and a lead by laser, and a leading end portion of the lead to be bonded to an electrode pad of the substrate Is formed thinner than other portions of the lead.
- Patent Document 2 a resin sealing body, a first semiconductor chip and a second semiconductor chip which are located inside the resin sealing body and have electrodes formed on the front and back surfaces, and the resin sealing A first lead that extends over the inside and outside of the stopper and is electrically connected to the electrode of the first semiconductor chip, the first lead, and the inside and outside of the resin sealing body.
- the laser welding shown in FIG. 9 is performed before the resin 17 is coated.
- circuit patterns 5 and 6 (including wiring patterns not shown) formed on the insulating substrate (ceramics 4) by the spattered spatter 21 are short-circuited, or bonding wires 9 are bonded.
- the wiring such as is cut (fused), or the semiconductor chip 8 is damaged.
- the spatter is scattered, resulting in poor insulation of the insulating substrate, short circuit between circuit patterns, disconnection of the wire wiring, physical damage to the semiconductor chip (melting marks, fine scratches, micro cracks, etc.) and the electrical properties of the semiconductor chip. Cause poor electrical characteristics (short circuit, etc.).
- An object of the present invention is to solve the above-mentioned problems and prevent a spatter generated by laser welding from adhering to a circuit pattern or a semiconductor chip, thereby preventing deterioration of electrical characteristics and its manufacture. It is to provide a method.
- a circuit pattern formed on an insulating substrate, a semiconductor chip fixed on the circuit pattern, a connection conductor fixed to at least one of the circuit pattern or the semiconductor chip, and a welded portion of the connection conductor The circuit pattern, an insulating resin covering the semiconductor chip, and an external terminal for supplying a main current to the main electrode of the semiconductor chip and joining the welded portion of the connection conductor by laser welding.
- connection conductor An upper insulating resin that covers the exposed portion of the connection conductor and the external terminal is provided on the insulating resin.
- the upper insulating resin covering the exposed portion of the connection conductor, the external terminal, and the external connection conductor is provided on the insulating resin.
- the semiconductor chip has one or a plurality of signal electrodes in addition to the main electrode, and the insulating resin covers at least a bonding wire that connects the signal electrode and a signal terminal led out to the outside. It is good to be.
- connection conductor may have a bent structure in which the fixed surface and the welded portion are positioned with a space therebetween.
- the circuit pattern, a coating step of coating the semiconductor chip with an insulating resin, and subsequent to the coating step, an external terminal for supplying a main current to the main electrode of the semiconductor chip is laser welded to the welding portion of the connection conductor
- a semiconductor comprising: a step of joining an external connection conductor by laser welding; and a filling step of filling an upper insulating resin covering the exposed portion of the connection conductor, the external terminal, and the external connection conductor on the insulating resin. It is set as the manufacturing method of an apparatus.
- the insulating resin is a curable resin
- the covering step includes a step of curing the curable resin, and a removing step of removing foreign matters on the surface of the insulating resin before the filling step.
- the insulating resin and the upper layer insulating resin are curable resins, and the semiconductor device manufacturing method includes a curing step of simultaneously curing the insulating resin and the upper layer insulating resin after the filling step.
- At least a part of signal terminals that conduct to the signal electrodes of the semiconductor chip or bonding wires that conduct to the signal terminals are covered with the insulating resin.
- the filling of the insulating resin is performed in two portions, the first filling is performed below the upper surface of the lower member to be laser welded, laser welding is performed in that state, and then further addition is performed.
- Filling the insulation resin can cause physical damage (scratches, cracks, cutting, etc.) to circuit patterns, semiconductor chips, and bonding wires even when spatter is scattered during laser welding. Therefore, it is possible to prevent deterioration of electrical characteristics (decrease in breakdown voltage, non-conduction due to disconnection).
- FIG. 1 is a cross-sectional view of main parts of a semiconductor device according to a first embodiment of the present invention.
- the principal part sectional view showing the modification of the semiconductor device of the 1st example.
- the principal part sectional drawing which shows another modification of the semiconductor device of 1st Example.
- FIGS. 2A and 2B are cross-sectional views of a main part manufacturing process illustrating a method for manufacturing the semiconductor device of FIG. 1, in which FIGS. It is a block diagram of the A section when the distance between the terminal case and the connection conductor is large, in which FIG. (A) is a diagram when the external terminal is extended, and (b) is a diagram when the external connection conductor is used. Sectional drawing of the principal part of the semiconductor device of 2nd Example of this invention.
- FIG. 1 is a cross-sectional view of main parts of a semiconductor device according to a first embodiment of the present invention.
- the principal part sectional view showing the modification of the semiconductor device of the 1st example.
- FIG. 4 is a configuration diagram of a semiconductor device according to a third embodiment of the present invention, in which (a) is a cross-sectional view of the main part and (b) is a cross-sectional view of the main part taken along line YY of (a).
- FIG. 10 is a main part configuration diagram of a semiconductor device according to a fourth embodiment of the present invention, where (a) is a main part sectional view, (b) is a main part sectional view taken along line YY of (a), and (c).
- (d) is principal part sectional drawing from which the structure of C part of (a) differs. Sectional drawing of the principal part of the conventional semiconductor device. The figure which shows a mode that a spatter disperses.
- FIG. 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment of the present invention.
- the basic structure is the same as that of the conventional semiconductor device shown in FIG. 9 except that the connection conductor 14 is inserted between the circuit pattern 5 and the external terminal 11 and between the circuit pattern 6 and the external terminal 11. This is the point.
- a backside copper foil 3 and copper of an insulating circuit board comprising a ceramic 4 (insulating substrate), a backside copper foil 3 formed on the back side of the ceramics 4, and a circuit pattern 5 and a circuit pattern 6 formed on the front side of the ceramics 4.
- the base 1 is joined with the solder 2, and the circuit pattern 5 and the semiconductor chip 8 are joined with the solder 7. Further, the block-shaped connection conductor 14 is joined to the circuit pattern 5 and the circuit pattern 6 with the solder 13.
- the joining by the solder 2 and the solder 13 may be ultrasonic joining.
- an emitter electrode (not shown) on the top of the semiconductor chip 8 and the circuit pattern 6 are connected by a bonding wire 9 (aluminum wire or the like) by ultrasonic vibration.
- a bonding wire 9 aluminum wire or the like
- the terminal case 10 in which the external terminals 11 are insert-molded and the copper base 1 are heat-bonded with a silicone adhesive (not shown).
- the resin 17a is filled so that the upper surface P of the connection conductor 14 is exposed and the bonding wire 9 is buried (see FIG. 4A).
- connection conductor 14 and the external terminal 11 are spot laser welded.
- the laser beam irradiation position in the laser welding is above the external terminal 11.
- a metal that can be easily joined to the circuit pattern and easily welded to the external terminal 11 is selected.
- a metal that is easy to laser weld to the connection conductor 14 is selected. From the viewpoint of flowing the main current to the outside, it is desirable that the conductivity is good, and copper or a copper alloy is preferable. Further, nickel plating or the like may be applied to the surface in consideration of bondability.
- the external terminal 11 is irradiated with a laser, and the external terminal 11 and the connection conductor 14 are welded at the welded portion 12.
- the external terminal 11 is melted by laser irradiation, and a part of the external terminal 11 is spattered 21 and scattered.
- the scattered spatter adheres onto the resin 17a.
- the resin 17b is filled as an upper layer insulating resin (see FIG. 4B).
- the resin 17a and the resin 17b are silicone gel or epoxy resin, and both are resins of the same material.
- the resin 17a may remain in a liquid state during laser welding or may be in a cured state. Further, both resins may be made of different materials.
- a step of removing the spatter 21 adhering to the resin 17a may be added. For example, air is blown onto the resin 17a to remove the spatter 21. If the resin 17a is cured before the laser irradiation, it becomes easy to remove the spatter 21 by air or the like.
- the spatter 21 adheres onto the resin 17a, and the resin 17a serves as a mask, so that the spatter 21 does not reach the circuit pattern 5, the circuit pattern 6, etc., the semiconductor chip 8, and the bonding wire 9, so that they are not damaged.
- spatter 21 prevents physical damage (scratches, cracking, cutting, etc.) to the circuit patterns 5, 6, the semiconductor chip 8, and the bonding wire 9. It is possible to prevent deterioration of electrical characteristics (decrease in breakdown voltage, non-conduction due to disconnection).
- FIG. 2 shows a modification of the semiconductor device of the first embodiment.
- FIGS. 1A and 1B show cross-sections of main parts in the order of processes.
- the semiconductor chip 8 has one or a plurality of signal electrodes on the main surface of the semiconductor chip 8 on which the main electrode is disposed.
- a signal bonding wire 90 for connecting the signal electrode to the signal terminal 11 ′ is connected. As shown in FIG. 5A, at least a part of the signal terminal 11 'that conducts to the signal electrode of the semiconductor chip 8 or a bonding wire 90 that conducts to the signal terminal 11' is covered with a resin 17a.
- the bonding wires 9 for flowing the main current are usually thicker than the bonding wires 90 connected to the signal electrodes, and a plurality of bonding wires 9 are connected to one main electrode.
- the thickness and number of the bonding wires 9 are selected depending on the magnitude of the current flowing through the main electrode or the magnitude of the current that can be passed per bonding wire.
- a thin wire is used for the bonding wire 90 connected to the signal electrode because a large current does not flow and the signal electrode is small as in the bonding wire 9 connected to the main electrode.
- the resin 17a desirably covers all the bonding wires. Since the bonding wire 9 through which the main current flows is thicker and more rigid than the bonding wire 90 connected to the signal electrode, it is less susceptible to the impact of the sputter 21 than the bonding wire 90 connected to the signal electrode. In addition, since a plurality of adjacent bonding wires 9 are connected in parallel, even if the sputter 21 adheres to the bonding wires 9, it is not easily affected by a short circuit.
- the filling height of the resin 17a is at least a height that covers the bonding wire 90 connected to the signal electrode. .
- the position H of the welded portion 12 is determined so as to have this height, as shown in FIG. 2, the height of the semiconductor device can be reduced.
- the bonding wire 90 connected to the signal electrode can be reliably protected from the sputter 21.
- the connecting conductor 14 is joined to the surface of the circuit pattern 5 and the surface of the circuit pattern 6 with the solder 13 as described above.
- the solder bonding between the connection conductor 14 and the circuit pattern 5 and the circuit pattern 6 can be performed in the same process as the solder bonding between the copper base 1 and the back surface copper foil and the solder bonding between the circuit pattern 5 and the semiconductor chip 8. .
- the connecting conductor 14 can be soldered without newly increasing the soldering process.
- the external terminal 11 and the connection conductor 14 are spot laser welded.
- the thickness of the connection conductor 14 used here is equal to or greater than the thickness of the external terminal 11, so that the circuit pattern 5 and the circuit pattern 6 of the insulated circuit board where the welded portion 12 is located below the connection conductor 14 or a circuit (not shown). Without reaching a circuit pattern such as wiring, stable and strong joining by laser welding with high reliability can be realized.
- FIG. 3 shows another modification of the semiconductor device of the first embodiment.
- FIG. 3 shows a cross-sectional view of the main part of the semiconductor device around the signal terminal 11 ′.
- the copper base 1 is not displayed.
- the signal terminal 11 ′ molded (sealed) integrally with the terminal case 10 and the signal electrode of the semiconductor chip 8 are electrically connected directly through the bonding wire 90. Has been.
- a circuit pattern 5 ′ different from the circuit pattern 5 is provided on the ceramic 4 and the circuit pattern 5 ′ and the signal electrode of the semiconductor chip 8 are directly connected to the bonding wire. 90 is electrically connected. Then, the signal terminal 11 ′ formed integrally with the terminal case 10 and the circuit pattern 5 ′ are electrically connected through the bonding wire 91.
- the signal terminal 11 ′ may be joined to the circuit pattern 5 ′ via the solder 13. Then, the signal terminal 11 ′ and the signal electrode of the semiconductor chip 8 may be electrically connected directly through the bonding wire 90.
- FIG. 4 is a process for explaining the manufacturing method of the semiconductor device of FIG. 1, and FIG. 4A and FIG. 4B are cross-sectional views of the main part manufacturing process shown in the order of the processes. The process is described with reference to FIG.
- the spatter 21 generated during laser welding adheres to the surface of the resin 17a and does not adhere to the circuit patterns 5 and 6 and the semiconductor chip 8. As a result, deterioration of electrical characteristics is prevented. After that, since the resin 17b is filled, the sputter 21 is mixed into the resin 17 at the interface between the resin 17a and the resin 17b, and the spatter 21 is scattered at this interface.
- FIGS. 5A and 5B are configuration diagrams of part A when the distance between the terminal case and the connection conductor is large.
- FIG. 5A is a diagram in the case where the external terminal is extended
- FIG. 5B is a diagram in which the external connection conductor is used.
- FIG. As shown in the figure, when the distance between the terminal case 10 and the connection conductor 14 is large, the external terminal 11 is extended to the connection conductor 14 as shown in FIG. Thus, the external connection conductor 19 may be used to bridge the external terminal 11 and the connection conductor 14.
- FIG. 6 is a cross-sectional view of the main part of the semiconductor device according to the second embodiment of the present invention.
- the shape of the connection conductor for spot laser welding with the external terminal 11 is a U-shaped connection conductor 15.
- the U-shape is referred to because it is a shape in which the letter “U” is tilted sideways.
- the surface solder-bonded to the circuit pattern 5 and the surface (P) to be welded at the welded portion 12 are connected to each other with a portion (connecting portion) rising from the circuit pattern surface with a space therebetween.
- connection conductor 15 U-shaped
- the upper flat plate portion P bends and the connecting conductor 15 and the external terminal 11 are firmly adhered to each other on the laser welding surface, and good laser welding can be performed.
- the U-shaped upper flat plate portion a melts and penetrates through the center of the welded portion 12 during laser welding. Holes may be formed. In that case, the laser beam is irradiated to the U-shaped lower flat plate portion b through the through hole.
- the energy of the laser beam is weakened and the lower flat plate portion b of the U shape is not melted.
- the U-shaped connection conductor 15 it is possible to prevent the welded portion 12 from reaching the circuit pattern 5 and the circuit pattern 6 of the insulated circuit board. Therefore, it is possible to realize stable and strong bonding by highly reliable laser welding.
- the resin 17a is filled so as to cover the bonding wire 9 below the surface (upper surface P) of the U-shaped upper flat plate portion before laser welding as in the first embodiment, and laser welding is performed.
- the resin 17b is filled again on the resin 17a.
- FIGS. 7A and 7B are configuration diagrams of a semiconductor device according to a third embodiment of the present invention.
- FIG. 7A is a cross-sectional view of the main part, and FIG. 7B is cut along the YY line of FIG. It is principal part sectional drawing.
- the difference from the case of FIG. 1 and FIG. 6 is that the shape of the connection conductor is an ⁇ -type connection conductor 16 having an ⁇ shape.
- the term “ ⁇ type” is used because it resembles a letter with a shape of ⁇ .
- the surface that is solder-bonded to the circuit pattern 5 and the surface (P) that is welded by the welded portion 12 are connected by a portion (connecting portion) that rises from the circuit pattern surface with a space therebetween.
- the ⁇ -type connection conductor 16 is fixed to the external terminal 11 with a welded portion 12 by laser welding. Before this laser welding, the resin 17a is filled so as to be positioned below the upper flat surface (upper surface P) of the ⁇ -type connecting conductor 16. This prevents damage and defects due to the spatter 21. After the laser welding, the resin 17b is filled on the resin 17a.
- the ⁇ -type connection conductor 16 is joined to the circuit pattern 5 and the circuit pattern 6 by the solder 13. Similarly in this case, the thin circuit pattern 5 and the circuit pattern 6 and the thick external terminal 11 are not welded, and the thick ⁇ -type connection conductor 16 is inserted between them, which is the same as the case where the U-shaped connection conductor is inserted. In addition, it is possible to prevent the welded portion 12 from reaching the circuit pattern 5 and the circuit pattern 6 of the insulated circuit board. Therefore, it is possible to realize stable and strong bonding by highly reliable laser welding. In this case, the thickness of the ⁇ -type connection conductor 16 is equal to or greater than the thickness of the external terminal 11.
- connection conductor 14 bonded to the circuit pattern or the semiconductor chip and the surface to be laser-welded.
- a similar effect can be obtained by providing a space in the space and positioning the space on the extension of the optical path of the laser beam.
- a part of the side wall of the cylinder or the quadrangular column may be cut to form a slit-like opening (not shown).
- a square pipe having a square shape in section may be cut, one surface may be soldered to the circuit pattern 5 or the circuit pattern 6, and the external terminal 11 may be spot laser welded to the opposite surface.
- This square pipe can be prepared inexpensively because it is only necessary to cut a long pipe. Further, since the cross section is a square shape, there is a gap on the extension of the optical path of the laser beam, and the same effect can be obtained.
- FIGS. 8A and 8B are main part configuration diagrams of a semiconductor device according to a fourth embodiment of the present invention.
- FIG. 8A is a cross-sectional view of the main part
- FIG. 8B is a YY line of FIG. Cross-sectional view of the cut main part
- FIG. 10C is a cross-sectional view of the main part in which the structure of the B part in FIG. 11A is different
- FIG. 14D is a main part in which the structure of the C part of FIG. It is sectional drawing.
- This figure shows a case where two semiconductor chips are connected by an ⁇ -type connection conductor 20 and the ⁇ -type connection conductor 20 and the external connection conductor 19 (lead frame) are laser-welded.
- FIG. 8A is a cross-sectional view of the main part
- FIG. 8B is a YY line of FIG.
- FIG. 10C is a cross-sectional view of the main part in which the structure
- FIG. 2B shows a state in which two semiconductor chips 8 (for example, an IGBT chip and a diode chip) are fixed by solder 13 at two feet of the ⁇ -type connecting conductor 20.
- FIG. 3C shows the case where the external terminal is embedded in the terminal case and the portion connected to the bonding wire 9 is exposed from the terminal case 10.
- a normal case structure has a structure as shown in FIG.
- the ⁇ -type connection conductor 20 is fixed to the external connection conductor 19 (a metal plate or lead frame connected to the external terminal 11) with a welded portion 12 by laser welding.
- the resin 17a is filled so as to be positioned below the upper flat surface (upper surface P) of the ⁇ -type connecting conductor 20. This prevents damage and defects due to the spatter 21.
- the resin 17b is filled on the resin 17a.
- a pad 22 (such as a gate pad) formed on the external terminal 11 and the ceramic 4 is connected by a bonding wire 9, and the bonding wire 9 is buried in a resin 17a.
- the external connection conductor 19 connects the ⁇ -type connection conductor 20 and the external terminal 11, but the external connection conductor 19 is not used as shown in FIG. You may extend to the mold connection conductor 20 and connect the ⁇ connection conductor 20 directly with the external terminal 11.
- connection conductor 14 U-shaped connection conductor 15, ⁇ -type connection conductors 16 and 20, and connection conductors such as a square pipe (not shown) may be a low electrical resistance material (a material having a high electrical conductivity). It is preferable to use a copper / copper alloy. In addition, although an aluminum wire is bonded to the upper side of the semiconductor chip 8, there is a case of wiring by a lead frame.
- the wavelength of the laser beam used for the spot laser welding is preferably 0.19 ⁇ m to 10.6 ⁇ m.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Dispersion Chemistry (AREA)
- Wire Bonding (AREA)
- Laser Beam Processing (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
(1)絶縁基板上に形成された回路パターンと、前記回路パターン上に固着された半導体チップと、前記回路パターンもしくは前記半導体チップの少なくとも一方に固着された接続導体と、前記接続導体の溶接部を露出させ、前記回路パターン、前記半導体チップを被覆した絶縁樹脂と、前記半導体チップの主電極に主電流を流し、前記接続導体の前記溶接部にレーザ溶接で接合された外部端子と、からなる構成とする。
(3)絶縁基板上に形成された回路パターンと、前記回路パターン上に固着された半導体チップと、前記回路パターンもしくは前記半導体チップの少なくとも一方に固着された接続導体と、前記接続導体の溶接部を露出させ、前記回路パターン、前記半導体チップを被覆した絶縁樹脂と、前記半導体チップの主電極に主電流を流す外部端子と、該外部端子と前記接続導体の前記溶接部とにそれぞれレーザ溶接で接合された外部接続導体と、からなる構成とする。
(5)前記半導体チップは、前記主電極の他に1または複数の信号電極を有し、前記絶縁樹脂は、少なくとも前記信号電極と外部に導出する信号端子とを接続するボンディングワイヤを被覆しているとよい。
(7)絶縁基板上に形成された回路パターンに半導体チップを固着する工程と、前記回路パターンもしくは前記半導体チップの少なくとも一方に接続導体を固着する工程と、前記接続導体の溶接部を露出させ、前記回路パターン、前記半導体チップを絶縁樹脂にて被覆する被覆工程と、前記被覆工程に続いて、前記半導体チップの主電極に主電流を流す外部端子を、前記接続導体の前記溶接部にレーザ溶接で接合する工程と、前記絶縁樹脂上に、前記接続導体の露出部と前記外部端子を被覆する上層絶縁樹脂を充填する充填工程と、を含む半導体装置の製造方法とする。
<実施例1>
図1は、この発明の第1実施例の半導体装置の要部断面図である。基本的な構造は、図9に示した従来の半導体装置と同じだが、異なるのは、回路パターン5と外部端子11との間および回路パターン6と外部端子11との間に接続導体14を挿入している点である。
次に、外部端子11がインサート成型された端子ケース10と銅ベース1とを図示しないシリコーン系接着剤にて加熱接着する。この後、接続導体14の上部面Pが露出しボンディングワイヤ9が埋没するように樹脂17aを充填する(図4(a)参照)。
図2に第1実施例の半導体装置の変形例を示す。ここで、図(a)および図(b)には工程順の要部断面が示されている。
主電流を流すボンディングワイヤ9は、信号電極に接続するボンディングワイヤ90より太く剛性も大きいため、信号電極に接続するボンディングワイヤ90に比べてスパッタ21の衝突の影響を受けにくい。また、近接するボンディングワイヤ9は複数本並列に接続されたものであるため、スパッタ21がボンディングワイヤ9に付着しても、短絡の影響も受けにくい。
接続導体14を絶縁回路基板の回路パターン5および回路パターン6にはんだ接合した後、外部端子11と接続導体14とをスポットレーザ溶接する。ここで用いる接続導体14の厚さは、外部端子11の厚さ以上とすることで、溶接部12が接続導体14の下に位置する絶縁回路基板の回路パターン5および回路パターン6や図示しない回路配線などの回路パターンに到達することなく、信頼性の高いレーザ溶接による安定した強固な接合が実現できる。
図3は第1実施例の半導体装置の別の変形例を示す。図3では、信号端子11’周辺の半導体装置の要部断面図が示されている。尚、図3において、銅ベース1は、表示されていない。
図4は、図1の半導体装置の製造方法を説明する工程であり、同図(a)、同図(b)は工程順に示した要部製造工程断面図である。工程の説明は前記の図1で行っている。
図6は、この発明の第2実施例の半導体装置の要部断面図である。図1の場合との差異は、外部端子11とスポットレーザ溶接を行う接続導体の形状がU字型の接続導体15としている点である。ここで、U字型と称したのは、「U」の文字を横に倒した形状であるためである。回路パターン5にはんだ接合する面と、溶接部12で溶接する面(P)とが回路パターン面より立ち上がる部分(連結部)によって空間を隔てて連結された形状である。接続導体15をU字形状とすることで、レーザ溶接の際、上側に位置する外部接続導体(リードフレーム)で下側に位置するU字型接続導体15の上部平板部(上部面P)を押さえ込むことにより上部平板部Pがたわんでレーザ溶接面において、接続導体15と外部端子11とがしっかりと密着して良好なレーザ溶接ができる。
図7は、この発明の第3実施例の半導体装置の構成図であり、同図(a)は要部断面図、同図(b)は同図(a)のY-Y線で切断した要部断面図である。図1および図6の場合との差異は、接続導体の形状をΩ型としたΩ型接続導体16とした点である。Ω型と称したのは形状がΩの文字に似ているためである。回路パターン5にはんだ接合する面と、溶接部12で溶接する面(P)とが、回路パターン面より立ち上がる部分(連結部)によって、空間を隔てて連結された形状である。Ω型接続導体16は外部端子11とレーザ溶接による溶接部12で固着される。このレーザ溶接する前に樹脂17aをΩ型接続導体16の上側の平坦部表面(上部面P)より下に位置するように充填する。これによってスパッタ21による損傷や不良を防止する。レーザ溶接後、樹脂17a上に樹脂17bを充填する。
図8は、この発明の第4実施例の半導体装置の要部構成図であり、同図(a)は要部断面図、同図(b)は同図(a)のY-Y線で切断した要部断面図、同図(c)は同図(a)のB部の構造が異なる要部断面図、同図(d)は同図(a)のC部の構造が異なる要部断面図である。この図は2個の半導体チップをΩ型接続導体20で接続し、そのΩ型接続導体20と外部接続導体19(リードフレーム)をレーザ溶接した場合の図である。同図(b)はΩ型接続導体20は2本の足元に2個の半導体チップ8(例えば、IGBTチップとダイオードチップなど)がそれぞれはんだ13で固着している状態を示している。同図(c)は端子ケースに外部端子が埋め込まれボンディングワイヤ9と接続する箇所が端子ケース10から露出している場合である。通常のケース構造は同図(c)のような構造をしている。
上記については単に本発明の原理を示すものである。さらに、多数の変形、変更が当業者にとって可能であり、本発明は上記に示し、説明した正確な構成および応用例に限定されるものではなく、対応するすべての変形例および均等物は、添付の請求項およびその均等物による本発明の範囲とみなされる。
2、7、13 はんだ
3 裏面銅箔
4 セラミックス(絶縁基板)
5、5’、6 回路パターン
8 半導体チップ
9 ボンディングワイヤ(アルミワイヤ)
10 端子ケース
11 外部端子
11’ 信号端子
12 溶接部
14 接続導体
15 U字型接続導体
17、17a、17b 樹脂
19 外部接続導体
20 Ω型接続導体
21 スパッタ
22 パッド
90、91 ボンディングワイヤ
P 上部面
Claims (11)
- 絶縁基板上に形成された回路パターンと、
前記回路パターン上に固着された半導体チップと、
前記回路パターンもしくは前記半導体チップの少なくとも一方に固着された接続導体と、
前記接続導体の溶接部を露出させ、前記回路パターン、前記半導体チップを被覆した絶縁樹脂と、
前記半導体チップの主電極に主電流を流し、前記接続導体の前記溶接部にレーザ溶接で接合された外部端子と、
からなることを特徴とする半導体装置。 - 前記絶縁樹脂上に、前記接続導体の露出部と前記外部端子を被覆する上層絶縁樹脂を備えたことを特徴とする請求の範囲第1項に記載の半導体装置。
- 絶縁基板上に形成された回路パターンと、
前記回路パターン上に固着された半導体チップと、
前記回路パターンもしくは前記半導体チップの少なくとも一方に固着された接続導体と、
前記接続導体の溶接部を露出させ、前記回路パターン、前記半導体チップを被覆した絶縁樹脂と、
前記半導体チップの主電極に主電流を流す外部端子と、
該外部端子と前記接続導体の前記溶接部とにそれぞれレーザ溶接で接合された外部接続導体と、
からなることを特徴とする半導体装置。 - 前記絶縁樹脂上に、前記接続導体の露出部と前記外部端子と前記外部接続導体とを被覆する上層絶縁樹脂を備えたことを特徴とする請求の範囲第3項に記載の半導体装置。
- 前記半導体チップは、前記主電極の他に1または複数の信号電極を有し、前記絶縁樹脂は、少なくとも前記信号電極と外部に導出する信号端子とを接続するボンディングワイヤを被覆していることを特徴とする請求の範囲第1項または第3項に記載の半導体装置。
- 前記接続導体は、前記固着した面と前記溶接部とを、空間を隔てて位置する屈曲構造であることを特徴とする請求の範囲第1項または第3項に記載の半導体装置。
- 絶縁基板上に形成された回路パターンに半導体チップを固着する工程と、
前記回路パターンもしくは前記半導体チップの少なくとも一方に接続導体を固着する工程と、
前記接続導体の溶接部を露出させ、前記回路パターン、前記半導体チップを絶縁樹脂にて被覆する被覆工程と、
前記被覆工程に続いて、前記半導体チップの主電極に主電流を流す外部端子を、前記接続導体の前記溶接部にレーザ溶接で接合する工程と、
前記絶縁樹脂上に、前記接続導体の露出部と前記外部端子を被覆する上層絶縁樹脂を充填する充填工程と、
を含むことを特徴とする半導体装置の製造方法。 - 絶縁基板上に形成された回路パターンに半導体チップを固着する工程と、
前記回路パターンもしくは前記半導体チップの少なくとも一方に接続導体を固着する工程と、
前記接続導体の溶接部を露出させ、前記回路パターン、前記半導体チップを絶縁樹脂にて被覆する被覆工程と、
前記被覆工程に続いて、前記半導体チップの主電極に主電流を流す外部端子と、前記接続導体の前記溶接部とにそれぞれ外部接続導体をレーザ溶接で接合する工程と、
前記絶縁樹脂上に、前記接続導体の露出部と前記外部端子と前記外部接続導体とを被覆する上層絶縁樹脂を充填する充填工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記絶縁樹脂は、硬化性樹脂であって、前記被覆工程は、前記硬化性樹脂を硬化させる工程を含み、前記充填工程の前に、前記絶縁樹脂の表面の異物を除去する除去工程を有することを特徴とする請求の範囲第7項または第8項に記載の半導体装置の製造方法。
- 前記絶縁樹脂および上層絶縁樹脂は、硬化性樹脂であって、前記充填工程に続いて、前記絶縁樹脂および前記上層絶縁樹脂を同時に硬化する硬化工程を有することを特徴とする請求の範囲第7項または第8項に記載の半導体装置の製造方法。
- 前記半導体チップの信号電極に導通する信号端子の少なくとも一部もしくは前記信号端子に導通するボンディングワイヤを、前記絶縁樹脂により被覆することを特徴とする請求の範囲第7項または第8項に記載の半導体装置の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009547019A JP5183642B2 (ja) | 2007-12-20 | 2008-12-09 | 半導体装置およびその製造方法 |
CN2008801209553A CN101933139B (zh) | 2007-12-20 | 2008-12-09 | 半导体装置及其制造方法 |
DE112008003425.7T DE112008003425B4 (de) | 2007-12-20 | 2008-12-09 | Verfahren zum Herstellen eines Halbleiterbauelements |
US12/801,603 US8710666B2 (en) | 2007-12-20 | 2010-06-16 | Semiconductor device and method for fabricating the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007328641 | 2007-12-20 | ||
JP2007-328641 | 2007-12-20 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/801,603 Continuation US8710666B2 (en) | 2007-12-20 | 2010-06-16 | Semiconductor device and method for fabricating the same |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2009081723A1 true WO2009081723A1 (ja) | 2009-07-02 |
Family
ID=40801030
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2008/072314 WO2009081723A1 (ja) | 2007-12-20 | 2008-12-09 | 半導体装置およびその製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8710666B2 (ja) |
JP (1) | JP5183642B2 (ja) |
CN (1) | CN101933139B (ja) |
DE (1) | DE112008003425B4 (ja) |
WO (1) | WO2009081723A1 (ja) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011114157A (ja) * | 2009-11-26 | 2011-06-09 | Mitsubishi Electric Corp | 電力変換装置 |
US20130285221A1 (en) * | 2011-01-07 | 2013-10-31 | Fuji Electric Co., Ltd | Semiconductor device and method of manufacturing same |
JP2014506014A (ja) * | 2011-11-09 | 2014-03-06 | 東莞勤上光電股▲ふん▼有限公司 | ハイパワーled放熱構造の製造プロセス |
US9399268B2 (en) | 2013-12-19 | 2016-07-26 | Fuji Electric Co., Ltd. | Laser welding method, laser welding jig, and semiconductor device |
US10083935B2 (en) | 2016-08-18 | 2018-09-25 | Fuji Electric Co., Ltd. | Semiconductor device and a manufacturing method of the semiconductor device |
DE112022000173T5 (de) | 2021-06-23 | 2023-07-20 | Fuji Electric Co., Ltd. | Halbleitermodul und verfahren zu dessen herstellung |
WO2024075463A1 (ja) * | 2022-10-07 | 2024-04-11 | 住友電気工業株式会社 | 半導体装置 |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2408260A1 (de) * | 2010-07-13 | 2012-01-18 | Saint-Gobain Glass France | Glasscheibe mit einem elektrischen Anschlusselement |
WO2012152542A1 (de) | 2011-05-10 | 2012-11-15 | Saint-Gobain Glass France | Scheibe mit einem elektrischen anschlusselement |
PL2708093T3 (pl) | 2011-05-10 | 2020-05-18 | Saint-Gobain Glass France | Szyba z elektrycznym elementem przyłączeniowym |
JP2014519149A (ja) | 2011-05-10 | 2014-08-07 | サン−ゴバン グラス フランス | 電気的な接続素子を備えているガラス板 |
JP5790196B2 (ja) * | 2011-06-23 | 2015-10-07 | 富士電機株式会社 | 半導体装置の製造方法 |
CN103534796B (zh) | 2011-08-10 | 2016-06-01 | 富士电机株式会社 | 半导体装置和半导体装置的制造方法 |
FR2986902A1 (fr) * | 2012-02-09 | 2013-08-16 | Pixinbio | Procede d'assemblage d'un dispositif portable d'analyse d'echantillon biologique |
CN102738099A (zh) * | 2012-06-05 | 2012-10-17 | 嘉兴斯达微电子有限公司 | 一种新型高可靠功率模块 |
KR101642754B1 (ko) * | 2012-08-24 | 2016-07-26 | 미쓰비시덴키 가부시키가이샤 | 반도체장치 |
CN103208473B (zh) * | 2012-12-15 | 2016-01-20 | 南京银茂微电子制造有限公司 | 采用激光焊接端子的功率模块 |
CN103887300A (zh) * | 2012-12-20 | 2014-06-25 | 浙江大学 | 具有高可靠性导热绝缘基板的功率igbt模块 |
CN103887246A (zh) * | 2012-12-20 | 2014-06-25 | 浙江大学 | 具有新型接合层的电力电子模块散热结构 |
CN103035590A (zh) * | 2012-12-25 | 2013-04-10 | 浙江大学 | 一种igbt功率模块 |
JP6028592B2 (ja) | 2013-01-25 | 2016-11-16 | 三菱電機株式会社 | 半導体装置 |
JP6171586B2 (ja) * | 2013-06-04 | 2017-08-02 | 富士電機株式会社 | 半導体装置 |
JP6398399B2 (ja) * | 2013-09-06 | 2018-10-03 | 富士電機株式会社 | 半導体装置およびその製造方法 |
CN103785980A (zh) * | 2014-01-27 | 2014-05-14 | 江苏德丽斯特半导体科技有限公司 | 大功率晶闸管导电柱和门极线焊接夹具 |
DE102014219585A1 (de) * | 2014-09-26 | 2016-03-31 | Robert Bosch Gmbh | Kontaktanordnung mit einem Schaltungsträger und einem Verbindungselement |
JP6325975B2 (ja) * | 2014-12-19 | 2018-05-16 | 新光電気工業株式会社 | リードフレーム、半導体装置 |
CN105990265B (zh) * | 2015-02-26 | 2019-04-05 | 台达电子工业股份有限公司 | 功率转换电路的封装模块及其制造方法 |
CN105047624B (zh) * | 2015-07-01 | 2017-11-24 | 四川广义微电子股份有限公司 | Igbt芯片导热模块及其制备方法 |
JP6711001B2 (ja) * | 2016-02-17 | 2020-06-17 | 富士電機株式会社 | 半導体装置及び製造方法 |
DE102017115879B4 (de) * | 2017-07-14 | 2021-07-22 | Semikron Elektronik Gmbh & Co. Kg | Verfahren zur Herstellung eines leistungselektronischen Submoduls mittels eines Schweißenverfahrens |
JP6987031B2 (ja) * | 2018-08-08 | 2021-12-22 | 三菱電機株式会社 | 電力用半導体装置及びその製造方法、並びに、電力変換装置 |
CN110418518B (zh) * | 2019-07-18 | 2020-12-11 | 烟台台芯电子科技有限公司 | 一种提高igbt模块端子焊接强度的工艺方法 |
JP7280789B2 (ja) | 2019-09-24 | 2023-05-24 | 株式会社東芝 | パワーモジュール |
JP6866913B2 (ja) * | 2019-10-24 | 2021-04-28 | 三菱電機株式会社 | 半導体装置 |
JP7562965B2 (ja) * | 2020-03-10 | 2024-10-08 | 富士電機株式会社 | 製造方法、製造装置、治具アセンブリ、半導体モジュールおよび車両 |
JP2022183503A (ja) * | 2021-05-31 | 2022-12-13 | 富士電機株式会社 | 半導体モジュールおよび半導体モジュールの製造方法 |
WO2023193928A1 (en) * | 2022-04-08 | 2023-10-12 | Hitachi Energy Switzerland Ag | Arrangement for a power module, power module and method for producing an arrangement for a power module |
CN115227956A (zh) * | 2022-07-26 | 2022-10-25 | 空芯微医疗科技(上海)有限责任公司 | 空心微针的制备方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000068447A (ja) * | 1998-08-26 | 2000-03-03 | Toyota Central Res & Dev Lab Inc | パワーモジュール |
JP2000252410A (ja) * | 1999-03-02 | 2000-09-14 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2007165690A (ja) * | 2005-12-15 | 2007-06-28 | Fuji Electric Holdings Co Ltd | ヒートスプレッダと金属板との接合方法 |
Family Cites Families (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3747051A (en) * | 1970-07-16 | 1973-07-17 | Amp Inc | Welding method and means using foil electrode |
JPS59181627A (ja) | 1983-03-31 | 1984-10-16 | Toshiba Corp | 半導体装置の製造方法 |
US4751199A (en) * | 1983-12-06 | 1988-06-14 | Fairchild Semiconductor Corporation | Process of forming a compliant lead frame for array-type semiconductor packages |
JPS60157243A (ja) | 1984-01-25 | 1985-08-17 | Mitsubishi Electric Corp | 半導体装置 |
JPS632360A (ja) * | 1986-06-20 | 1988-01-07 | Fujitsu Ltd | 回路部品の外部リ−ド接続方法 |
SG52794A1 (en) * | 1990-04-26 | 1998-09-28 | Hitachi Ltd | Semiconductor device and method for manufacturing same |
JP2816239B2 (ja) * | 1990-06-15 | 1998-10-27 | 株式会社日立製作所 | 樹脂封止型半導体装置 |
JPH0577944A (ja) | 1991-09-19 | 1993-03-30 | Canon Inc | 手差し給紙装置 |
JPH0577944U (ja) * | 1992-03-24 | 1993-10-22 | シチズン時計株式会社 | 水晶発振器 |
JPH0629459A (ja) * | 1992-07-08 | 1994-02-04 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2721093B2 (ja) * | 1992-07-21 | 1998-03-04 | 三菱電機株式会社 | 半導体装置 |
US5484959A (en) * | 1992-12-11 | 1996-01-16 | Staktek Corporation | High density lead-on-package fabrication method and apparatus |
JP3329073B2 (ja) * | 1993-06-04 | 2002-09-30 | セイコーエプソン株式会社 | 半導体装置およびその製造方法 |
JPH0794845A (ja) | 1993-09-20 | 1995-04-07 | Toppan Printing Co Ltd | 半導体素子搭載用基板および半導体装置 |
JPH07147347A (ja) * | 1993-11-25 | 1995-06-06 | Matsushita Electric Ind Co Ltd | 集積回路装置 |
US5473190A (en) * | 1993-12-14 | 1995-12-05 | Intel Corporation | Tab tape |
KR0147259B1 (ko) * | 1994-10-27 | 1998-08-01 | 김광호 | 적층형 패키지 및 그 제조방법 |
JP3201187B2 (ja) | 1994-12-08 | 2001-08-20 | 富士電機株式会社 | 半導体装置 |
US5661337A (en) * | 1995-11-07 | 1997-08-26 | Vlsi Technology, Inc. | Technique for improving bonding strength of leadframe to substrate in semiconductor IC chip packages |
US5844308A (en) * | 1997-08-20 | 1998-12-01 | Cts Corporation | Integrated circuit anti-bridging leads design |
TW434756B (en) * | 1998-06-01 | 2001-05-16 | Hitachi Ltd | Semiconductor device and its manufacturing method |
US6256200B1 (en) * | 1999-05-27 | 2001-07-03 | Allen K. Lam | Symmetrical package for semiconductor die |
JP3406270B2 (ja) * | 2000-02-17 | 2003-05-12 | 沖電気工業株式会社 | 半導体装置及びその製造方法 |
US6368899B1 (en) * | 2000-03-08 | 2002-04-09 | Maxwell Electronic Components Group, Inc. | Electronic device packaging |
KR20010095252A (ko) * | 2000-04-04 | 2001-11-03 | 도낀 가부시끼가이샤 | 고주파 전류 억제형 전자 부품 및 이를 위한 접합 와이어 |
US6818968B1 (en) * | 2000-10-12 | 2004-11-16 | Altera Corporation | Integrated circuit package and process for forming the same |
JP3563387B2 (ja) * | 2001-01-23 | 2004-09-08 | Necエレクトロニクス株式会社 | 半導体装置用導電性硬化樹脂及び半導体装置 |
US6791168B1 (en) * | 2002-07-10 | 2004-09-14 | Micron Technology, Inc. | Semiconductor package with circuit side polymer layer and wafer level fabrication method |
JP4078993B2 (ja) * | 2003-01-27 | 2008-04-23 | 三菱電機株式会社 | 半導体装置 |
TWI244173B (en) * | 2003-11-12 | 2005-11-21 | Optimum Care Int Tech Inc | Semiconductor chip package structure |
US6972372B1 (en) * | 2004-05-28 | 2005-12-06 | Macronix International Co., Ltd. | Method and apparatus for stacking electrical components using outer lead portions and exposed inner lead portions to provide interconnection |
DE102004058305B3 (de) * | 2004-12-02 | 2006-05-18 | Infineon Technologies Ag | Halbleiterbauteil mit einem eine Passivierungsschicht aufweisenden Halbleiterchip sowie Verfahren zur Herstellung desselben |
DE102005037321B4 (de) * | 2005-08-04 | 2013-08-01 | Infineon Technologies Ag | Verfahren zur Herstellung von Halbleiterbauteilen mit Leiterbahnen zwischen Halbleiterchips und einem Schaltungsträger |
TWI284407B (en) * | 2005-11-03 | 2007-07-21 | Cyntec Co Ltd | Package device with electromagnetic interference shield |
JP4335203B2 (ja) | 2005-11-30 | 2009-09-30 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
JP4842118B2 (ja) | 2006-01-24 | 2011-12-21 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US7298038B2 (en) * | 2006-02-25 | 2007-11-20 | Stats Chippac Ltd. | Integrated circuit package system including die stacking |
US8004075B2 (en) * | 2006-04-25 | 2011-08-23 | Hitachi, Ltd. | Semiconductor power module including epoxy resin coating |
JP5103863B2 (ja) * | 2006-10-16 | 2012-12-19 | 富士電機株式会社 | 半導体装置 |
JP2008227131A (ja) * | 2007-03-13 | 2008-09-25 | Renesas Technology Corp | 半導体装置及びその製造方法 |
US7868471B2 (en) * | 2007-09-13 | 2011-01-11 | Stats Chippac Ltd. | Integrated circuit package-in-package system with leads |
US7906860B2 (en) * | 2007-10-26 | 2011-03-15 | Infineon Technologies Ag | Semiconductor device |
-
2008
- 2008-12-09 CN CN2008801209553A patent/CN101933139B/zh active Active
- 2008-12-09 JP JP2009547019A patent/JP5183642B2/ja active Active
- 2008-12-09 WO PCT/JP2008/072314 patent/WO2009081723A1/ja active Application Filing
- 2008-12-09 DE DE112008003425.7T patent/DE112008003425B4/de active Active
-
2010
- 2010-06-16 US US12/801,603 patent/US8710666B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000068447A (ja) * | 1998-08-26 | 2000-03-03 | Toyota Central Res & Dev Lab Inc | パワーモジュール |
JP2000252410A (ja) * | 1999-03-02 | 2000-09-14 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2007165690A (ja) * | 2005-12-15 | 2007-06-28 | Fuji Electric Holdings Co Ltd | ヒートスプレッダと金属板との接合方法 |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011114157A (ja) * | 2009-11-26 | 2011-06-09 | Mitsubishi Electric Corp | 電力変換装置 |
US20130285221A1 (en) * | 2011-01-07 | 2013-10-31 | Fuji Electric Co., Ltd | Semiconductor device and method of manufacturing same |
US9136209B2 (en) * | 2011-01-07 | 2015-09-15 | Fuji Electric Co., Ltd. | Semiconductor device with specific lead frame for a power semiconductor module |
JP2014506014A (ja) * | 2011-11-09 | 2014-03-06 | 東莞勤上光電股▲ふん▼有限公司 | ハイパワーled放熱構造の製造プロセス |
US9399268B2 (en) | 2013-12-19 | 2016-07-26 | Fuji Electric Co., Ltd. | Laser welding method, laser welding jig, and semiconductor device |
US10442035B2 (en) | 2013-12-19 | 2019-10-15 | Fuji Electric Co., Ltd. | Laser welding method |
US10083935B2 (en) | 2016-08-18 | 2018-09-25 | Fuji Electric Co., Ltd. | Semiconductor device and a manufacturing method of the semiconductor device |
DE112022000173T5 (de) | 2021-06-23 | 2023-07-20 | Fuji Electric Co., Ltd. | Halbleitermodul und verfahren zu dessen herstellung |
WO2024075463A1 (ja) * | 2022-10-07 | 2024-04-11 | 住友電気工業株式会社 | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
JPWO2009081723A1 (ja) | 2011-05-06 |
CN101933139B (zh) | 2012-11-07 |
DE112008003425T5 (de) | 2010-10-28 |
DE112008003425B4 (de) | 2023-08-31 |
US20100295187A1 (en) | 2010-11-25 |
JP5183642B2 (ja) | 2013-04-17 |
US8710666B2 (en) | 2014-04-29 |
CN101933139A (zh) | 2010-12-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5183642B2 (ja) | 半導体装置およびその製造方法 | |
JP5090088B2 (ja) | 半導体装置およびその製造方法 | |
CN103035542B (zh) | 用于生产功率半导体设置的方法 | |
JP4924411B2 (ja) | 電力半導体装置 | |
JP4614586B2 (ja) | 混成集積回路装置の製造方法 | |
JP4078993B2 (ja) | 半導体装置 | |
WO2015111691A1 (ja) | 電極端子、電力用半導体装置、および電力用半導体装置の製造方法 | |
JP5239291B2 (ja) | 半導体装置およびその製造方法 | |
US20070172980A1 (en) | Semiconductor apparatus manufacturing method | |
JP2017224736A (ja) | 半導体装置、製造方法、及び導電性ポスト | |
JP4967701B2 (ja) | 電力半導体装置 | |
JP4798020B2 (ja) | 半導体装置およびその製造方法 | |
JP2008205058A (ja) | 半導体装置 | |
JP5233853B2 (ja) | 半導体装置 | |
JP5119139B2 (ja) | 半導体装置及び半導体装置の製造方法 | |
JP2002026067A (ja) | 半導体装置及びその実装方法 | |
TW201436667A (zh) | 電路板 | |
JP7055109B2 (ja) | 半導体装置 | |
JP2019133965A (ja) | 半導体装置及びその製造方法 | |
JP3658946B2 (ja) | 電力用トランジスタの実装構造 | |
JP2020184577A (ja) | 半導体装置の製造方法および接合材供給治具ならびにその製造方法 | |
JP2009224529A (ja) | 半導体装置およびその製造方法 | |
CN111354709A (zh) | 半导体装置及其制造方法 | |
US20220384321A1 (en) | Semiconductor module and method for fabricating the same | |
JP2014220329A (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 200880120955.3 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 08863509 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2009547019 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1120080034257 Country of ref document: DE |
|
RET | De translation (de og part 6b) |
Ref document number: 112008003425 Country of ref document: DE Date of ref document: 20101028 Kind code of ref document: P |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 08863509 Country of ref document: EP Kind code of ref document: A1 |