WO2007086551A1 - プリント配線板及びプリント配線板の製造方法 - Google Patents

プリント配線板及びプリント配線板の製造方法 Download PDF

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Publication number
WO2007086551A1
WO2007086551A1 PCT/JP2007/051354 JP2007051354W WO2007086551A1 WO 2007086551 A1 WO2007086551 A1 WO 2007086551A1 JP 2007051354 W JP2007051354 W JP 2007051354W WO 2007086551 A1 WO2007086551 A1 WO 2007086551A1
Authority
WO
WIPO (PCT)
Prior art keywords
opening
solder
small
diameter opening
diameter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/051354
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
Katsuhiko Tanno
Youichirou Kawamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP2007556031A priority Critical patent/JP4731574B2/ja
Priority to EP07707585A priority patent/EP1978556A1/en
Priority to CN2007800011165A priority patent/CN101356642B/zh
Publication of WO2007086551A1 publication Critical patent/WO2007086551A1/ja
Priority to US12/120,076 priority patent/US8087164B2/en
Anticipated expiration legal-status Critical
Priority to US13/274,897 priority patent/US9480170B2/en
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3465—Application of solder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/094—Array of pads or lands differing from one another, e.g. in size, pitch or thickness; Using different connections on the pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0278—Flat pressure, e.g. for connecting terminals with anisotropic conductive adhesive
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/041—Solder preforms in the shape of solder balls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/043—Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3465—Application of solder
    • H05K3/3478—Application of solder preforms; Transferring prefabricated solder patterns
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01221—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition
    • H10W72/01225—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition in solid form, e.g. by using a powder or by stud bumping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49139—Assembling to base an electrical component, e.g., capacitor, etc. by inserting component lead or terminal into base aperture
    • Y10T29/4914—Assembling to base an electrical component, e.g., capacitor, etc. by inserting component lead or terminal into base aperture with deforming of lead or terminal
    • Y10T29/49142—Assembling to base an electrical component, e.g., capacitor, etc. by inserting component lead or terminal into base aperture with deforming of lead or terminal including metal fusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147—Assembling terminal to base
    • Y10T29/49149—Assembling terminal to base by metal fusion bonding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
    • Y10T29/49167—Manufacturing circuit on or in base by forming conductive walled aperture in base with deforming of conductive path

Definitions

  • the present invention relates to a printed wiring board and a printed wiring board manufacturing method that can be suitably used for a nod / cage substrate that also has a build-up multilayer wiring board force for mounting an IC chip.
  • solder bumps are used for electrical connection between a knock substrate and an IC chip.
  • the solder bump is formed by the following process.
  • the IC chip is placed on the solder bumps, and the solder bumps and the IC chip nodes (terminals) are connected by reflow.
  • a printing technique using a ball alignment mask and a squeegee disclosed in Japanese Patent Application Laid-Open No. 2001-267731 is used.
  • Patent Document 1 JP 2001-267773 A
  • the solder balls having a small diameter are smaller than the sand grains.
  • the solder balls are deformed by the squeegee and the height of the solder bumps is increased. Variations in thickness result in quality degradation. That is, when the diameter of the solder ball is reduced, the weight ratio with respect to the surface area is reduced, and the solder ball adsorption phenomenon due to intermolecular force occurs.
  • solder balls that tend to agglomerate are sent in contact with the squeegee, so that the solder balls are damaged and some of them are chipped.
  • the volume of the solder bump will be different on each connection pad, resulting in variations in the height of the solder bump as described above.
  • the bumps constituting the power supply line and the ground line are required to have a large diameter so that a large current can flow.
  • the pads and bumps constituting the signal line are required to have a small diameter. For this reason, as shown in FIG. 17A, the present applicant provides a large-diameter opening solder bump 78P (large solder volume) in the large-diameter opening 71P of the solder resist layer 70 for power supply and grounding.
  • One of the objects of the present invention is to form bumps at substantially the same height on connection pads (conductor circuits having different sizes exposed from the solder resist layer) having different solder resist opening diameters.
  • An object of the present invention is to provide a printed wiring board and a method for manufacturing the printed wiring board.
  • the method of manufacturing a printed wiring board having bumps according to claim 1 is characterized by at least the following steps (a) to (d):
  • solder resist layer having a small-diameter opening and a large-diameter opening that expose the connection pad
  • interlayer resin insulation layers and conductor layers are alternately laminated on a core substrate having through-hole conductors that conduct between the front surface and the back surface, and each of the conductor layers has a barrier. Connected by via-hole conductors, and a solder resist layer is provided on the outermost layer. Opening force of one resist layer In a multilayer printed wiring board in which a part of the exposed conductor layer constitutes a pad for mounting an electronic component, and a solder bump is formed on the pad, the opening is a relative A small-diameter opening having a small diameter and a large-diameter opening having a relatively large diameter,
  • the solder bumps formed in the small-diameter opening and the large-diameter opening have the same volume, and the solder bump formed in the small-diameter opening is flattened to form the small-diameter opening.
  • the technical feature is that the heights of the solder bumps formed and the solder bumps formed in the large-diameter opening are adjusted to approximate each other.
  • a low melting point metal sphere is mounted on the large-diameter opening and the small-diameter opening of the solder resist layer using a mask. Reflow is performed to form bumps with a low height from the low melting point metal sphere at the small opening in the solder resist layer, and bumps with a low melting point metal ball at the large opening in the solder resist layer. After that, hold down the bump with the high height of the small-diameter opening, and make it almost the same height as the bump with the small opening of the large-diameter opening.
  • the bump can be formed at substantially the same height, and the bump force of the small diameter opening and the bump of the large diameter opening and the amount of low melting point metal Because of the same, when an IC chip is mounted via a bump with a small diameter opening and a bump with a large diameter opening, there is no connection between the bumps with a small diameter opening, and the connection reliability between the IC chip and the printed wiring board It becomes possible to ensure the sex.
  • the cylindrical member is positioned above the mask, and the low melting point metal balls are gathered by sucking air from the opening of the cylindrical member, so that the cylindrical member or the printed wiring board and the mask are placed horizontally.
  • the low melting point metal spheres gathered immediately below the cylindrical member are moved and dropped to the small-diameter opening and large-diameter opening of the solder resist layer through the opening of the mask. For this reason, the fine low melting point metal sphere can be surely mounted on all the openings of the solder resist layer.
  • the low melting point metal sphere since the low melting point metal sphere is moved in a non-contact manner, unlike the case of using a squeegee, the low melting point metal sphere can be mounted in a small diameter opening and a large diameter opening without damaging the bump. Can be made uniform. Furthermore, a low-melting-point metal sphere can be appropriately placed in the opening even on a printed wiring board with many undulations on the surface, such as a build-up multilayer wiring board. [0010] In the printed wiring board according to claim 3, even if the solder resist opening diameter is different, the solder bump formed on the small-diameter opening is flattened, so that the solder bump having the same volume and the small-diameter opening can be obtained.
  • the power line and the grounding pad are formed in a large-diameter opening, and the wiring length is shortened by mainly disposing the pad on the center side of the printed wiring board, and the resistance value is reduced.
  • the resistance value is reduced.
  • the wiring density is increased, and the small-diameter opening is mainly disposed on the outer peripheral side of the large-diameter opening on the center side.
  • the solder bump of the small diameter opening with the plate material for fluttering having the opening corresponding to the part where the opening of the diameter is formed, and solder the solder bump of the small diameter opening with the same volume to the large diameter opening. Solder bumps are approximated to height to ensure connection reliability.
  • the solder bump formed on the small-diameter opening is flattened, so that the solder bump having the same volume and the small-diameter opening can be obtained.
  • the height of the solder bump of the large diameter opening is approximated to 10 m, and the solder bump force of the small diameter opening is the same volume as the solder bump of the large diameter opening.
  • solder ball 77 is placed on the connection pad of the multilayer printed wiring board.
  • the solder ball mounting apparatus to be mounted will be described with reference to FIG.
  • FIG. 14 (A) is a configuration diagram showing the configuration of the solder ball mounting device according to one embodiment of the present invention
  • FIG. 14 (B) shows the solder ball mounting device of FIG. It is an arrow view seen.
  • the solder ball mounting device 100 positions and holds the multilayer printed wiring board 10.
  • FIG. 11 shows a cross-sectional view of the multilayer printed wiring board 10.
  • FIG. 12 shows a state in which the IC chip 90 is attached to the multilayer printed wiring board 10 shown in FIG.
  • FIG. 13 shows a plan view of the multilayer printed wiring board 10 before the IC chip is attached.
  • the number of solder bumps 78P and solder bumps 78S shown in FIG. 13 is reduced and schematically shown. In an actual package substrate, several hundred solder bumps 78P and solder bumps 78S are provided.
  • a conductor circuit 34 is formed on the surface of the core substrate 30.
  • the front surface and the back surface of the core substrate 30 are connected through a through hole 36.
  • an interlayer resin insulation layer 50 in which via holes 60 and conductor circuits 58 are formed, and an interlayer resin insulation layer 150 in which via holes 160 and conductor circuits 158 are formed are disposed on the core substrate 30.
  • a solder layer is formed on the upper layer of the via hole 160 and the conductor circuit 158.
  • a dies layer 70 is formed.
  • the solder bump 78P for grounding is disposed, and the solder bump 78S for signal is provided on the node 73S of the small diameter opening 71S.
  • the power supply and grounding solder bumps 78P and the signal solder bumps 78S have the same volume of solder ball force as described later so as to have the same volume.
  • the height HI of the large-diameter opening solder bump 78P is about 3, and the height H2 of the small-diameter opening solder bump 78S is about 30 / zm, which is the same as the height of the large-diameter opening solder bump 78P by fluttering. Is set.
  • the large-diameter opening solder bumps 78P for power supply and ground are often arranged near the center of the multilayer printed wiring board so as to shorten the wiring distance, and the small-diameter opening solder bumps 78S for signals are relatively outward. Arranged on the outer peripheral side of the large-diameter opening solder bump 78P.
  • Solder bumps 78D are formed on the lower surface side of the multilayer printed wiring board through the openings 71 of the solder resist layer 70.
  • the opening of the solder resist is formed so as to expose a part of the conductor circuit 158, but the opening is formed so as to include only the via hole 160 or the via hole 160 and a part of the conductor circuit 158. May be.
  • solder bumps 78P are connected to the power supply and grounding electrode 92P of the IC chip 90 for signal use.
  • the small-diameter opening solder bump 78S is connected to the signal electrode 92S.
  • the solder bump 78D on the lower surface side is connected to the land 96 of the daughter board 94!
  • the power supply line and the grounding pad 73P are provided with a large-diameter opening. It is formed on 71 P and is mainly placed on the center side of the multilayer printed wiring board 10 (area in the dotted line PL), thereby shortening the wiring length from the IC chip 90 to the daughter board 94 and lowering the resistance value. As a result, the drop in supply voltage when power consumption instantaneously increases in the IC chip 90 is reduced, and malfunction of the IC chip 90 is prevented.
  • the wiring density is increased by forming the signal pad 73S disposed in the area indicated by the broken line SL on the outer periphery of the dotted line PL in the small-diameter opening 71S.
  • solder resist openings for signal lines on the knock board are even smaller.
  • diameter reduction and pitch reduction are not desired to be able to cope with the instantaneous increase in power consumption of the IC chip.
  • solder bumps which also have a solder alloy strength, are reduced in diameter, the resistance value increases, causing a voltage drop when the power consumption increases momentarily, causing malfunctions in the IC chip.
  • the solder resist opening for the signal line is made smaller, and the solder bump for the power supply ground is not made smaller.
  • filler 37 containing copper particles with an average particle size of 10 ⁇ m is screen-printed on through hole 36. Fill, dry, and cure (Fig. 2 (A)). This is applied to the substrate on which a mask having an opening in the through hole portion is placed by a printing method so that the through hole is filled, and after filling, dried and cured.
  • the filler 37 protruding from the through hole 36 is removed by belt sander polishing using # 600 belt polishing paper (manufactured by Sankyo Rikagaku), and further, scratches due to this belt sander polishing are removed. Puff polishing is performed to flatten the surface of the substrate 30 (see FIG. 2 (B)). In this way, the substrate 30 is obtained in which the side wall conductor layer 36b of the through hole 36 and the resin filler 37 are firmly adhered to each other through the rough layer 36 ⁇ .
  • a palladium catalyst (manufactured by Atotech) is applied to the surface of the substrate 30 flattened in the above (3), and electroless copper plating is applied, so that electroless copper having a thickness of 0.6 m is obtained.
  • a plating film 23 is formed (see FIG. 2C).
  • electrolytic copper plating is performed under the following conditions to form an electrolytic copper plating film 24 with a thickness of 15 m, thickening of the portion that becomes the conductor circuit 34, and filling of the through hole 36 A portion to be a lidded layer (through-hole land) covering the filled filler 37 is formed (Fig. 2 (D)).
  • electrolytic plating solution [Electrolytic plating solution]
  • the plating films 23 and 24 and the copper foil 32 in portions where the etching resist 25 is not formed are dissolved and removed with an etching solution mainly composed of salty cupric copper, and further, The etching resist 25 is stripped and removed with 5% KOH to form an independent conductor circuit 34 and a lid plating layer 36a covering the filler 37 (see FIG. 3A).
  • Product: Product name; ABF-45SH) 50 y is placed on the substrate, cut by temporary pressure bonding under conditions of pressure 0.445MPa, temperature 80 ° C, pressure bonding time 10 seconds, and further by the following method
  • An interlayer resin insulating layer 50 was formed by pasting using a vacuum laminator apparatus (FIG. 3 (C)).
  • the resin film for the interlayer resin insulation layer is subjected to main pressure bonding on the substrate under the conditions of a vacuum of 67 Pa, a pressure of 0.4 Mpa, a temperature of 85 ° C., a pressure bonding time of 60 seconds, and then at 170 ° C. for 40 minutes. Heat cured.
  • catalyst nuclei are attached to the surface of the interlayer resin insulation layer and the inner wall surface of the via hole opening.
  • the above substrate is made of palladium chloride (PbCl) and salt stannic acid (SnCl
  • the catalyst was applied by dipping in a catalyst solution containing 2) and depositing palladium metal.
  • the thickness of the lower conductor circuit 58 was 15 m (Fig. 5 (A)). However, the thickness of the lower conductor circuit may be between 5 and 25 / ⁇ ⁇ .
  • solder resist composition 70 is applied to both sides of the multilayer wiring board to a thickness of 20 ⁇ m, and the conditions are 70 minutes at 20 ° C. and 30 minutes at 70 ° C. After the drying process, a photomask with a thickness of 5 mm on which the pattern of the opening of the solder resist is drawn is brought into close contact with the solder resist layer 70 and exposed to UV light of lOOOiuJ / cm 2 and developed with a DMTG solution.
  • a part of the conductor circuit 158 is inserted into the small-diameter opening 71S with a large-diameter pad 73P formed by exposing a part of A small-diameter pad 73S was provided (Fig. 5 (C)).
  • solder resist layer is cured by heating at 80 ° C for 1 hour, at 100 ° C for 1 hour, at 120 ° C for 1 hour, and at 150 ° C for 3 hours, and has an opening. Then, a solder resist pattern layer having a thickness of 15 to 25 ⁇ m was formed.
  • the substrate is potassium gold cyanide (7.6 X 10— 3 molZD, ammonium chloride (1.9 X 10— ⁇ ⁇ ), sodium taenoate (1.2 X 10— imol / l) Immerse it in a non-electrolytic plating solution containing sodium phosphite (1.7 X 10— ⁇ ⁇ / ⁇ ) at 80 ° C for 7.5 minutes to form a thickness of 0. 03 / zm gold-plated layer 74 was formed (Fig. 5 (D)) In addition to the nickel-gold layer, a single layer of tin, a precious metal layer (gold, silver, noradium, platinum, etc.) was formed. May be.
  • the alignment mark 34M on the multilayer printed wiring board 10 is recognized by the alignment force mela 146, and the position of the multilayer printed wiring board 10 with respect to the ball alignment mask 16 is to correct. That is, the positions of the openings 16a of the ball alignment mask 16 are adjusted so as to correspond to the small diameter openings 71S and the large diameter openings 71P of the multilayer printed wiring board 10, respectively.
  • a solder ball 77 (diameter 75 m, Sn 63Pb37 (manufactured by Hitachi Metals)) is quantitatively supplied from the solder ball supply device 122 to the mounting cylinder 124 side. It may be supplied in advance in the mounting cylinder. In the embodiment, the force using SnZPb solder for the solder ball Sn and Pb-free solder in which group forces such as Ag, Cu, In, Bi, Zn, etc. are selected may be used.
  • (III) Solder ball mounting As shown in FIG. 7A, the mounting cylinder 124 is positioned above the ball alignment mask 16 while maintaining a predetermined clearance (for example, 0.5 to 4 times the ball diameter) with the ball alignment mask. By sucking air from the suction part 124b, the flow velocity in the gap between the mounting cylinder and the printed wiring board is set to 5 m / sec to 35 m / sec, and the ball alignment mask just below the opening 124A of the mounting cylinder 124 Solder balls 77 were combined on 16.
  • a predetermined clearance for example, 0.5 to 4 times the ball diameter
  • the mounting cylinders 124 arranged along the Y axis of the multilayer printed wiring board 10 shown in FIGS. 7 (B), 8 (A), FIG. 14 (B), and FIG. Sends horizontally along the X-axis via the X-direction moving axis 140.
  • the solder balls 77 assembled on the ball alignment mask 16 are moved along with the movement of the mounting cylinder 124, and the small diameter openings 71S of the multilayer printed wiring board 10 are passed through the openings 16a of the ball alignment mask 16. And drop into the large-diameter opening 71P and mount it.
  • the solder balls 77 are sequentially aligned on all the connection pads on the multilayer printed wiring board 10 side.
  • the mounting cylinder 124 is moved, but instead, with the mounting cylinder 124 fixed, the multilayer printed wiring board 10 and the ball alignment mask 16 are moved to gather just below the mounting cylinder 124.
  • the solder balls 77 thus made can be mounted on the small-diameter opening 71S and the large-diameter opening 71P of the multilayer printed wiring board 10 through the openings 16a of the ball alignment mask 16.
  • solder ball 77 on the upper surface is melted by reflowing at 230 ° C, and the height of the solder ball 77 from the large diameter opening 71P is low (HI 30 m: surface of the solder resist layer)
  • Solder bump 78S was formed on the lower surface, and solder bump 78D was formed on the lower surface (FIG. 9).
  • solder bump 78S having a small diameter 71S and a high height is formed.
  • Flattened, large-diameter opening 71P Solder bump Same height as 78P (HI 30 ⁇ m) (H2 30 ⁇ m) (Fig. 11). This flat plate 80 can be heated!
  • the small-diameter opening 71S is mainly disposed on the outer peripheral side of the large-diameter opening 71P on the center side, so that the opening 80A corresponding to the portion where the large-diameter opening 71P is formed is provided.
  • the connection pads of the printed wiring board and the electrodes of the IC chip 90 are connected via the solder bumps 78P and 78S.
  • the solder bump 78S force of the small-diameter opening 71S has the same amount of solder as the solder bump 78P of the large-diameter opening 71P, so that no connection occurs in the solder bump 78S of the small-diameter opening 71S, and the IC chip 90 Connection reliability with the multilayer printed wiring board 10 can be ensured.
  • it is attached to the daughter board 94 via the solder bump 78D (FIG. 12).
  • the solder bumps 78S having the small diameters 78S and the high heights are flattened so that the solder bumps 71S having the different diameters 71S and the solder bumps 78P having the large diameters 71P are substantially the same. Can be formed at a height. Therefore, when IC chip 90 is mounted via solder bump 78S and solder bump 78P, the mounting yield of the IC chip can be increased, and the connection reliability between IC chip 90 and multilayer printed wiring board 10 is ensured. It becomes possible to do.
  • the solder bump 78P of the large-diameter opening 71P for power supply and grounding is maintained in a semi-circular shape without fluttering, so that voids are removed during reflow when mounting an IC chip. Air voids are not easily generated in the solder bumps, and it is difficult to achieve high resistance, which is advantageous for power supply.
  • the mounting cylinder 124 is positioned above the ball alignment mask 16, and the solder balls 77 are combined by sucking air from the mounting cylinder 124, thereby mounting the mounting cylinder 124. Or, by moving the printed wiring board and the ball alignment mask 16 relative to each other in the horizontal direction, the solder balls 77 assembled just below the mounting cylinder 124 are moved over the ball alignment mask 16 to provide a ball alignment mask.
  • the multi-layer printed wiring board 10 is dropped into the small-diameter opening 71S and the large-diameter opening 71P through the 16 openings 16a.
  • the fine solder balls 77 can be reliably mounted on all the small diameter openings 71S and the large diameter openings 71P of the multilayer printed wiring board 10.
  • the solder ball 77 since the solder ball 77 is moved in a non-contact manner, unlike the case of using a squeegee, the solder ball can be mounted in the small diameter opening 71S and the large diameter opening 71P without damaging the solder balls 78S, 78P. Can be made uniform. Further, since the solder balls are guided by the suction force, the aggregation and adhesion of the solder balls can be prevented. Solder bumps with a uniform height and large volume become solder bumps that have low resistance against heat and have high resistance to thermal shock, which is advantageous for power supply.
  • the height of the small-diameter solder bump 78S is 30 ⁇ m, and the height of the large-diameter solder bump 78S is 30 / z m.
  • the small height solder bump 78S was flattened.
  • the solder bumps 78S and the solder bumps 78P have the same volume due to the force of the solder balls having the same diameter as in the first embodiment.
  • FIG. 16 schematically shows a solder bump 78S of a small-diameter opening 71S flattened as a whole and a large-diameter opening 71S flattened only at the top.
  • the second embodiment has an advantage that the height of all the solder bumps can be made uniform.
  • FIG. 1 is a process diagram showing a method for producing a multilayer printed wiring board according to a first embodiment of the present invention.
  • FIG. 2 is a process diagram showing a method for producing the multilayer printed wiring board according to the first embodiment.
  • FIG. 3 is a process diagram showing a method for producing the multilayer printed wiring board according to the first embodiment.
  • FIG. 4 is a process diagram showing a method for producing the multilayer printed wiring board according to the first embodiment.
  • FIG. 5 is a process diagram showing a method for producing the multilayer printed wiring board according to the first embodiment.
  • FIG. 6 is a process diagram showing a method for producing the multilayer printed wiring board according to the first embodiment.
  • FIG. 7 is a process diagram showing a method for producing the multilayer printed wiring board according to the first embodiment.
  • FIG. 8 is a process diagram showing a method for producing the multilayer printed wiring board according to the first embodiment.
  • FIG. 9 is a process diagram showing a method for producing the multilayer printed wiring board according to the first embodiment.
  • FIG. 10 is a process diagram showing a method for producing the multilayer printed wiring board according to the first embodiment.
  • FIG. 11 is a cross-sectional view of the multilayer printed wiring board according to the first embodiment.
  • FIG. 12 is a cross-sectional view showing a state where an IC chip is mounted on the multilayer printed wiring board shown in FIG.
  • FIG. 13 is a plan view of the multilayer printed wiring board according to the first embodiment.
  • FIG. 14 (A) is a configuration diagram showing the configuration of the solder ball mounting device according to the embodiment of the present invention
  • FIG. 14 (B) is an arrow indicating the solder ball mounting device of FIG. 14 (A). It is an arrow view also seeing B side force.
  • FIG. 15 is a process diagram showing a method for producing a multilayer printed wiring board according to the second embodiment of the present invention.
  • FIG. 16 is a cross-sectional view of the multilayer printed wiring board according to the second embodiment.
  • FIG. 17 (A) is an explanatory view showing solder bumps with different diameters in the prior art
  • FIG. 17 (B) is an explanatory view showing solder bumps after reflow.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
PCT/JP2007/051354 2006-01-27 2007-01-29 プリント配線板及びプリント配線板の製造方法 Ceased WO2007086551A1 (ja)

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JP2007556031A JP4731574B2 (ja) 2006-01-27 2007-01-29 プリント配線板及びプリント配線板の製造方法
EP07707585A EP1978556A1 (en) 2006-01-27 2007-01-29 Printed-circuit board, and method for manufacturing the same
CN2007800011165A CN101356642B (zh) 2006-01-27 2007-01-29 印刷线路板及其印刷线路板的制造方法
US12/120,076 US8087164B2 (en) 2006-01-27 2008-05-13 Printed wiring board and a method of manufacturing a printed wiring board
US13/274,897 US9480170B2 (en) 2006-01-27 2011-10-17 Printed wiring board and a method of manufacturing a printed wiring board

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JP2006-019065 2006-01-27

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JPH11204687A (ja) * 1998-01-19 1999-07-30 Juki Corp バンプ形成方法及びバンプ形成装置
JP2001210749A (ja) * 2000-01-26 2001-08-03 Kyocera Corp バンプ電極付き配線基板およびその製造方法
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JP2009224625A (ja) * 2008-03-17 2009-10-01 Ngk Spark Plug Co Ltd はんだバンプを有する配線基板及びその製造方法
US8143534B2 (en) 2008-03-17 2012-03-27 Ngk Spark Plug Co., Ltd. Wiring board having solder bump and method for manufacturing the same
KR101536006B1 (ko) * 2008-03-17 2015-07-10 니혼도꾸슈도교 가부시키가이샤 솔더범프를 가지는 배선기판 및 그 제조방법
JP2017139463A (ja) * 2016-02-05 2017-08-10 サムソン エレクトロ−メカニックス カンパニーリミテッド． プリント回路基板及びこれを含むパッケージ基板
KR20170093452A (ko) * 2016-02-05 2017-08-16 삼성전기주식회사 인쇄회로기판 및 이를 포함하는 패키지 기판
JP7031942B2 (ja) 2016-02-05 2022-03-08 サムソン エレクトロ－メカニックス カンパニーリミテッド． プリント回路基板及びこれを含むパッケージ基板
KR102632351B1 (ko) 2016-02-05 2024-02-02 삼성전기주식회사 인쇄회로기판 및 이를 포함하는 패키지 기판
JP2021005609A (ja) * 2019-06-26 2021-01-14 イビデン株式会社 プリント配線板およびその製造方法
JP7257273B2 (ja) 2019-06-26 2023-04-13 イビデン株式会社 プリント配線板およびその製造方法

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EP1978556A1 (en) 2008-10-08
CN101888747B (zh) 2012-09-05
US8087164B2 (en) 2012-01-03
CN101356642A (zh) 2009-01-28
KR20080017431A (ko) 2008-02-26
TW200742515A (en) 2007-11-01
CN101888747A (zh) 2010-11-17
US20120031659A1 (en) 2012-02-09
US9480170B2 (en) 2016-10-25
CN101356642B (zh) 2010-09-01

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