CN101888747B - 印刷线路板的制造方法 - Google Patents

印刷线路板的制造方法 Download PDF

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Publication number
CN101888747B
CN101888747B CN2010102198697A CN201010219869A CN101888747B CN 101888747 B CN101888747 B CN 101888747B CN 2010102198697 A CN2010102198697 A CN 2010102198697A CN 201010219869 A CN201010219869 A CN 201010219869A CN 101888747 B CN101888747 B CN 101888747B
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Prior art keywords
diameter opening
solder
mask
mentioned
opening
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Expired - Fee Related
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CN2010102198697A
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CN101888747A (zh
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丹野克彦
川村洋一郎
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Ibiden Co Ltd
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Ibiden Co Ltd
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Abstract

本发明提供一种印刷线路板及其印刷线路板的制造方法,该制造方法可以在阻焊层的开口直径不同的连接焊盘上以大致相同的高度形成凸块。由被搭载在阻焊层(70)的小直径开口(71S)上的焊锡球(77)形成为高度较高的小直径凸块(78S),平坦化该小直径凸块(78S),使其与大直径开口(71P)的焊锡凸块(78P)高度相同。小直径开口(71S)的焊锡凸块(78S)与大直径开口(71P)的焊锡凸块(78P)的焊锡量相同,使用小直径开口(71S)的焊锡凸块(78S)不会产生未连接,可以确保IC芯片(90)与多层印刷线路板(10)的连接可靠性。

Description

印刷线路板的制造方法
本申请是申请日为2007年01月29日、申请号为200780001116.5(PCT/JP2007/051354)、发明名称为“印刷线路板及其印刷线路板的制造方法”的申请的分案申请。 
技术领域
本发明涉及可适用于安装IC芯片用封装基板的印刷线路板及印刷线路板的制造方法,该封装基板由积层式多层印刷线路板构成。 
背景技术
为了电连接封装基板与IC芯片,而采用了焊锡凸块。由以下工序形成焊锡凸块。 
(1)在形成在封装基板上的连接焊盘上印刷焊剂。 
(2)在印刷了焊剂的连接焊盘上搭载焊锡球。 
(3)进行回流焊由焊锡球形成焊锡凸块。 
在封装基板上形成了焊锡凸块后,在焊锡凸块上载置IC芯片,通过回流焊使焊锡凸块与IC芯片的焊盘(端子)相连接,由此将IC芯片安装在封装基板上。在将上述焊锡球搭载在连接焊盘上的过程中,使用例如专利文献1中公开的并用球排列用掩模与刮板的印刷技术。 
专利文献1:日本特开2001-267731号 
但是,小直径的焊锡球比砂粒小,使用在日本特开2001-267731号中的并用球排列用掩模与刮板的方法,用刮板使焊锡球变形,出现焊锡凸块的高度参差不齐,品质降低。即,当焊锡球直径小时,则相对于表面积的重量比变小,产生由分子间引力所引起的焊锡球的吸附现象。在现有技术中,由于使刮板接触易于聚集的焊锡球来输送该焊锡球,因此会损伤焊锡球而使其产生局部欠缺。当焊锡球缺少一部分时,使得在各连接焊盘上焊锡凸块的体积变得不同,因此如上述那样产生焊锡凸块的高度参差不齐。 
另外,随着IC芯片的高速化,为了可流过大电流,要求构成电源线、地线的凸块为大直径,另一方面,随着IC芯片的高集成化,要求构成信号线的焊盘、凸块为小直径。因此,本申请人研究了如图17(A)所示那样在阻焊层70的大直径开口71P上设置大直径开口焊锡凸块78P(焊锡体积大)作为电源线、地线用焊锡凸块、在小直径开口71S上设置小直径开口焊锡凸块78S(焊锡体积小)作为信号线用焊锡凸块的方法。但是,在如图17(A)所示的结构中,可知:安装了IC芯片时,如图17(B)所示那样构成小直径开口焊锡凸块78S的焊锡向IC芯片90的焊盘92侧流出,在IC芯片的焊盘92与印刷线路板的焊盘158之间产生断线。 
发明内容
本发明的目的之一是提供一种可以在阻焊层的开口直径不同的连接焊盘(从阻焊层露出的大小不同的导体电路)上以大致相同的高度形成凸块的印刷线路板及印刷线路板的制造方法。 
本发明的另一目的是提供一种安装性成品率高、安装后的连接可靠性高的印刷线路板及印刷线路板的制造方法。 
为了达成上述目的,技术方案1是一种印刷线路板的制造方法,该印刷线路板为多层印刷线路板,该印刷线路板是这样形成的:在具有导通正面与背面的通孔导体的芯基板上交替层 叠层间树脂绝缘层和导体层,由导通孔导体将各导体层之间连接,在最外层设有阻焊层,将从该阻焊层开口露出的导体层的一部分构成为用于安装电子部件的焊盘,在该焊盘上形成有焊锡凸块,该印刷线路板的制造方法至少具有以下(a)~(d)工序: 
(a)形成具有使连接焊盘露出的小直径开口与大直径开口的阻焊层, 
(b)使用掩模,在上述阻焊层的小直径开口及大直径开口上搭载低熔点金属球,该掩模具有与上述阻焊层的小直径开口及大直径开口相对应的开口部, 
(c)进行回流焊,由上述小直径开口的低熔点金属球形成高度较高的凸块,由上述大直径开口的低熔点金属球形成高度较低的凸块, 
(d)从上方按压上述小直径开口的高度较高的凸块,使其高度与上述大直径开口的高度较低的凸块的高度相同。 
另外,在技术方案3的印刷线路板中,该印刷线路板为多层印刷线路板,该印刷线路板是这样形成的:在具有导通正面与背面的通孔导体的芯基板上交替层叠层间树脂绝缘层和导体层,由导通孔导体将各导体层之间连接,在最外层设有阻焊层,将从该阻焊层开口露出的导体层的一部分构成为用于安装电子部件的焊盘,在该焊盘上形成有焊锡凸块,该印刷线路板的特征在于, 
上述开口由具有相对较小直径的小直径开口和具有相对较大直径的大直径开口构成, 
形成在上述小直径开口及上述大直径开口的焊锡凸块具有相同的体积,并且,通过使形成在上述小直径开口的焊锡凸块平坦化来进行调整,使得形成在该小直径开口的焊锡凸块的高度与形成在上述大直径开口的焊锡凸块的高度相同。 
在技术方案1中,使用掩模,在阻焊层的大直径开口与小 直径开口搭载低熔点金属球。进行回流焊,在阻焊层的小直径开口处由小直径开口的低熔点金属球形成高度较高的凸块,在阻焊层的大直径开口处由大直径开口的低熔点金属球形成高度较低的凸块。其后,从上方按压小直径开口的高度较高的凸块,使其与大直径开口的高度较低的凸块高度大致相同。因此,即使用于露出连接焊盘的阻焊层开口直径不同,也可以以大致相同高度形成凸块,另外,小直径开口的凸块的低熔点金属量与大直径开口的凸块的低熔点金属量相同,因此,通过小直径开口的凸块与大直径开口的凸块搭载IC芯片时,在小直径开口的凸块不会出现未连接,可以确保IC芯片与印刷线路板的连接可靠性。 
在技术方案2中,使筒构件位于掩模的上方,通过从该筒构件的开口部吸引空气来聚集低熔点金属球,通过使筒构件或者印刷线路及掩模在水平方向上相对移动,使聚集到筒构件正下方的低熔点金属球移动,从而使聚集的低熔点金属球通过掩模的开口部向阻焊层的小直径开口与大直径开口落下。因此,可以确保将微细的低熔点金属球搭载在阻焊层的所有开口上。另外,以非接触的方式使低熔点金属球移动,与使用刮板时不同,可以不对低熔点金属球产生损伤地将低熔点金属球搭载在小直径开口与大直径开口上,可以使凸块的高度均匀。另外,即使是如积层式多层线路板那样的、表面起伏较多的印刷线路板上也可以适当地将低熔点金属球搭载在开口上。 
在技术方案3的印刷线路板中,阻焊层开口直径不同,通过使形成在上述小直径开口处的焊锡凸块平坦化,使体积相同的小直径开口的焊锡凸块与大直径开口的焊锡凸块的高度近似,另外,小直径开口的焊锡凸块与大直径开口的焊锡凸块的体积相同,因此,通过小直径开口的焊锡凸块与大直径开口的焊锡凸块搭载IC芯片时,在小直径开口的焊锡凸块搭载IC芯片 不会出现未连接,可以确保IC芯片与印刷线路板的连接可靠性。 
在技术方案4的印刷线路板中,在大直径开口处形成作为电源线、地线用的焊盘,并将该焊盘主要配置在印刷线路板的中心侧,从而可缩短布线长度,降低电阻值,由此,可以降低瞬时耗电增大时的电压下降,防止IC芯片的误动作。另外,不进行平坦化,保持半圆形状,从而在进行搭载IC芯片时进行回流焊之际,容易除去空隙,可以防止由于空隙使电阻值变大。另一方面,在小直径开口上形成信号用焊盘,从而可提高布线密度,并且,将该小直径开口主要配置在中心侧的大直径开口的外周侧,从而使用平坦化用板材使该小直径开口的焊锡凸块平坦化,使同一体积的小直径开口的焊锡凸块与大直径开口的焊锡凸块的高度近似,确保连接可靠性。上述平坦化用板材具有与形成大直径开口的部位相对应的开口部, 
在技术方案5的印刷线路板中,即使阻焊层开口直径不同,通过将形成在小直径开口的焊锡凸块平坦化,也可以使同一体积的小直径开口的焊锡凸块与大直径开口的焊锡凸块的高度之差接近10μm,另外,小直径开口的焊锡凸块与大直径开口的焊锡凸块的体积相同,因此,通过小直径开口的焊锡凸块与大直径开口的焊锡凸块搭载IC芯片时,在小直径开口的焊锡凸块不会出现未连接,可以确保IC芯片与印刷线路板连接可靠性。 
附图说明
图1是表示本发明的第1实施例的多层印刷线路板的制造方法的工序图。 
图2是表示第1实施例的多层印刷线路板的制造方法的工序图。 
图3是表示第1实施例的多层印刷线路板的制造方法的工 序图。 
图4是表示第1实施例的多层印刷线路板的制造方法的工序图。 
图5是表示第1实施例的多层印刷线路板的制造方法的工序图。 
图6是表示第1实施例的多层印刷线路板的制造方法的工序图。 
图7是表示第1实施例的多层印刷线路板的制造方法的工序图。 
图8是表示第1实施例的多层印刷线路板的制造方法的工序图。 
图9是表示第1实施例的多层印刷线路板的制造方法的工序图。 
图10是表示第1实施例的多层印刷线路板的制造方法的工序图。 
图11是表示第1实施例的多层印刷线路板的剖视图。 
图12是表示在图11中所示多层印刷线路板上载置了IC芯片的状态的剖视图。 
图13是表示第1实施例的多层印刷线路板的俯视图。 
图14(A)是表示本发明的一实施例的焊锡球搭载装置结构的构成图,图14(B)是表示从箭头B侧观察图14(A)中的焊锡球搭载装置的侧视图。 
图15是表示第2实施例的多层印刷线路板的制造方法的工序图。 
图16是表示第2实施例的多层印刷线路板的剖视图。 
图17(A)是表示在以往技术中的不同直径的焊锡凸块的说明图,图17(B)是表示回流焊后的焊锡凸块的说明图。 
附图标记说明: 
30:电路板;36:通孔;40:填充树脂层;50:层间树脂绝缘层;58:导体电路;60:导通孔;70:阻焊层;71S:小直径开口;71P:大直径开口;77:焊锡球;78S:小直径焊锡凸块;78P:大直径焊锡凸块;100:焊锡球搭载装置;124:搭载筒。 
具体实施方式
第1实施例
焊锡球搭载装置
参照图14对将微小(直径小于200μm)的焊锡球77搭载在多层印刷线路板的连接焊盘上的焊锡球搭载装置进行说明。 
图14(A)是表示本发明的一实施例的焊锡球搭载装置结构的构成图,图14(B)是表示从箭头B侧观察图14(A)中的焊锡球搭载装置的侧视图。 
焊锡球搭载装置100具有XYθ吸引台114、上下移动轴112、球排列用掩模16、搭载筒(筒构件)124、吸引盒126、球去除筒161、吸收盒166、球除去吸引装置168、掩模夹具144、移动轴140、移动轴支承导轨142、校准照相机146、残余量检测传感器118、焊锡球供给装置122;该XYθ吸引台114定位保持多层印刷线路板10,该上下移动轴112使该XYθ吸引台114升降,该球排列用掩模16具有与多层印刷线路板的连接焊盘相对应的开口,该搭载筒(筒构件)124引导焊锡球,该吸引盒126向搭载筒施加负压,该球去除筒161用于回收剩余的焊锡球,该吸收盒166向该球去除筒161施加负压,该球除去吸引装置168保持回收的焊锡球,该掩模夹具144夹持球排列用掩模16,该X方向移动轴140向X方向输送搭载筒124与球除去筒161,该移动轴支承导轨142支持X方向移动轴140,该校准照 相机146用于拍摄多层印刷线路板10,该残余量检测传感器118检测位于搭载筒124下的焊锡球的残余量,该焊锡球供给装置122根据由残余量检测传感器118所检测出的残余量向搭载筒124侧供给焊锡球。 
接着,参照图1~图13对本发明的第1实施例的多层印刷线路板10的结构进行说明。图11是表示该多层印刷线路板10的剖视图,图12是表示在图11中所示多层印刷线路板10上安装IC芯片90、并向子板94载置的状态的图。图13是表示安装IC芯片前的多层印刷线路板10的俯视图。在此,在图11与图12中,是减少了如图13所示的焊锡凸块78P与焊锡凸块78S的数量来予以示意表示。另外,在实际的封装基板中设置数百个焊锡凸块78P与焊锡凸块78S。 
如图11所示,在多层印刷线路板10中,芯基板30的表面上形成有导体电路34。通过通孔36连接芯基板30的正面与背面,在芯基板30上配设有层间树脂绝缘层50、150,该层间树脂绝缘层50上形成有导通孔60与导体电路58,该层间树脂绝缘层150上形成有导通孔160与导体电路158。在该导通孔160与导体电路158的上层形成有阻焊层70。在阻焊层70上形成有大直径(直径D1=105μm)开口71P与小直径(直径D2=80μm)开口71S,在大直径开口71P的焊盘73P上配置电源用、地线用的大直径焊锡凸块78P,在小直径开口71S的焊盘73S上配置信号用的小直径焊锡凸块78S。如后所述,电源用、地线用的焊锡凸块78P与信号用焊锡凸块78S由相同容量的焊锡球构成,以使得它们称为相同体积。另外,将大直径开口焊锡凸块78P的高度H1设定在30μm左右,通过进行平坦化处理,将小直径开口焊锡凸块78S的高度H2设定在与大直径开口焊锡凸块78P高度相同的30μm左右。将电源用、地线用大直径开口焊锡凸块 78P大多配置在多层印刷线路板的靠近中央附近,将信号用小直径开口焊锡凸块78S配置在相对靠外的大直径开口焊锡凸块78P的外周侧,从而使布线距离短。在多层印刷线路板的下表面侧,通过该阻焊层70的开口71形成有焊锡凸块78D。另外,在图11中,将阻焊层的开口形成为露出一部分导体回路158,但也可以使开口形成为只包含导通孔160或者包含导通孔160与导体回路158的一部分。 
如图12所示,将多层印刷线路板10上表面侧的电源用、地线用大直径开口焊锡凸块78P连接在IC芯片90的电源用、地线用电极92P上,将信号用小直径开口焊锡凸块78S连接在IC芯片90的信号用电极92S上。另一方面,将下表面侧的焊锡凸块78D连接在子板94的连接盘96上。 
图13是表示安装IC芯片前的多层印刷线路板的俯视图,如图13所示,在第1实施例的多层印刷线路板10中,将电源用、地线用焊盘73P形成在大直径开口71P上,并将该焊盘73P主要配置在多层印刷线路板10的中心侧(点划线PL内的区域),由此,缩短从IC芯片90到子板94的布线长度,降低电阻值。由此,减小在IC芯片90的瞬时耗电增大时的供电电压下降,防止IC芯片90的误动作。另一方面,在小直径开口71S上形成被配置在点划线PL的外周、用虚线SL表示的区域内的信号用焊盘73S,由此,提高布线密度。 
随着IC芯片的高集成化,要求封装基板的信号线用阻焊层开口进一步小直径化、小间距化。相反,为了可以应对IC芯片的瞬间耗电的增大,又不希望封装基板的电源线、地线用焊锡凸块直径过小。即,使由焊锡合金形成的焊锡凸块直径变小,则电阻值变大,在瞬间耗电增大时产生电压下降,会导致IC芯片误动作。作为对这两个相反要求的对应方法,优选是采用使 信号线用阻焊层开口直径变小、不使电源、地线用焊锡凸块直径变小。 
接着,参照图1~图6,对上面参照图10所述的多层印刷线路板10的制造方法进行说明。 
(1)以覆铜层叠板30A为初始材料(图1(A)),该覆铜层叠板30A为在绝缘性基板30的两面上层压有5~250μm的铜箔32而成的材料,该绝缘性基板30由厚度0.2~0.8mm的玻璃环氧树脂或者BT(双马来酰亚胺三嗪树脂bismaleimidetriazine)树脂形成。首先在该覆铜层叠板上钻孔,穿设通孔33(图1(B)),实施无电解电镀处理及电解电镀处理,形成通孔36的侧壁导体层36b(图1(C))。 
(2)用水清洗形成了通孔36的基板30,并使其干燥后,进行将含有NaOH(10g/l)、NaClO2(40g/l)、Na3PO4(6g/l)的水溶液作为黑化液(氧化液)的黑化处理,及进行将含有NaOH(10g/l)、NaBH4(6g/l)的水溶液作为还原液的还原处理,在通孔36的侧壁导体层36b及表面形成粗糙面36α(图1(D))。 
(3)接着,通过丝网印刷向通孔36填充含有平均粒径为10μm的铜粒子的填充剂37(タツタ电线制的非导电性填孔铜膏、商品名:DD膏),并使其干燥固化(图2(A))。这是通过载置了在通孔部分设置了开口的掩模的基板上,通过用印刷法涂布向通孔填充,并在填充之后使其干燥固化。 
接着,由使用#600的带研磨纸(三共理化学制)的带式磨机研磨除去从通孔36溢出的填充剂37,进而进行抛光研磨,除去由于带式磨机研磨造成的伤痕。使基板30的表面平坦化(参照图2(B))。这样,得到通过粗糙面36α将通孔36的侧壁导体层36b与树脂填充剂37牢固地紧密连接的基板30。 
(4)在上述(3)中平坦化了的基板30的表面上施加钯催化剂(Ato tech制),实施无电解镀铜,由此,形成厚度0.6μm的无电解镀铜膜23(参照图2(C))。 
(5)接着,在以下条件下实施电解镀铜,形成厚度15μm的电解镀铜膜24,形成成为使导体电路34部分加厚及覆盖填充于通孔36的填充剂37的盖电镀层(通孔连接盘)部分(参照图2(D))。 
[电解电镀水溶液] 
硫酸                180g/l 
硫酸铜              80g/l 
添加剂(Ato Tech Japan制,商品名:カパラシドGL) 
                    1ml/l 
[电解电镀条件] 
电流密度            1A/dm2
时间                70分钟 
温度                室温 
(6)在形成了导体电路及成为盖电镀层部分的基板30的两面上张贴市面上出售的感光性干膜,载置掩模,在100mJ/cm2下曝光,用0.8%的碳酸钠进行显影处理,由此,形成厚度为15μm的抗蚀层25(参照图2(E))。 
(7)而且,使用氯化铜作为主要成分的蚀刻液溶解除去没有形成抗蚀层25的部分的电镀膜23、24与铜箔32,进而,用5%KOH剥离除去抗蚀层25,形成独立的导体电路34及覆盖填充剂37的盖电镀层36a((参照图3(A))。 
(8)接着,在导体电路34及覆盖填充剂37的盖电镀层36a的表面形成由Cu-Ni-P合金形成的厚度为2.5μm的粗化层(凹凸层)34β,另外,在该粗化层34β的表面形成厚度为了0.3μm 的Sn层((参照图3(B),但是,图中未示Sn层)。 
(9)在基板的两面上将比基板稍大的层间树脂绝缘层用树脂膜(味之素社制,商品名ABF-45SH)50γ载置在基板上,在压力0.45MPa、温度80℃、压接时间10秒的条件下进行临时压接并裁断后,而且,通过用以下的方法使用真空层压装置贴附而形成了层间树脂绝缘层50((图3(C))。即,在真空度67Pa、压力0.47MPa、温度85℃、压接时间60秒的条件下将层间树脂绝缘层用树脂膜正式压接在基板上,其后,在170℃热固化40分钟。 
(10)接着,用波长为10.4μm的CO2气体激光,在光束直径4.0mm、凹帽头模式、脉冲宽度3~30μ秒、掩模的贯通孔的直径1.0~5.0mm、1~3次射击的条件下,在层间树脂绝缘层50上形成导通孔用开口51((图3(D))。 
(11)将形成了导通孔用开口51的基板浸渍在含有60g/l的高锰酸的80℃的溶液中10分钟,除去存在于层间树脂绝缘层50表面的粒子,由此,在包括导通孔用开口51内壁在内的层间树脂绝缘层50的表面上形成了粗糙面50α(图4(A))。 
(12)接着,将完成上述处理之后的基板浸渍在中和溶液(シプレイ社制),然后用水清洗。 
另外,在粗面化处理(粗化深度3μm)后的该基板的表面施加钯催化剂,由此,在层间树脂绝缘层的表面及导通孔用开口的内壁面附着催化剂核。即,将上述基板浸渍在含有氯化钯(PdCl2)与氯化锡(SnCl2)的催化剂液体中,通过析出钯金属来施加催化剂。 
(13)接着,在上村工业社制的无电解镀铜水溶液(スルカツプPEA)中,浸渍施加了催化剂的基板,在整个粗糙面上形成厚度为0.3~3.0μm的无电解镀铜膜,得到在包括导通孔用 开口51内壁在内的层间树脂绝缘层50的表面形成了无电解镀铜膜52的基板。(图4(B))。 
[无电解电镀条件] 
在34℃的液体温度下持续45分钟 
(14)在形成了无电解镀铜膜52的基板上张贴市面上出售的感光性干膜,载置掩模,在110mJ/cm2的状态下曝光,用0.8%的碳酸钠水溶液进行显影处理,由此,设置厚度为25μm的阻镀层54。接着,用50℃的水对基板进行清洗,对其进行脱脂,再用25℃的水对基板进行清洗,再用硫酸进行清洗后,在以下条件下施行电解电镀,在未形成阻镀层54部形成了厚度为15μm的电解镀铜膜56(图4(C))。 
[电解电镀液] 
硫酸                2.24mol/l 
硫酸铜              0.26mol/l 
添加剂              19.5ml/l 
(Ato Tech Japan制,商品名:カパラシドGL) 
[电解电镀条件] 
电流密度            1A/dm2
时间                70分钟 
温度                22±2℃ 
(15)另外,用5%KOH剥离除去阻镀层54之后,用硫酸与过氧化氢的混合液进行蚀刻处理而溶解除去该阻镀层下的无电解电镀膜,做成独立的导体电路58及导通孔60(图4(D))。 
(16)接着,进行与上述(4)同样的处理,在导体电路58及导通孔60的表面形成了粗糙面58α。下层的导体电路58的厚度为15μm(图5(A))。但是,下层导体电路的厚度也可形成为5~25μm之间。 
(17)重复进行上述(9)~(16)的工序,由此,进一步在上层形成具有导体电路158及导通孔160的层间树脂绝缘层150,得到多层印刷线路板(图5(B))。 
(18)接着,在多层印刷线路板的两面,涂布厚度为20μm的市面上出售的阻焊层70组成物,在70℃下20分钟、70℃下30分钟的条件下进行干燥处理后,将描画了阻焊层开口部的图案的厚度为5mm的光掩模紧密粘贴在阻焊层70上,在1000mJ/cm2的紫外线下曝光,用DMTG溶液进行显影处理,在上表面侧形成大直径(D1=φ105μm)开口71P和小直径(D2=φ80μm)开口71S,在下表面侧形成直径200μm的开口71,在大直径开口71P处形成露出一部分导体电路158而成的大直径焊盘73P、在小直径开口71S处形成露出一部分导体电路158而成的小直径焊盘73S(图5(C))。 
然后,进一步在80℃下1小时、100℃下1小时、120℃下1小时、150℃下3小时的条件下分别进行加热处理,使阻焊层固化,形成具有开口、其厚度为15~25μm的阻焊层。 
(19)接着,将形成了阻焊层70的基板浸渍在含有氯化镍(2.3×10-1mol/l)、次亚磷酸钠(2.8×10-1mol/l)、柠檬酸钠(1.6×10-1mol/l)且pH=4.5的无电解镀镍液中20分钟,在开口部71、71S、71P形成了厚度约为5μm的镀镍层72。另外,在80℃的条件下将基板浸渍在含有氰化金钾(7.6×10-3mol/l)、氯化铵(1.9×10-1mol/l)、柠檬酸钠(1.2×10-1mol/l)、次磷酸钠(1.7×10-1mol/l)的无电解镀金液中7.5分钟,在镀镍层72上形成厚度约为0.03μm的镀金层74(图5(D))。除镍金层以外,也可以形成锡、贵金属层(金、银、钯、铂等)的单层。 
(20)焊锡球的搭载工序 
接着,参照图6~图8对使用上面参照图13所述的焊锡球搭 载装置100向印刷线路板10搭载焊锡球的工序进行说明。 
(I)多层印刷线路板的位置识别与修正 
如图6(A)所示,使用校准照相机146识别多层印刷线路板10的校准标记34M,使用XYθ吸引台114相对于球排列用掩模16修正多层印刷线路板10的位置。即,对球排列用掩模16的开口16a进行位置调整使得其分别与多层印刷线路板10的小直径开口71S对应。 
(II)供给焊锡球 
如图6(B)所示,从焊锡球供给装置122向搭载筒124侧定量供给焊锡球77(直径75μm、Sn63Pb37(日立金属社制))。另外,也可以预先向搭载筒内供给焊锡球。虽然在实施例中焊锡球使用的是Sn/Pb焊锡,但是,也可以使用从Sn与Ag、Cu、In、Bi、Zn等群中选出的无Pb焊锡。 
(III)搭载焊锡球 
如图7(A)所示,在球排列用掩模16的上方定位搭载筒124,使其与该球排列用掩模保持规定间隙(例如,球直径的0.5~4倍),通过从吸引部24b吸引空气,使搭载筒与印刷线路板之间的间隙的焊锡球流速为5m/sec~35m/sec,使焊锡球77聚集到该搭载筒124的开口部124A正下方的球排列用掩模16上。 
其后,如图7(B)及图8(A)所示,通过X方向移动轴140沿X轴向沿水平方向输送搭载筒124,该搭载筒124是与图14(B)及图14(A)中所示的沿多层印刷线路板10的Y轴排列的。由此,随着搭载筒124的移动,使聚集到球排列用掩模16上的焊锡球77移动,使焊锡球77通过球排列用掩模16的开口16a向多层印刷线路板10的小直径开口71S及大直径开口71P落下,而搭载于其上。由此,焊锡球77依次被排列搭载在多层印刷线路板10侧的所有连接焊盘上。 
虽然在此为使搭载筒124移动,但也可取而代之,在固定搭载筒124的状态下,使多层印刷线路板10及球排列用掩模16移动,使聚集到搭载筒124正下方的焊锡球77通过球排列用掩模16的开口16a向多层印刷线路板10的小直径开口71S与大直径开口71P搭载。 
(IV)除去附着焊锡球 
如图8(B)所示,由搭载筒124将剩余的焊锡球77引导到在球排列用掩模16上没有开口16a的位置后,由球去除筒161将剩余的焊锡球吸引除去。 
(21)其后,通过在230℃进行回流焊来熔融上表面的焊锡球77,由大直径开口71P的焊锡球77形成高度较低(H1≈30μm:从阻焊层的表面突出的高度)的大直径开口焊锡凸块78P,由小直径开口71S的焊锡球77形成高度较低(H3≈40μm:从阻焊层的表面突出的高度)的小直径开口焊锡凸块78S,并在下表面形成焊锡凸块78D(图9)。 
(22)而且,如图10所示,通过抵压在相当于大直径开口焊锡凸块部的位置具有开口80A的平板80,使小直径开口71S的高度较高的焊锡凸块78S平坦化,使其变成与大直径开口71P的焊锡凸块78P的高度(H1≈30μm)相同的高度(H2≈30μm)。该平板80也可以加热。 
在第1实施例中,将小直径开口71S主要配置在中心侧的大直径开口71P的外周侧,使用平板80将该小直径开口71S的焊锡凸块平坦化,该平板80具有与形成大直径开口71P的部位相对应的开口80A,从而可以使体积相同的小直径开口71S的焊锡凸块78S与大直径开口71P的焊锡凸块78P的高度近似。 
将IC芯片90载置在多层印刷线路板10,进行回流焊,从而 通过焊锡凸块78P、78S使印刷线路板的连接焊盘与IC芯片90的电极连接。此时,小直径开口71S的焊锡凸块78S与大直径开口71P的焊锡凸块78P的焊锡量相同,因此,在小直径开口71S的焊锡凸块78S不会产生未连接,可以确保IC芯片90与多层印刷线路板10之间的连接可靠性。其后,通过焊锡凸块78D安装到子板94(图12)。 
在第1实施例中,通过将小直径开口71S的高度较高的焊锡凸块78S平坦化,可以以大致相同的高度形成口径不同的小直径开口71S的焊锡凸块78S与大直径开口71P的焊锡凸块78P。因此,在通过焊锡凸块78S与焊锡凸块78P搭载IC芯片90时,可以提高IC芯片的安装成品率,并可以确保IC芯片90与多层印刷线路板10的连接可靠性。 
另外,在第1实施例中,不对电源用及地线用大直径开口71P的焊锡凸块78P进行平坦化而保持半圆形,从而,在进行搭载IC芯片时进行回流焊之际,容易除去空隙,使得在焊锡凸块内不会产生由空气而引起的空隙,难以成为高电阻,因此,有利于电源供给。 
另外,根据本实施例,使筒构件124位于球排列用掩模16的上方,通过从该筒构件124吸引空气来聚集低熔点焊锡球77,通过使筒构件124或者印刷线路及球排列用掩模16在水平方向上相对移动,使聚集到筒构件124正下方的焊锡球77在球排列用掩模16上移动,从而使焊锡球77通过球排列用掩模16的开口16a向多层印刷线路板10的小直径开口71S与大直径开口71P落下,因此,可以确保使微细的焊锡球77搭载在多层印刷线路板10的所有小直径开口71S与大直径开口71P上。另外,以非接触的方式使焊锡球77移动,与使用刮板时不同,可以不会对焊锡球产生损伤地将焊锡球搭载在小直径开口71S与大直径开 口71P上,可以使焊锡凸块78S、78P的体积均匀。另外,因为由吸引力引导焊锡球,所以,可以防止焊锡球的集聚与附着。因为以同等高度成为体积较大的焊锡凸块,因此,焊锡凸块不仅耐冷热冲击性较好,且电阻较低,对电源供给有利。 
在第1实施例中,使小直径焊锡凸块78S的高度与大直径焊锡凸块78P高度一致为30μm。在使凸块高度为10μm以下时,难以产生未连接凸块,使得容易确保焊锡凸块的连接可靠性。 
第2实施例
接着,参照图15、图16对本发明的第2实施例的多层印刷线路板及多层印刷线路板的制造方法进行说明。 
参照图10、图11,如上所述,只对高度较高的小直径焊锡凸块78S进行平坦化。对此,在第2实施例中,如图15所示,将平板80抵压在高度较低的大直径焊锡凸块78P与高度较高的小直径焊锡凸块78S上,使小直径开口71S的高度较高的焊锡凸块78S与大直径开口71P的焊锡凸块78P平坦化,使它们高度相同(H2≈30μm)(图11),该大直径焊锡凸块78P形成在大直径(D1=φ105μm)的开口71P处,该小直径焊锡凸块78S形成在小直径(D2=φ80μm)的开口71S处。另外,焊锡凸块78P与焊锡凸块78S与第1实施例相同,由同一直径的焊锡球形成,体积相同。 
图16示意表示整体被平坦化了的小直径开口71S的焊锡凸块78S与只有顶部被平坦化了的大直径开口71P的焊锡凸块78P。在第2实施例中,具有使所有的焊锡凸块的高度均匀的优点。 

Claims (2)

1.一种印刷线路板的制造方法,该印刷线路板为多层印刷线路板,该印刷线路板是这样形成的:在具有导通正面与背面的通孔导体的芯基板上交替层叠层间树脂绝缘层和导体层,由导通孔导体将各导体层之间连接,在最外层设有阻焊层,将从该阻焊层开口露出的导体层的一部分构成为用于安装电子部件的焊盘,在该焊盘上形成有焊锡凸块,该印刷线路板的制造方法至少具有以下(a)~(d)工序:
(a)形成具有使连接焊盘露出的小直径开口与大直径开口的阻焊层,
(b)使用掩模,在上述阻焊层的小直径开口及大直径开口上搭载低熔点金属球,该掩模具有与上述阻焊层的小直径开口及大直径开口相对应的开口部,
(c)进行回流焊,由上述小直径开口处的低熔点金属球形成高度较高的凸块,由上述大直径开口处的低熔点金属球形成高度较低的凸块,
(d)从上方按压上述小直径开口的高度较高的凸块,使其高度与上述大直径开口的高度较低的凸块的高度相同。
2.根据权利要求1所述的印刷线路板的制造方法,其特征在于,在上述(b)工序中,使具有与上述掩模相对的开口部的筒构件位于该掩模的上方,通过用该筒构件吸引空气,使上述低熔点金属球聚集到该筒构件正下方的上述掩模上,通过使上述筒构件或印刷线路板及掩模在水平方向上相对移动,使聚集到上述筒构件正下方的上述低熔点金属球通过上述掩模的开口部向上述阻焊层的小直径开口及大直径开口落下。
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Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101854771A (zh) * 2005-06-30 2010-10-06 揖斐电株式会社 印刷线路板
KR20080017431A (ko) * 2006-01-27 2008-02-26 이비덴 가부시키가이샤 프린트 배선판 및 프린트 배선판의 제조 방법
JP5154271B2 (ja) * 2008-03-17 2013-02-27 日本特殊陶業株式会社 はんだバンプを有する配線基板及びその製造方法
US8587129B2 (en) * 2009-07-31 2013-11-19 Stats Chippac Ltd. Integrated circuit packaging system with through silicon via base and method of manufacture thereof
US8410376B2 (en) * 2009-08-28 2013-04-02 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
US20110048775A1 (en) * 2009-08-31 2011-03-03 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
JP5428667B2 (ja) * 2009-09-07 2014-02-26 日立化成株式会社 半導体チップ搭載用基板の製造方法
US7867821B1 (en) * 2009-09-18 2011-01-11 Stats Chippac Ltd. Integrated circuit package system with through semiconductor vias and method of manufacture thereof
KR101055473B1 (ko) * 2009-12-15 2011-08-08 삼성전기주식회사 기판 제조용 캐리어 부재 및 이를 이용한 기판의 제조방법
US8604600B2 (en) * 2011-12-30 2013-12-10 Deca Technologies Inc. Fully molded fan-out
KR20110124993A (ko) * 2010-05-12 2011-11-18 삼성전자주식회사 반도체 칩 및 이를 포함하는 반도체 패키지 및 반도체 칩의 제조 방법
KR101708093B1 (ko) * 2011-03-22 2017-02-17 르네사스 일렉트로닉스 가부시키가이샤 반도체 장치
US9236278B2 (en) * 2011-09-23 2016-01-12 Stats Chippac Ltd. Integrated circuit packaging system with a substrate embedded dummy-die paddle and method of manufacture thereof
US8546925B2 (en) * 2011-09-28 2013-10-01 Texas Instruments Incorporated Synchronous buck converter having coplanar array of contact bumps of equal volume
US9368439B2 (en) * 2012-11-05 2016-06-14 Nvidia Corporation Substrate build up layer to achieve both finer design rule and better package coplanarity
US8969191B2 (en) * 2013-07-16 2015-03-03 Taiwan Semiconductor Manufacturing Co., Ltd. Mechanisms for forming package structure
KR102192356B1 (ko) 2013-07-29 2020-12-18 삼성전자주식회사 반도체 패키지
JP6320066B2 (ja) * 2014-02-13 2018-05-09 イビデン株式会社 ボール搭載用マスクおよびボール搭載装置
JP2015231003A (ja) * 2014-06-06 2015-12-21 イビデン株式会社 回路基板および回路基板の製造方法
CN105530768B (zh) * 2014-09-28 2019-02-05 深南电路有限公司 一种电路板的制作方法及电路板
KR102632351B1 (ko) * 2016-02-05 2024-02-02 삼성전기주식회사 인쇄회로기판 및 이를 포함하는 패키지 기판
CN107318228B (zh) * 2017-08-29 2019-09-06 郑州云海信息技术有限公司 一种印制电路板的制造方法及其制造装置
TWI650048B (zh) * 2017-09-19 2019-02-01 南亞電路板股份有限公司 印刷電路板結構及其形成方法
CN108235591B (zh) * 2018-01-08 2020-08-18 昆山首源电子科技有限公司 5g通讯高频信号板镀金蚀刻工艺
CN110534451A (zh) * 2018-05-25 2019-12-03 唐虞企业股份有限公司 一种导电端子置件设备及其导电端子置件方法
JP7257273B2 (ja) * 2019-06-26 2023-04-13 イビデン株式会社 プリント配線板およびその製造方法
CN113709972A (zh) * 2021-09-27 2021-11-26 合肥移瑞通信技术有限公司 一种电路板及其制造方法、封装件

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1156949A (zh) * 1995-11-16 1997-08-13 松下电器产业株式会社 印刷电路板及其安装体
US5660321A (en) * 1996-03-29 1997-08-26 Intel Corporation Method for controlling solder bump height and volume for substrates containing both pad-on and pad-off via contacts
JP2001102738A (ja) * 1999-09-30 2001-04-13 Matsushita Electric Ind Co Ltd 電子部品実装半田付け方法
CN101356642B (zh) * 2006-01-27 2010-09-01 揖斐电株式会社 印刷线路板及其印刷线路板的制造方法

Family Cites Families (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2974436B2 (ja) 1991-02-26 1999-11-10 シチズン時計株式会社 ハンダバンプの形成方法
JP3152834B2 (ja) * 1993-06-24 2001-04-03 株式会社東芝 電子回路装置
JP3226703B2 (ja) * 1994-03-18 2001-11-05 株式会社日立製作所 半導体装置及びその製法
JP3138159B2 (ja) * 1994-11-22 2001-02-26 シャープ株式会社 半導体装置、半導体装置実装体、及び半導体装置の交換方法
JP2842361B2 (ja) * 1996-02-28 1999-01-06 日本電気株式会社 半導体装置
JPH1013007A (ja) * 1996-03-29 1998-01-16 Ngk Spark Plug Co Ltd 半田バンプを有する配線基板及びその製造方法及び平坦化治具
JP3401391B2 (ja) * 1996-04-16 2003-04-28 日本特殊陶業株式会社 半田バンプを有する基板の製造方法
JP2861965B2 (ja) * 1996-09-20 1999-02-24 日本電気株式会社 突起電極の形成方法
EP1796446B1 (en) * 1996-11-20 2011-05-11 Ibiden Co., Ltd. Printed circuit board
TW392315B (en) * 1996-12-03 2000-06-01 Nippon Electric Co Boards mounting with chips, mounting structure of chips, and manufacturing method for boards mounting with chips
KR100244580B1 (ko) * 1997-06-24 2000-02-15 윤종용 금속 범프를 갖는 회로 기판의 제조 방법 및 그를 이용한 반도체 칩 패키지의 제조 방법
US6028011A (en) * 1997-10-13 2000-02-22 Matsushita Electric Industrial Co., Ltd. Method of forming electric pad of semiconductor device and method of forming solder bump
JPH11145176A (ja) * 1997-11-11 1999-05-28 Fujitsu Ltd ハンダバンプの形成方法及び予備ハンダの形成方法
JPH11204687A (ja) * 1998-01-19 1999-07-30 Juki Corp バンプ形成方法及びバンプ形成装置
US6137164A (en) * 1998-03-16 2000-10-24 Texas Instruments Incorporated Thin stacked integrated circuit device
US6100112A (en) * 1998-05-28 2000-08-08 The Furukawa Electric Co., Ltd. Method of manufacturing a tape carrier with bump
US6461953B1 (en) * 1998-08-10 2002-10-08 Fujitsu Limited Solder bump forming method, electronic component mounting method, and electronic component mounting structure
US6268114B1 (en) * 1998-09-18 2001-07-31 Taiwan Semiconductor Manufacturing Company, Ltd Method for forming fine-pitched solder bumps
US6746896B1 (en) * 1999-08-28 2004-06-08 Georgia Tech Research Corp. Process and material for low-cost flip-chip solder interconnect structures
JP2001203318A (ja) * 1999-12-17 2001-07-27 Texas Instr Inc <Ti> 複数のフリップチップを備えた半導体アセンブリ
JP2001267731A (ja) 2000-01-13 2001-09-28 Hitachi Ltd バンプ付き電子部品の製造方法および電子部品の製造方法
JP2001210749A (ja) * 2000-01-26 2001-08-03 Kyocera Corp バンプ電極付き配線基板およびその製造方法
JP2001319992A (ja) * 2000-02-28 2001-11-16 Shinko Electric Ind Co Ltd 配線基板、半導体装置及びそれらの製造方法
JP2002043467A (ja) * 2000-07-31 2002-02-08 Hitachi Chem Co Ltd 半導体パッケージ用基板とその製造方法およびその基板を用いた半導体パッケージ並びに半導体パッケージの製造方法
JP2002050716A (ja) * 2000-08-02 2002-02-15 Dainippon Printing Co Ltd 半導体装置及びその作製方法
US6459150B1 (en) * 2000-08-17 2002-10-01 Industrial Technology Research Institute Electronic substrate having an aperture position through a substrate, conductive pads, and an insulating layer
CN1156204C (zh) * 2000-09-04 2004-06-30 华泰电子股份有限公司 积体电路基板柱状凸块成型方法
JP4130526B2 (ja) * 2000-11-10 2008-08-06 株式会社日立製作所 バンプ形成方法およびその装置
US6596618B1 (en) * 2000-12-08 2003-07-22 Altera Corporation Increased solder-bump height for improved flip-chip bonding and reliability
US6910812B2 (en) * 2001-05-15 2005-06-28 Peregrine Semiconductor Corporation Small-scale optoelectronic package
JP2003188508A (ja) * 2001-12-18 2003-07-04 Toshiba Corp プリント配線板、面実装形回路部品および回路モジュール
US6940176B2 (en) * 2002-05-21 2005-09-06 United Microelectronics Corp. Solder pads for improving reliability of a package
JP2004055628A (ja) * 2002-07-17 2004-02-19 Dainippon Printing Co Ltd ウエハレベルの半導体装置及びその作製方法
JP4181510B2 (ja) * 2003-02-28 2008-11-19 日本特殊陶業株式会社 樹脂製配線基板
JP4094982B2 (ja) * 2003-04-15 2008-06-04 ハリマ化成株式会社 はんだ析出方法およびはんだバンプ形成方法
JP4536430B2 (ja) * 2004-06-10 2010-09-01 イビデン株式会社 フレックスリジッド配線板
EP1776004A4 (en) * 2004-08-04 2009-09-02 Ibiden Co Ltd METHOD AND DEVICE FOR FASTENING A SOLDERING BALL
US7405474B1 (en) * 2004-10-12 2008-07-29 Cypress Semiconductor Corporation Low cost thermally enhanced semiconductor package
US7215026B2 (en) * 2005-04-14 2007-05-08 Samsung Electonics Co., Ltd Semiconductor module and method of forming a semiconductor module
KR100702969B1 (ko) * 2005-04-19 2007-04-03 삼성전자주식회사 더미 솔더 볼을 갖는 bga형 반도체 칩 패키지의 기판 실장 구조
KR20100025597A (ko) 2005-05-23 2010-03-09 이비덴 가부시키가이샤 프린트 배선판
JP2006344824A (ja) * 2005-06-09 2006-12-21 Nec Electronics Corp 半導体装置および半導体装置の製造方法
CN101868120A (zh) 2005-06-30 2010-10-20 揖斐电株式会社 印刷线路板及其制造方法
CN101854771A (zh) * 2005-06-30 2010-10-06 揖斐电株式会社 印刷线路板
US7566650B2 (en) * 2005-09-23 2009-07-28 Stats Chippac Ltd. Integrated circuit solder bumping system
DE102005055280B3 (de) * 2005-11-17 2007-04-12 Infineon Technologies Ag Verbindungselement zwischen Halbleiterchip und Schaltungsträger sowie Verfahren zur Herstellung und Verwendung des Verbindungselements
US20070145104A1 (en) * 2005-12-28 2007-06-28 Mengzhi Pang System and method for advanced solder bumping using a disposable mask
US20070155154A1 (en) * 2005-12-29 2007-07-05 Mengzhi Pang System and method for solder bumping using a disposable mask and a barrier layer
US7517788B2 (en) * 2005-12-29 2009-04-14 Intel Corporation System, apparatus, and method for advanced solder bumping
DE102006001767B4 (de) * 2006-01-12 2009-04-30 Infineon Technologies Ag Halbleitermodul mit Halbleiterchips und Verfahren zur Herstellung desselben
US7472473B2 (en) * 2006-04-26 2009-01-06 Ibiden Co., Ltd. Solder ball loading apparatus
US7823762B2 (en) * 2006-09-28 2010-11-02 Ibiden Co., Ltd. Manufacturing method and manufacturing apparatus of printed wiring board

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1156949A (zh) * 1995-11-16 1997-08-13 松下电器产业株式会社 印刷电路板及其安装体
US5660321A (en) * 1996-03-29 1997-08-26 Intel Corporation Method for controlling solder bump height and volume for substrates containing both pad-on and pad-off via contacts
JP2001102738A (ja) * 1999-09-30 2001-04-13 Matsushita Electric Ind Co Ltd 電子部品実装半田付け方法
CN101356642B (zh) * 2006-01-27 2010-09-01 揖斐电株式会社 印刷线路板及其印刷线路板的制造方法

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