CN101331812B - 印刷线路板的制造方法 - Google Patents

印刷线路板的制造方法 Download PDF

Info

Publication number
CN101331812B
CN101331812B CN2007800007403A CN200780000740A CN101331812B CN 101331812 B CN101331812 B CN 101331812B CN 2007800007403 A CN2007800007403 A CN 2007800007403A CN 200780000740 A CN200780000740 A CN 200780000740A CN 101331812 B CN101331812 B CN 101331812B
Authority
CN
China
Prior art keywords
solder
mask
opening
ball
connection pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2007800007403A
Other languages
English (en)
Other versions
CN101331812A (zh
Inventor
丹野克彦
川村洋一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Publication of CN101331812A publication Critical patent/CN101331812A/zh
Application granted granted Critical
Publication of CN101331812B publication Critical patent/CN101331812B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L24/742—Apparatus for manufacturing bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/8121—Applying energy for connecting using a reflow oven
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01061—Promethium [Pm]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01084—Polonium [Po]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0191—Dielectric layers wherein the thickness of the dielectric plays an important role
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/041—Solder preforms in the shape of solder balls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/043—Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

本发明提供一种印刷线路板的制造方法，该制造方法可以可靠地在小直径连接焊盘上形成高度较高的凸块，该小直径连接焊盘设置在阻焊层的开口处。在该制造方法中，通过回流焊熔融焊锡球(77)，由搭载在上表面的开口(71)的焊锡球(77)形成高度较高的焊锡凸块(78U)。此时，通过调整阻焊层(70)的厚度，使搭载在开口(71)的焊锡球(77)与连接焊盘(158P)的距离接近，由此，可以确保在对焊锡球(77)进行回流焊时可靠地取得焊锡凸块(78U)与连接焊盘(158P)的连接。

Description

印刷线路板的制造方法 
技术领域
本发明涉及印刷线路板的制造方法，特别是，涉及适用于安装IC芯片用的封装基板的印刷线路板的制造方法。 
背景技术
为了电连接封装基板与IC芯片，而采用了焊锡凸块。由以下工序形成焊锡凸块。 
(1)在形成在封装基板上的连接焊盘上印刷焊剂。 
(2)在印刷了焊剂的连接焊盘上搭载焊锡球。 
(3)进行回流焊由焊锡球形成焊锡凸块。 
在封装基板上形成了焊锡凸块后，在焊锡凸块上载置IC芯片，通过回流焊使焊锡凸块与IC芯片的焊盘(端子)相连接，由此将IC芯片安装在封装基板上。在将上述焊锡球搭载在连接焊盘上的过程中，使用例如专利文献1中公开的并用球排列用掩模与刮板的印刷技术。 
专利文献1：日本特开2001-267731号 
但是，小直径的焊锡球比砂粒小，使用在专利文献1中的并用球排列用掩模与刮板的方法，用刮板使焊锡球变形，出现焊锡凸块的高度参差不齐，品质降低。即，当焊锡球直径小时，则相对于表面积的重量比变小，产生由分子间引力所引起的焊锡球的吸附现象。在现有技术中，由于使刮板接触易于聚集的焊锡球来输送该焊锡球，因此会损伤焊锡球而使其产生局部欠缺。当焊锡球缺少一部分时，使得在各连接焊盘上焊锡凸块的体积变得不同，因此如上述那样产生焊锡凸块的高度参差不齐。 
另外，一方面，随着IC芯片的高集成化，在封装用的印刷线路板中，搭载焊锡凸块的连接焊盘要求小直径化。相反，连接在连接焊盘上的焊锡凸块要求有一定高度。即，这是因为，IC芯片与由树脂形成的印刷线路板的热膨胀系数不同，若焊锡凸块的高度较高，用该焊锡凸块可以容易吸收由于IC芯片与印刷线路板之间的热膨胀系数差而产生的应力。
因此，如图15(A)所示，为了使连接焊盘158P为小直径而在阻焊层70设置开口71、形成具有高度的焊锡凸块，从而如图15(B)所示，在小直径的连接焊盘158P上搭载相对较大的焊锡球77，进行回流焊，如图15(C)所示，形成了焊锡凸块。由其结果可知，除了产生与连接焊盘158P取得连接的焊锡凸块78U之外，也产生了从连接焊盘158P浮起而没有取得与连接焊盘158P连接的焊锡凸块78F。 
发明内容
本发明的目的之一是提供一种印刷线路板的制造方法，该制造方法可以可靠地在小直径连接焊盘(从阻焊层露出的导体电路)上形成高度较高的凸块，该小直径连接焊盘设置在阻焊层的开口处。 
为了达成上述目的，技术方案1的具有凸块的印刷线路板的制造方法的技术特征为至少具有以下(a)～(c)工序： 
(a)形成使连接焊盘的一部分露出并具有从开口上端到露出的上述连接焊盘表面的深度为3～18μm的开口的阻焊层， 
(b)在该开口上搭载低熔点金属球， 
(c)进行回流焊，在上述连接焊盘上由低熔点金属球形成凸块。 
在技术方案1中，在阻焊层的小直径开口上搭载相对较大的低熔点金属球。进行回流焊而在阻焊层的小直径开口由低熔点金属球形成高度较高的凸块。此时，通过调整阻焊层的厚度，使从开口上端到连接焊盘表面的深度为3～18μm，使搭载在开口的低熔点金属球与连接焊盘之间距离接近，因此，在对低熔点金属球进行回流焊时，可以确保取得焊锡凸块与连接焊盘的连接。在此，若深度超过18μm，则在搭载低熔点金属球时，低熔点金属球在阻焊层开口上端面容易卡住，有时不能搭载到开口。而且，在对低熔点金属球进行回流焊时，由于低熔点金属球与连接焊盘远离，有时会发生不能取得焊锡凸块与连接焊盘之间的连接。另一方面，若深度不足3μm，作为堤坝的能力下降，在对低熔点金属球进行回流焊时，有时低熔点金属流出，与相邻的连接焊盘的低熔点金属球接触而发生短路。另外，在输送等中，焊锡球容易越过阻焊层，因此有时焊锡球没有搭载在连接焊盘上。 
在技术方案2中，在将低熔点金属球搭载在开口的状态下，调整阻焊层的厚度而使低熔点金属球与连接焊盘接触。在进行回流焊时，使搭载在开口的低熔点金属球与连接焊盘接触，因此可以确保取得焊锡凸块与与连接焊盘的连接。 
在技术文案3中，使用具有与阻焊层的开口相对应的开口部的掩模，使筒构件位于该掩模的上方，通过从该筒构件的开口部吸引空气，使低熔点金属球聚集，通过使筒构件或者印刷线路及掩模在水平方向上相对移动，使聚集到筒构件正下方的低熔点金属球移动，通过掩模的开口部向阻焊层的开口落下，因此，可以将微小的低熔点金属球确实地搭载在阻焊层的所有开口上。另外，由于以非接触方式移动低熔点金属球，与使用刮板时不同，因此可以不对低熔点金属球产生损伤地将低熔点金属球搭载在开口，可以使凸块的高度均匀。另外，即使是在积层多层线路板那样的表面起伏较多的印刷线路板上也可以将 低熔点金属球适当地搭载在开口上。 
附图说明
图1是表示本发明的第1实施例的多层印刷线路板的制造方法的工序图。 
图2是表示第1实施例的多层印刷线路板的制造方法的工序图。 
图3是表示第1实施例的多层印刷线路板的制造方法的工序图。 
图4是表示第1实施例的多层印刷线路板的制造方法的工序图。 
图5是表示第1实施例的多层印刷线路板的制造方法的工序图。 
图6是表示第1实施例的多层印刷线路板的制造方法的工序图。 
图7是表示第1实施例的多层印刷线路板的制造方法的工序图。 
图8是表示第1实施例的多层印刷线路板的制造方法的工序图。 
图9是表示第1实施例的多层印刷线路板的制造方法的工序图。 
图10是表示第1实施例的多层印刷线路板的剖视图。 
图11是表示在图10中所示多层印刷线路板上载置了IC芯片的状态的剖视图。 
图12(A)是表示本发明的实施例的焊锡球搭载装置的结构的构成图，图12(B)是表示从箭头B侧观察图12(A)中的焊锡球搭载装置的侧视图。 
图13是表示在开口搭载了焊锡球的状态的说明图。 
图14是表示焊锡球的搭载成功率的试验结果的图表。 
图15(A)是表示在现有技术中的形成阻焊层的说明图，图15(B)是表示搭载焊锡球的说明图，图15(C)是表示回流焊后的焊锡凸块的说明图。 
附图标记说明： 
30：基板；36：通孔；40：填充树脂层；50：层间树脂绝缘层；58：导体电路；60：层间导通孔；70：阻焊层；71：开口；77：焊锡球；78U：焊锡凸块；100：焊锡球搭载装置；124：搭载筒(筒构件)；D2：从开口上端到连接焊盘表面的深度。 
具体实施方式
第1实施例
焊锡球搭载装置
参照图12对将微小(直径不足200μm)的焊锡球77搭载在多层印刷线路板的连接焊盘上的焊锡球搭载装置进行说明。 
图12(A)是表示本发明的一实施例的焊锡球搭载装置的结构的构成图，图12(B)是表示从箭头B侧观察图12(A)中的焊锡球搭载装置的侧视图。 
焊锡球搭载装置100具有XYθ吸引台114、上下移动轴112、球排列用掩模16、搭载筒(筒构件)124、吸引盒126、球去除筒161、吸收盒166、球除去吸引装置168、掩模夹具144、移动轴140、移动轴支承导轨142、校准照相机146、余量检测传感器118、焊锡球供给装置122；该XYθ吸引台114定位保持多层印刷线路板10，该上下移动轴112使该XYθ吸引台114升降，该球排列用掩模16具有与多层印刷线路板的连接焊盘相对 应的开口，该搭载筒(筒构件)124引导焊锡球，该吸引盒126向搭载筒施加负压，该球去除筒161用于回收剩余的焊锡球，该吸收盒166向该球去除筒161施加负压，该球除去吸引装置168保持回收的焊锡球，该掩模夹具144夹持球排列用掩模16，该X方向移动轴140向X方向输送搭载筒124与球除去筒161，该移动轴支承导轨142支持X方向移动轴140，该校准照相机146用于拍摄多层印刷线路板10，该余量检测传感器118检测位于搭载筒124下的焊锡球的余量，该焊锡球供给装置122根据由余量检测传感器118所检测出的余量向搭载筒124侧供给焊锡球。 
接着，参照图1～图11对本发明的第1实施例的多层印刷线路板10的结构进行说明。图10是表示该多层印刷线路板10的剖视图，图11是表示在图10中所示的多层印刷线路板10上安装IC芯片90、载置在子板94上的状态的图。如图10所示，在多层印刷线路板10中，芯基板30的表面上形成有导体电路34。通过通孔36连接芯基板30的表面与背面，在芯基板30上配设有层间树脂绝缘层50、150，该层间树脂绝缘层50上形成有层间导通孔60与导体电路58，该层间树脂绝缘层150上形成有层间导通孔160与导体电路158。在该层间导通孔160与导体电路158的上面形成有阻焊层70。在上面侧阻焊层70形成有直径W1＝60μm的开口71，设置有焊锡凸块78U。将焊锡凸块78U的高度H1(从阻焊层表面突出的高度)设定为30μm左右。在多层印刷线路板的下面侧，通过阻焊层70的开口71形成有焊锡凸块78D。另外，在图10中，将阻焊层的开口形成为露出导体电路158的一部分，也可以使开口形成为只包含导通孔160或者包含层间导通孔160与导体电路158的一部分。 
如图11所示，将多层印刷线路板10的上表面侧的焊锡凸块78U连接在IC芯片90的电极焊盘92。另一方面，将下表面侧的焊锡凸块78D连接在子板94的焊盘96。
接着，参照图1～图7，对上面参照图10所述的多层印刷线路板10的制造方法进行说明。 
(1)以覆铜层叠板30A为初始材料(图1(A))，该覆铜层叠板30A为在绝缘性基板30的两面上层压有5～250μm的铜箔32而成的材料，该绝缘性基板30由厚度0.2～0.8mm的玻璃环氧树脂或者BT(双马来酰亚胺三嗪树脂bismaleimidetriazine)树脂形成。首先在该覆铜层叠板上钻孔，穿设通孔33(图1(B))，实施无电解电镀处理及电解电镀处理，形成通孔36的侧壁导体层36b(图1(C))。 
(2)用水清洗形成了通孔36的基板30，并使其干燥后，进行将含有NaOH(10g/l)、NaClO2(40g/l)、Na3PO4(6g/1)的水溶液作为黑化液(氧化液)黑化处理，及进行将含有NaOH(10g/l)、Na3BH4(6g/l)的水溶液作为还原液的还原处理，在通孔36的侧壁导体层36b及表面形成粗糙面36α(图1(D))。 
(3)接着，通过丝网印刷向通孔36填充含有平均粒径为10μm的铜粒子的填充剂37(タッタ电线制的非导电性填孔铜膏、商品名：DD膏)，并使其干燥固化(图2(A))。这是通过载置了在通孔部分设置了开口的掩模的基板上，通过用印刷法涂布向通孔填充，并在填充之后使其干燥固化。 
接着，由使用#600的带研磨纸(三共理化学制)的带式磨机研磨除去从通孔36溢出的填充剂37，进而进行抛光研磨，除去由于带式磨机研磨造成的伤痕。使基板30的表面平坦化(参照图2(B))。这样，得到通过粗糙面36α将通孔36的侧壁导体层36b与树脂填充剂37牢固地紧密连接的基板30。 
(4)在上述(3)中平坦化了的基板30的表面上施加钯催化剂(Ato tech制)，实施无电解镀铜，由此，形成厚度0.6μm的无电解镀铜膜23(参照图2(C))。 
(5)接着，在以下条件下实施电解镀铜，形成厚度15μm的电解镀铜膜24，形成成为使导体电路34部分加厚及覆盖填充于通孔36的填充剂37的盖电镀层(通孔连接盘)部分(参照图2(D))。 
[电解电镀水溶液] 
硫酸              180g/l 
硫酸铜            80g/l 
添加剂(Ato Tech Japan制，  商品名：カパラシド GL) 
                  1ml/l 
[电解电镀条件] 
电流密度          1A/dm2
时间              70分钟 
温度              室温 
(6)在形成了成为导体电路及盖电镀层部分的基板30的两面上张贴市面上出售的感光性干膜，载置掩模，在100mJ/cm2 下曝光，用0.8％的碳酸钠进行显影处理，由此，形成厚度为15μm的抗蚀层25(参照图2(E))。 
(7)而且，使用氯化铜作为主要成分的蚀刻液溶解除去没有形成抗蚀层25的部分的电镀膜23、24与铜箔32，进而，用5％KOH剥离除去抗蚀层25，形成独立的导体电路34及覆盖填充剂37的盖电镀层36a((参照图3(A))。 
(8)接着，在导体电路34及覆盖填充剂37的盖电镀层36a的表面形成由Cu-Ni-P合金形成的厚度为2.5μm的粗化层(凹凸层)34β，另外，在该粗化层34β的表面形成厚度为了0.3μm的Sn层((参照图3(B)，但是，图中未示Sn层)。 
(9)在基板的两面上将比基板稍大的层间树脂绝缘层用树脂膜(味ぇ素社制，商品名ABF-45SH)50γ载置在基板上，在压力0.45MPa、温度80℃、压接时间10秒的条件下进行临时压接并裁断后，而且，通过用以下的方法使用真空层叠装置贴附而形成了层间树脂绝缘层50((图3(C))。即，在真空度67Pa、压力0.47MPa、温度85℃、压接时间60秒的条件下将层间树脂绝缘层用树脂膜正式压接在基板上，其后，在170℃热固化40分钟。 
(10)接着，用波长为10.4μm的CO2气体激光，在光束直径4.0mm、凹帽头模式、脉冲宽度3～30μ秒、掩模的贯通孔的直径1.0～5.0mm、1～3次射击的条件下，在层间树脂绝缘层50上形成层间导通孔用开口51((图3(D))。 
(11)将形成了层间导通孔用开口51的基板浸渍在含有60g/l的高锰酸的80℃的溶液中10分钟，除去存在于层间树脂绝缘层50的表面的粒子，由此，在包括层间导通孔用开口51内壁的层间树脂绝缘层50的表面上形成了粗糙面50α(图4(A))。 
(12)接着，将上述处理完成之后的基板浸渍在中和溶液(シプレィ社制)，然后用水清洗。 
另外，在粗面化处理(粗化深度3μm)后的该基板的表面施加钯催化剂，由此，在层间树脂绝缘层的表面及层间导通孔用开口的内壁面附着催化剂核。即，将上述基板浸渍在含有氯化钯(PdCl2)与氯化锡(SnCl2)的催化剂液体中，通过析出钯金属来施加催化剂。 
[0067] (13)接着，在上村工业社制的无电解镀铜水溶液(スルカップPEA)中，浸渍施加了催化剂的基板，在整个粗糙面上形成厚度为0.3～3.0μm的无电解镀铜膜，得到在包括层间导通孔用开口51内壁的层间树脂绝缘层50的表面形成了无电解镀 铜膜52的基板。(图4(B))。 
[无电解电镀条件] 
在34℃的液体温度下持续45分钟 
(14)在形成了无电解镀铜膜52的基板上张贴市面上出售的感光性干膜，载置掩模，在110mJ/cm2的状态下曝光，用0.8％的碳酸钠水溶液进行显影处理，由此，设置厚度为25μm的阻镀层54。接着，用50℃的水对基板进行清洗，对其进行脱脂，再用25℃的水对基板进行清洗，再用硫酸进行清洗后，在以下条件下施行电解电镀，在未形成阻镀层54部形成了厚度为15μm的电解镀铜膜56(图4(C))。 
[电解电镀液] 
硫酸              2.24mol/l 
硫酸铜            0.26mol/l 
添加剂(Ato Tech Japan制，商品名：カパラシド GL) 
                  19.5ml/l 
[电解电镀条件] 
电流密度          1A/dm2
时间              70分钟 
温度              22±2℃ 
(15)另外，用5％KOH剥离除去阻镀层54之后，用硫酸与过氧化氢的混合液进行蚀刻处理而溶解除去该阻镀层下的无电解电镀膜，做成独立的导体电路58及层间导通孔60(图4(D))。 
(16)接着，进行与上述(4)同样的处理，在导体电路58及层间导通孔60的表面形成了粗糙面58α。下层的导体电路58的厚度为15μm(图5(A))。但是，下层导体电路的厚度也可形成为5～25μm之间。 
(17)重复进行上述(9)～(16)的工序，由此，进一步在上层形成具有厚度为15μm的导体电路158及层间导通孔160的层间树脂绝缘层150，得到多层印刷线路板(图5(B))。 
(18)接着，在多层印刷线路板的两面，涂布厚度为10～40μm(参照图13的D4)的市面上出售的阻焊层70组成物，在70℃下20分钟、70℃下30分钟的条件下进行干燥处理后，将描画了阻焊层开口部的图案的厚度为5mm的光致掩膜紧密粘贴在阻焊层70上，在1000mJ/cm2的紫外线下曝光，在DMTG溶液中进行显影处理，在上面侧形成直径W1＝60μm的开口71，在下面侧形成直径200μm的开口71(图5(C))。 
然后，进一步在80℃下1小时、100℃下1小时、120℃下1小时、150℃下3小时的条件下分别进行加热处理，使阻焊层固化，形成具有开口71、其厚度为30μm的阻焊剂图案。 
接着，将形成了阻焊层70的基板浸渍在含有氯化镍(2.3×10-1mol/l)、次亚磷酸钠(2.8×10-1mol/l)、柠檬酸钠(1.6×10-1mol/l)且pH＝4.5的无电解镀镍液中20分钟，在开口部71形成厚度约为5μm的镀镍层72。另外，在80℃的条件下将基板浸渍在含有氰化金钾(7.6×10-3mol/l)、氯化铵(1.9×10-1mol/l)、柠檬酸钠(1.2×10-1mol/l)、次磷酸钠(1.7×10-1mol/l)的无电解镀金液中7.5分钟，在镀镍层72上形成厚度约为0.03μm的镀金层74(图6)。除镍金层以外，也可以形成锡、贵金属层(金、银、钯、铂等)的单层。在该工序中，在从开口71露出的导体电路158上设置镀镍层72与镀金层74而形成连接焊盘158P。在此，将如上述那样将阻焊层70的厚度调整到30μm，在厚度为15μm的导体电路158上设置厚度约为5μm的镀镍层72与厚度约为0.03μm的镀金层74，从而将从开口71的上端到连接焊盘158P的表面(镀金层74的表面)的深度 (D2)设定为10μm。 
(20)焊锡球的搭载工序 
接着，参照图7～图9对使用上面参照图12所述的焊锡球搭载装置100向印刷线路板10搭载焊锡球的工序进行说明。 
(I)多层印刷线路板的位置识别与修正 
如图7(A)所示，使用校准照相机146识别多层印刷线路板10的校准标记34M，使用XYθ吸引台114相对于球排列用掩模16修正多层印刷线路板10的位置。即，对球排列用掩模16的开口16a进行位置调整使得其分别与多层印刷线路板10的上表面开口71对应。 
(II)供给焊锡球 
如图7(B)所示，从焊锡球供给装置122向搭载筒124侧定量供给焊锡球77(直径75μm、Sn63Pb37(日立金属社制)。另外，也可以预先向搭载筒内供给焊锡球。虽然在实施例中焊锡球使用的是Sn/Pb焊锡，但是，也可以使用从Sn与Ag、Cu、In、Bi、Zn等群中选出的无Pb焊锡。 
(III)搭载焊锡球 
如图8(A)所示，在球排列用掩模16的上方定位搭载筒124，使其与该球排列用掩模保持规定间隙(例如，球直径的0.5～4倍)，通过从吸引部24b吸引空气，使搭载筒与印刷线路板之间的间隙的焊锡球流速为5m/sec～35m/sec，使焊锡球77聚集到该搭载筒124的开口部124A正下方的球排列用掩模16上。 
其后，通过X方向移动轴140沿X轴向沿水平方向输送搭载筒124，该搭载筒是如图8(B)及图9(A)与图12(B)及图12(A)中所示的沿多层印刷线路板10的Y轴排列的。由此，随着搭载筒124的移动使聚集到球排列用掩模16上的焊锡球77移动，使焊锡球77通过球排列用掩模16的开口16a向多层印刷 线路板10的上表面开口71落下，而搭载于其上。由此，焊锡球77依次被排列搭载在多层印刷线路板10侧的所有连接焊盘上。 
虽然在此为移动搭载筒124，但也可以替代它，在固定搭载筒124的状态下，使多层印刷线路板10及球排列用掩模16移动，使聚集到搭载筒124正下方的焊锡球77通过球排列用掩模16的开口16a向多层印刷线路板10的开口71搭载。 
(IV)除去附着焊锡球 
如图9(B)所示，由搭载筒124将剩余的焊锡球77引导到球排列用掩模16上没有开口16a的位置后，由球除去筒161将剩余的焊锡球吸引除去。 
(21)其后，通过在230℃进行回流焊而熔融上表面的焊锡球77，由搭载在上表面开口71的焊锡球77形成高度约30μm(H1)的焊锡凸块78U(图9)。此时，通过调整阻焊层70的厚度，使被搭载在开口71的焊锡球77与连接焊盘158P的距离接近，因此，在对焊锡球77进行回流焊时，容易取得焊锡凸块78U与连接焊盘158P的连接。特别是在将焊锡球77搭载在开口71的状态下，调整阻焊层70的厚度，使焊锡球77与连接焊盘158P接触，由此，可以确保取得焊锡凸块78U与连接焊盘158P的连接。另外，在下表面形成焊锡凸块78D。 
(22)而且，通过将IC芯片90载置在多层印刷线路板10上并进行回流焊，通过焊锡凸块78U连接印刷线路板的连接焊盘与IC芯片90的电极92。其后，通过焊锡凸块78D安装到子板94上(图11)。 
另外，根据本实施例，使搭载筒124位于球排列用掩模16的上方，通过从该搭载筒124吸引空气，来聚集焊锡球77，使搭载筒124或者印刷线路板及球排列用掩模16在水平方向上相对移动。从而使聚集到搭载筒正下方的焊锡球77在球排列用掩 模16上移动，通过球排列用掩模16的开口16a向多层印刷线路板10的开口71落下。此时，通过使从开口71上端到连接焊盘158P的深度变浅，焊锡球77难以卡在开口71上端面，因此，可以将微小的焊锡球77可靠地搭载在多层印刷线路板10的全部小径开口71。另外，因为在非接触的状态下使焊锡球77移动，与使用刮板时不同，可以不对焊锡球产生损伤地将焊锡球搭载在小直径开口71，可以使焊锡凸块78的高度均匀。而且，因为由吸引力引导焊锡球，所以，可以防止焊锡球的凝聚与附着。 
优选是由阻焊层70的厚度D4调整从开口71上端到连接焊盘158P的深度D2，使焊锡球77与连接焊盘158P接触。参照图13说明它们的关系。在此，设定开口直径W1(半径W1/2)、焊锡球的半径为R，从开口71上端到焊锡球77下端的距离X用下式表示。 
X = R - ( ( R 2 - ( W 1 / 2 ) 2 )
因此，优选通过调整阻焊层70的厚度D4，来使从开口上端到连接焊盘表面的深度D2成为距离X以下。 
而且，为了缩小焊锡球77与连接焊盘158之间存在的空隙部V，优选是距离X较小。这是因为，通过回流焊将焊锡球77做成焊锡凸块时，必须将该空隙部V的空气挤出到焊锡凸块外。因为如果没有将该空隙部V的空气挤出到焊锡凸块之外，则连接焊盘与焊锡凸块之间的紧密附着性差，会在焊锡凸块内产生空穴。有时不能在连接焊盘上形成焊锡凸块。空隙部V越大，这样的不良情况越容易发生。 
在此，通过改变阻焊层厚度、开口直径、焊锡球直径对使用上面参照图12所述的焊锡球搭载装置在2500个C4连接焊盘上搭载焊锡球77时的成功率进行试验的试验结果表示在图14中的图表中。 
由该结果可知，从开口上端到露出的连接焊盘表面的深度D2优选是18μm以下。这可以被认为是因为深度X越深，在阻焊层开口上端面，焊锡球就越容易卡住，进而不能搭载在开口上。另一方面，若D2不足3μm，虽然焊锡凸块的搭载性不成问题，但是，作为堤坝的能力下降，有时在对焊锡球进行回流焊时，焊锡流出，与相邻的连接焊盘的焊锡接触，发生短路。另外，搭载焊锡球后，移动基板时，有时完成搭载的焊锡球会跳出阻焊层，出现没有搭载焊锡球的连接焊盘。因此，深度D2的优选范围是3～18μm。而且，用X射线观察D2＝3、7、15、20μm时的焊锡凸块的内部，D2＝3、7、15μm时，在凸块内部没有观察到空穴，但在D2＝20μm时，在凸块内部观察到了空穴。另外，在该实施例中，用图12所示的装置进行焊锡球的搭载，但也可以用在日本特开平3-265150号、日本特开2000-77837号、日本特开平8-20682号等中公开的拾取焊锡凸块将其搭载在连接焊盘上的方法进行焊锡球的搭载。 

Claims (3)

1.一种印刷线路板的制造方法，该印刷线路板具有凸块，该制造方法至少具有以下(a)～(c)工序：
(a)形成使连接焊盘的一部分露出并具有从开口上端到露出的上述连接焊盘表面的深度为3～18μm的开口的阻焊层，
(b)在该开口上搭载低熔点金属球，
(c)进行回流焊，在上述连接焊盘上由低熔点金属球形成凸块。
2.根据权利要求1所述的印刷线路板的制造方法，其特征在于，在将上述低熔点金属球搭载在上述开口的状态下，使上述低熔点金属球与上述连接焊盘接触。
3.根据权利要求1或2所述的印刷线路板的制造方法，其特征在于，在上述(b)工序中，使用具有与上述阻焊层的开口相对应的开口部的掩模，使筒构件位于上述掩模的上方，该筒构件具有与该掩模相对的开口部，通过由该筒构件吸引空气，使上述低熔点金属球聚集到该筒构件正下方的上述掩模上，通过使上述筒构件或者印刷线路板及掩模在水平方向上相对移动，从而使聚集到上述筒构件正下方的上述低熔点金属球通过上述掩模的开口部向上述阻焊层的开口落下。
CN2007800007403A 2006-01-27 2007-01-26 印刷线路板的制造方法 Expired - Fee Related CN101331812B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2006019522 2006-01-27
JP019522/2006 2006-01-27
PCT/JP2007/051274 WO2007086509A1 (ja) 2006-01-27 2007-01-26 プリント配線板の製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN2010106229552A Division CN102098881A (zh) 2006-01-27 2007-01-26 印刷线路板的制造方法

Publications (2)

Publication Number Publication Date
CN101331812A CN101331812A (zh) 2008-12-24
CN101331812B true CN101331812B (zh) 2011-02-02

Family

ID=38309295

Family Applications (2)

Application Number Title Priority Date Filing Date
CN2007800007403A Expired - Fee Related CN101331812B (zh) 2006-01-27 2007-01-26 印刷线路板的制造方法
CN2010106229552A Pending CN102098881A (zh) 2006-01-27 2007-01-26 印刷线路板的制造方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN2010106229552A Pending CN102098881A (zh) 2006-01-27 2007-01-26 印刷线路板的制造方法

Country Status (7)

Country Link
US (1) US8083123B2 (zh)
EP (1) EP1978795A4 (zh)
JP (1) JP4666399B2 (zh)
KR (1) KR100973950B1 (zh)
CN (2) CN101331812B (zh)
TW (1) TW200746964A (zh)
WO (1) WO2007086509A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105556648A (zh) * 2013-10-16 2016-05-04 英特尔公司 集成电路封装衬底
US10068852B2 (en) 2013-12-18 2018-09-04 Intel Corporation Integrated circuit package with embedded bridge

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101854771A (zh) 2005-06-30 2010-10-06 揖斐电株式会社 印刷线路板
JP2009081334A (ja) * 2007-09-27 2009-04-16 Aisin Aw Co Ltd 多層プリント配線基板及びその製造方法。
KR101022942B1 (ko) * 2008-11-12 2011-03-16 삼성전기주식회사 흐름 방지용 댐을 구비한 인쇄회로기판 및 그 제조방법
KR101079513B1 (ko) 2009-05-13 2011-11-03 삼성전기주식회사 범프 인쇄장치 및 그 제어방법
US9455211B2 (en) 2013-09-11 2016-09-27 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure with openings in buffer layer
US9425121B2 (en) 2013-09-11 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure with guiding trenches in buffer layer
US9153550B2 (en) * 2013-11-14 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design with balanced metal and solder resist density
JP2015231003A (ja) * 2014-06-06 2015-12-21 イビデン株式会社 回路基板および回路基板の製造方法
JP6384647B1 (ja) * 2017-02-23 2018-09-05 株式会社村田製作所 電子部品、電子機器および電子部品の実装方法
CN107318228B (zh) * 2017-08-29 2019-09-06 郑州云海信息技术有限公司 一种印制电路板的制造方法及其制造装置
US10695875B2 (en) * 2018-03-19 2020-06-30 Asia Vital Components Co., Ltd. Soldering method of soldering jig
CN111162013B (zh) * 2020-01-06 2021-08-24 亿芯微半导体科技(深圳)有限公司 一种半导体封装结构及一种半导体封装的制造方法
CN111199889B (zh) * 2020-01-10 2021-07-16 宝德照明集团有限公司 一种半导体封装结构及其制备方法

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06105731B2 (ja) 1990-03-14 1994-12-21 新日本製鐵株式▲会▼社 バンプの転写方法及びその装置
JPH0820682A (ja) 1994-07-04 1996-01-23 Mitsubishi Cable Ind Ltd 電気絶縁性組成物
JPH09326412A (ja) * 1996-06-07 1997-12-16 Tokuyama Corp ハンダボールの取り付け方法
US5921458A (en) 1997-06-25 1999-07-13 Fan; Kuang-Shu Integrated circuit solder ball implant machine
CN100380792C (zh) 1998-07-06 2008-04-09 三洋电机株式会社 音响·振动发生装置
JP2000077837A (ja) 1998-08-27 2000-03-14 Ibiden Co Ltd 半田ボール搭載装置及び搭載方法
EP1845759A1 (en) * 1998-12-16 2007-10-17 Ibiden Co., Ltd. Conductive connecting pin and package substrate
JP2001267731A (ja) 2000-01-13 2001-09-28 Hitachi Ltd バンプ付き電子部品の製造方法および電子部品の製造方法
JP4130526B2 (ja) * 2000-11-10 2008-08-06 株式会社日立製作所 バンプ形成方法およびその装置
JP3819806B2 (ja) * 2002-05-17 2006-09-13 富士通株式会社 バンプ電極付き電子部品およびその製造方法
JP4047251B2 (ja) * 2003-07-31 2008-02-13 日本特殊陶業株式会社 配線基板および配線基板の製造方法
EP1776004A4 (en) 2004-08-04 2009-09-02 Ibiden Co Ltd METHOD AND DEVICE FOR FASTENING A SOLDERING BALL
CN101868120A (zh) * 2005-06-30 2010-10-20 揖斐电株式会社 印刷线路板及其制造方法
US7823762B2 (en) 2006-09-28 2010-11-02 Ibiden Co., Ltd. Manufacturing method and manufacturing apparatus of printed wiring board
WO2008053833A1 (fr) * 2006-11-03 2008-05-08 Ibiden Co., Ltd. Tableau de câblage imprimé multicouche
DE102007023666A1 (de) * 2006-12-01 2008-06-05 Infineon Technologies Ag Halbleiterbaustein und Verfahren zur Herstellung eines Halbleiterbausteins
US7907801B2 (en) * 2007-01-17 2011-03-15 Ibiden Co., Ltd. Optical element, package substrate and device for optical communication
US7972521B2 (en) * 2007-03-12 2011-07-05 Semiconductor Components Industries Llc Method of making reliable wafer level chip scale package semiconductor devices
US7674987B2 (en) * 2007-03-29 2010-03-09 Ibiden Co., Ltd. Multilayer printed circuit board
TWI334643B (en) * 2007-04-11 2010-12-11 Nan Ya Printed Circuit Board Corp Solder pad and method of making the same
WO2009144846A1 (ja) * 2008-05-30 2009-12-03 イビデン株式会社 半田ボール搭載方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105556648A (zh) * 2013-10-16 2016-05-04 英特尔公司 集成电路封装衬底
US10325843B2 (en) 2013-10-16 2019-06-18 Intel Corporation Integrated circuit package substrate
US10068852B2 (en) 2013-12-18 2018-09-04 Intel Corporation Integrated circuit package with embedded bridge

Also Published As

Publication number Publication date
WO2007086509A1 (ja) 2007-08-02
US20090120680A1 (en) 2009-05-14
KR100973950B1 (ko) 2010-08-05
EP1978795A1 (en) 2008-10-08
JP4666399B2 (ja) 2011-04-06
CN101331812A (zh) 2008-12-24
TWI353204B (zh) 2011-11-21
EP1978795A4 (en) 2012-10-31
KR20080028467A (ko) 2008-03-31
JPWO2007086509A1 (ja) 2009-06-25
TW200746964A (en) 2007-12-16
CN102098881A (zh) 2011-06-15
US8083123B2 (en) 2011-12-27

Similar Documents

Publication Publication Date Title
CN101331812B (zh) 印刷线路板的制造方法
CN101356642B (zh) 印刷线路板及其印刷线路板的制造方法
CN101283631B (zh) 印刷线路板的制造方法
US8800143B2 (en) Multilayer printed wiring board and manufacturing method thereof
JP5021472B2 (ja) プリント配線板の製造方法
CN101180727B (zh) 印刷线路板及其制造方法
CN101112142A (zh) 多层印刷线路板
US7402760B2 (en) Multi-layer printed wiring board and manufacturing method thereof
US7845547B2 (en) Method for manufacturing a printed wiring board

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20110202

Termination date: 20170126