Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/01—Manufacture or treatment
  • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
  • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0213—Electrical arrangements not otherwise provided for
  • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
  • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
  • H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
  • H05K1/0222—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
  • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
  • H10W20/211—Through-semiconductor vias, e.g. TSVs
  • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
  • H10W20/2125—Top-view shapes
  • H10W20/2128—Coaxial through-semiconductor vias
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W42/00—Arrangements for protection of devices
  • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
  • H10W70/63—Vias, e.g. via plugs
  • H10W70/635—Through-vias
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/03—Use of materials for the substrate
  • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09209—Shape and layout details of conductors
  • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
  • H05K2201/09809—Coaxial layout
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
  • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
  • H05K2203/0703—Plating
  • H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
  • H05K3/42—Plated through-holes or plated via connections
  • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W44/00—Electrical arrangements for controlling or matching impedance
  • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
  • H10W44/203—Electrical connections
  • H10W44/209—Vertical interconnections, e.g. vias
  • H10W44/212—Coaxial feed-throughs in substrates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
  • H10W70/69—Insulating materials thereof
  • H10W70/698—Semiconductor materials that are electrically insulating, e.g. undoped silicon
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T29/00—Metal working
  • Y10T29/49—Method of mechanical manufacture
  • Y10T29/49002—Electrical device making
  • Y10T29/49117—Conductor or circuit manufacturing
  • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
  • Y10T29/49155—Manufacturing circuit on or in base
  • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Definitions

• Penetration substrate and interposer and method of manufacturing the penetration substrate
• the present invention relates to a through board and an interposer, and a method for manufacturing the through board, and more particularly to a through board, an interposer and a method for manufacturing the through board that can be used as a signal transmission path.
• a coaxial line having a coaxial structure is formed inside a substrate and used as a signal wiring layer.
• the present invention has been made in view of the above problems, and an object thereof is to provide a through-hole substrate and an interposer that can eliminate noise due to crosstalk, and a method for manufacturing the through-hole substrate.
• the through-hole substrate according to the present invention includes a substrate having a through-hole penetrating the front and back surfaces, a first conductive layer provided along the inner wall surface of the through-hole and having an inner wall surface therein, and an inner surface of the first conductive layer.
• a second conductive layer is provided along the wall surface with an insulating layer interposed therebetween.
• a through-hole substrate includes a first conductive layer provided along an inner wall surface of a through-hole penetrating the front and back surfaces, and an insulating layer between the inner wall surface of the first conductive layer. And a second conductive layer provided via. The second conductive layer is surrounded by the first conductive layer through the insulating layer inside the through hole. Since a crack configuration is formed, a configuration of a coaxial cable with improved shielding is obtained.
• the first conductive layer operates as a shield line
• the second conductive layer operates as a signal line
• the substrate may be an insulator substrate or a semiconductor substrate.
• an insulating layer is further included between the inner wall surface of the through hole and the first conductive layer.
• the through hole may be a through hole of an interposer.
• a method for manufacturing a through-hole substrate includes a step of preparing a substrate having front and back surfaces, a step of forming a through-hole in the substrate, and an inner wall surface of the through-hole. Forming a first conductive layer having an inner wall surface therein, and forming a second conductive layer along the inner wall surface of the first conductive layer with an insulating layer therebetween.
• the step of preparing the substrate having front and back surfaces includes the step of preparing a semiconductor substrate, and before forming the first conductive layer having the inner wall surface along the inner wall surface of the through hole.
• the method further includes a step of forming an insulating layer having an inner wall surface along the inner wall surface of the through hole, and then forming a second conductive layer along the inner wall surface of the insulating layer.
• the interposer is provided with a substrate, a first conductive layer provided on the substrate, and an insulating layer provided on the first conductive layer. And a second conductive layer sandwiched between them.
• the interposer a substrate, a first conductive layer provided on the substrate, and a second conductive layer provided on the substrate and provided on the first conductive layer with an insulating layer interposed therebetween. Therefore, the passive element can be formed using the first conductive layer and the second conductive layer separated by the insulating layer.
• the second conductive layer is surrounded by the first conductive layer with an insulating layer interposed therebetween.
• the first conductive layer and the second conductive layer constitute a passive element.
• the first conductive layer is held at a first potential
• the second conductive layer is a second current different from the first potential. May be held at the same potential.
• the first conductive layer may operate as a shield line, and the second conductive layer may operate as a signal line.
• the substrate includes a conductor or a semiconductor substrate, and when the substrate is a conductor or a semiconductor substrate, the substrate has a potential different from that of the first conductive layer and the second conductive layer. It may be held, or may be held at the same potential as at least one of the first conductive layer or the second conductive layer.
• a capacitor when the first conductive layer is held at the first potential and the second conductive layer is held at the second potential different from the first potential, a capacitor can be formed.
• the first conductive layer and the second conductive layer are held at the same potential, it can function as a guard electrode.
• the first conductive layer is surrounded by the second conductive layer with an insulating layer interposed therebetween.
• the first conductive layer is surrounded by the second conductive layer with an insulating layer in between
• an interposer that can eliminate noise due to crosstalk can be provided.
• FIG. 1A is a diagram showing, for each step, a method of manufacturing a through-hole substrate when a semiconductor substrate is used as the substrate.
• FIG. 1B is a diagram showing, for each step, a method for manufacturing a through-hole substrate when a semiconductor substrate is used as the substrate.
• FIG. 1C is a diagram showing, for each step, a method for manufacturing a through-hole substrate when a semiconductor substrate is used as the substrate.
• FIG. 1D is a diagram showing, for each step, a method for manufacturing a through-hole substrate when a semiconductor substrate is used as the substrate.
• FIG. 2A is a diagram showing a step-by-step manufacturing method for a through-hole substrate when an insulating substrate is used as the substrate.
• FIG. 2B is a diagram showing a step-by-step manufacturing method for a through-hole substrate when an insulating substrate is used as the substrate.
• FIG. 2D is a diagram showing a step-by-step manufacturing method for a through-hole substrate when an insulating substrate is used as the substrate.
• FIG. 3 is a cross-sectional view of the vicinity of a through hole of an interposer according to an embodiment of the present invention.
• FIG. 4A is a diagram showing the arrangement of wiring layers on the substrate of the interposer.
• FIG. 4B is a diagram showing the arrangement of wiring layers on the substrate of the interposer.
• FIG. 5A is a diagram showing a configuration when a shield function is provided inside the interposer.
• FIG. 5B is a diagram showing a configuration when a shield function is provided inside the interposer.
• FIG. 6A is a diagram showing processing for each step when a passive element is formed in the interposer.
• FIG. 6B is a diagram showing processing for each step when a passive element is formed in the interposer.
• FIG. 6C A diagram showing processing for each step when a passive element is formed in the interposer.
• FIG. 6D is a diagram showing processing for each step when a passive element is formed in the interposer.
• FIG. 7A is a perspective view of a functional element configured in an interposer.
• FIG. 7B is a perspective view of a functional element configured in the interposer.
• FIG. 7C is a perspective view of a functional element configured in the interposer.
• FIG. 8 is a circuit diagram of a configuration including a conductive layer and an insulating layer.
• FIG. 1A to FIG. 1D are diagrams showing a through hole substrate manufacturing process according to an embodiment of the present invention step by step.
• the term “penetrating substrate” refers to a substrate having a through-hole extending over the back surface of the substrate, including a printed circuit board (including flexible) and an interposer (silico). Included).
• a silicon substrate (penetrating substrate) 10 having a front surface 11 and a back surface 12 and having a plurality of through holes 19 penetrating between both surfaces is prepared. It is assumed that the entire substrate 10 is covered with a silicon oxide film 13.
• a Zn layer 14 is formed in the through hole 19 and around the front and back surfaces by electroless plating (FIG. 1A).
• a Cu layer 15 is also formed on the Zn layer 14 by electroless plating (FIG. 1B, these layers become the first conductive layers).
• the insulating layer 16 is formed on the Cu layer 15 by sputtering, for example.
• the insulating layer 16 is not limited to sputtering, and a silicon oxide film or a silicon nitride film may be formed by CVD, or an electrodeposited resin film may be formed.
• the electrodeposited resin include PTFE, resist, polyimide, polyamide, and the like.
• a Cu seed layer 17 is provided, which is formed as an electric field or electroless plating electrode, and an insulating layer is formed from this electrode toward the front surface 11 side.
• a conductive layer (second conductive layer) 18 is formed by growing a plating layer inside the through hole 16 (FIG. 1D).
• the through hole 19 of the substrate 10 is filled with the conductive layer 18, the insulating layer 16, and the conductive layers 15 and 14 from the center thereof, and a coaxial cable shape with improved shielding is obtained. Since this shape is a via hole having the shape of a coaxial cable that can reduce noise, reduce parasitic capacitance, and transmit signals at high speed, this shape is hereinafter referred to as a coaxial via.
• an insulating substrate such as a glass substrate or a sapphire substrate is used as the through substrate.
• FIGS. 2A to 2D are diagrams corresponding to FIGS. 1A to 1D in the case where such an insulating substrate is used.
• the through substrate is an insulating substrate, as in the previous embodiment, an insulating film such as an oxide film is formed along the inner wall of the through hole. It is not necessary to provide the edge layer 13.
• the other parts are the same as those in the previous embodiment, and a description thereof will be omitted.
• FIG. 3 is a cross-sectional view of the vicinity of the through hole of the interposer when the present invention is applied to the interposer.
• the interposer has a conductive layer (second conductive layer) 27 inside through hole 28, and conductive layer 27 is connected to conductive layer (second conductive layer) via insulating layer 23. ) Surrounded by 24.
• the conductive layer 27 is surrounded by the conductive layer via the insulating layer 23, a configuration of a coaxial cable can be obtained. As a result, an interposer resistant to noise can be provided.
• the conductive layer 24 extends on the substrate 20 with the insulating layer 29 therebetween, with the insulating layer 23 interposed therebetween and surrounding the conductive layer 27. At this time, as shown in FIG. 3, the conductive layer 27 is used as the signal line 31, and the conductive layer 24 is used as the shield wirings 32a and 32b.
• the signal line 31 and the shield wirings 32a and 32b are not limited to a cylindrical shape, and both are the substrate 2
• the shield wiring is not connected to the signal line and is in a floating state. However, if necessary, the signal line and shield line may be connected to the same potential as explained later! /.
• FIG. 4A is a cross-sectional view of the interposer in that case.
• a conductive layer 3la serving as a signal line is provided in the center portion on the interposer substrate 20 via an insulating layer 29, and vertically and horizontally so as to surround it.
• Conductive layers 32a, 32b, 32c and 32d are formed as shield layers.
• FIG. 4B is a modification of FIG. 4A.
• a conductive layer 32e having the same structure as that shown in FIG. 4A is formed by connecting all the conductive layers to be the force shield lines, and 3 lb of the conductive layer to be the signal lines is connected to the conductive layer 32e via the insulating layer 28.
• a wiring layer having a coaxial structure can be easily configured in the interposer.
• FIG. 5A and FIG. 5B are diagrams showing electrode pads.
• 5A is a plan view (a plan view indicated by AA in FIG. 5B), and
• FIG. 5B is a perspective view corresponding to FIGS. 4A and 4B.
• the substrate is omitted.
• each signal line 41a to 41d connected to each of four electrode pads 45a to 45d are shown.
• Each signal line 41a to 41d is surrounded by shield electrodes 42, 43 and 44 provided on the top and bottom and on the left and right.
• passive elements such as a coin L, a capacitor C, and a resistor R are formed inside the interposer.
• FIG. 6A to FIG. 6D are diagrams showing the formation of the passive element in this case step by step. Here, details of the photolithographic process are omitted.
• a silicon substrate 50 is prepared. Although not shown, the substrate surface is covered with an insulating film such as Si 2 O or SiN. Next, a conductive layer made of metal on the surface 51 of the substrate 50
• an insulating layer 53 is formed over the conductive layer 52 (FIG. 6A).
• the insulating layer 53 may be formed by using a CVD to form a silicon oxide film or a silicon nitride film, or by sputtering or electrodeposition.
• a via hole is provided in part of the insulating layer 53 and connected to the conductive layer 54 formed on the insulating layer 53.
• An insulating layer 55 is further formed thereon.
• FIG. 6D is a cross-sectional view of the portion indicated by DD in FIG. 6C.
• the interposer has a configuration in which the conductive layer 52 and the conductive layer 54 face each other through the insulating layer 53. This configuration can be used as a capacitor.
• the relationship between the signal line and the shield line can be obtained by setting the conductive layer 52 and the conductive layer 54 to the same potential. In this way, it is possible to form passive elements in the interposer.
• FIGS. 6A to 6D are perspective views showing specific examples in this case.
• the oxide film on the substrate 60 is omitted.
• FIG. 7A is a perspective view when the resistance R is formed.
• a metal conductive layer 62 is formed as the second layer by connecting to the coaxial via 61 provided in the silicon substrate 60.
• a metal conductive layer 64 is formed on the same layer.
• a polysilicon layer 63 is formed on the surface of the substrate 60. Are connected by first and second conductive layers 62 and 64.
• the polysilicon layer 63 Since the polysilicon layer 63 has a resistance value several orders of magnitude greater than that of metal, it can be used as a resistance layer.
• FIG. 7B is a perspective view when the capacitor C is formed.
• a metal conductive layer 66 is formed as the second layer by connecting to the coaxial via 61 provided in the silicon substrate 60.
• a metal conductive layer 67 is formed on the same second layer.
• a metal conductive layer 65 is formed on the surface of the substrate 60 with an insulating layer 68 sandwiched between the conductive layer 67 and the conductive layer 66 and the conductive layer 65 are connected.
• the conductive layer 65 and the conductive layer 67 function as the capacitor C because the insulating layer 68 is sandwiched therebetween.
• FIG. 7C is a perspective view when another capacitor C is formed.
• a metal conductive layer 69 is formed on the surface of the substrate 60 with the insulating layer 68 interposed between the coaxial vias 61 provided in the silicon substrate 60.
• the substrate 60 and the conductive layer 69 function as the capacitor C because the insulating layer 68 is sandwiched between them.
• FIG. 8 is a circuit diagram showing the configuration 70 including the conductive layer and the insulating layer shown in FIGS. 6A to 6D and FIGS. 7A to 7C.
• the configuration shown in FIG. 7B is taken as an example.
• conductive layers 65 and 67 are connected via insulating layer 68 therebetween. It is assumed that the conductive layer 65 is grounded and the conductive layer 67 is connected to the power source. In this case, configuration 70 functions as capacitor C.
• the parasitic capacitance can be reduced and the guard layer functions as a shield wiring.
• the substrate is a semiconductor substrate such as a silicon substrate or a conductive substrate as shown in the embodiment mode
• the substrate is held at a potential different from that of the conductive layer 65 or the conductive layer 67.
• the same potential as that of at least one of the conductive layer 65 and the conductive layer 67 may be maintained.
• the present invention is not limited to this, and may be a rectangle or a polygon.
• the force described above is an example in which a silicon substrate is used as the substrate.
• the present invention is not limited to this, and a glass substrate may be an insulating substrate such as a sapphire substrate.
• the through substrate and the interposer according to the present invention can be advantageously used as a substrate having the same function as that of the coaxial cable.

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• Physics & Mathematics (AREA)
• Electromagnetism (AREA)
• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
• Production Of Multi-Layered Print Wiring Board (AREA)
• Semiconductor Integrated Circuits (AREA)

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• 2005
  • 2005-07-05 KR KR1020087003018A patent/KR100858075B1/ko not_active Expired - Fee Related
  • 2005-07-05 EP EP05765497A patent/EP1775761A4/en not_active Withdrawn
  • 2005-07-05 US US11/631,638 patent/US7866038B2/en not_active Expired - Fee Related
  • 2005-07-05 WO PCT/JP2005/012425 patent/WO2006004128A1/ja not_active Ceased
  • 2005-07-06 TW TW094122866A patent/TW200616503A/zh not_active IP Right Cessation

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