WO2004084314A1 - 半導体装置とその製造方法 - Google Patents
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- WO2004084314A1 WO2004084314A1 PCT/JP2003/003382 JP0303382W WO2004084314A1 WO 2004084314 A1 WO2004084314 A1 WO 2004084314A1 JP 0303382 W JP0303382 W JP 0303382W WO 2004084314 A1 WO2004084314 A1 WO 2004084314A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
- H01L29/7885—Hot carrier injection from the channel
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
- H10B41/44—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a control gate layer also being used as part of the peripheral transistor
Definitions
- the present invention relates to a semiconductor device and a method of manufacturing the same, for example, a semiconductor device including a nonvolatile memory cell transistor and a peripheral circuit including a logic cell transistor, and a method of manufacturing the same.
- the floating gate structure As an electrically rewritable nonvolatile memory, a structure in which a floating gate structure having a charge retention function and a control gate structure that applies an electric field to the channel via the floating gate structure are stacked on a semiconductor region serving as a channel It has been known.
- the floating gate structure is formed to include a silicon layer insulated by an insulating layer or an oxide film forming a nitride film having a charge storage function, and a stack of a nitride film and an oxide film.
- Program by selectively injecting electrons into the floating gate structure.
- the conductivity of the channel changes depending on the presence or absence of charges in the floating gate structure, and the written information can be read.
- the written information can be erased.
- a floating electrode is formed of a silicon layer sandwiched between insulating layers, and the sidewalls are thermally oxidized.
- a floating gate electrode wrapped with a high-quality insulating film such as a thermal oxide film improves charge retention characteristics. Even when a floating gate structure is formed of an oxide film, a nitride film, and an oxide film, the charge retention characteristics can be improved by covering the side surfaces with an oxide film or the like.
- Semiconductor integrated circuit devices such as system LSIs, increase the degree of integration, as well as nonvolatile memories, high-voltage insulated gate field-effect (MOS) transistors for driving them, low-voltage MOS transistors for logic circuits, etc. It is configured to include a plurality of types of semiconductor elements. Low-voltage MOS transistors for logic circuits improve operating speed. Therefore, the gate length is reduced and the gate insulating film is formed thin.
- MOS insulated gate field-effect
- the manufacturing process of a semiconductor integrated circuit is designed so that the same process is preferably used for manufacturing a plurality of types of semiconductor elements.
- the gate electrode of the MOS transistor is formed of the same silicon layer as the control gate electrode of the nonvolatile memory element.
- the side wall of the gate electrode of the MOS transistor is also thermally oxidized.
- oxidizing species also penetrate into the interface between the silicon substrate and the insulating film thereon and the interface between the silicon layer and the insulating film, forming an oxidized region called a purse beak.
- the low-voltage MOS transistor has a short gate length and is formed using a thin gate insulating film.
- the thickness of the gate insulating film below the edge of the gate electrode becomes thicker, which reduces the drive current of the MOS transistor.
- the stacked gate structure of the nonvolatile memory and the single-layer gate structure of the MOS transistor are patterned by different processes using different masks. Therefore, the mask alignment margin is superimposed. If the margin for one mask alignment is 0.2 / m, the margin for two mask alignments is 0.28 / m. Increasing the mask alignment margin hinders high integration.
- Japanese Patent Application Laid-Open No. H10-2223782 proposes a nonvolatile memory element in which a control gate electrode is formed by a diffusion region in a substrate.
- a low-resistance region that functions as a control gate is formed in a semiconductor substrate, and a floating gate electrode that extends from above the channel region of the memory transistor to above the low-resistance region that functions as a control gate electrode is formed.
- the control gate electrode can be formed in the same process as the source / drain region of the memory transistor, and the manufacturing process of the nonvolatile memory can be simplified.
- Patent Document 1
- An object of the present invention is to provide a manufacturing method for manufacturing such a semiconductor device.
- Another object of the present invention is to provide a semiconductor device manufacturing method for manufacturing such a semiconductor device with high accuracy.
- Another object of the present invention is to provide a semiconductor device manufacturing method for efficiently manufacturing such a semiconductor device.
- a semiconductor substrate having a first element region and a second element region on a surface thereof, and a gate parsvic formed on the first element region and having a first length.
- a first transistor of a double gate type having a gate sidewall covered with a thermal oxide film, having a floating gate and a control gate, and a first transistor formed on the second element region and having a length shorter than a first length.
- a semiconductor device that operates as a logic circuit element is provided.
- Forming a stack of a gate structure stack (c) forming a stack of a gate electrode conductive layer and a mask insulating layer above the floating gate structure stack and above the second active region; And (e) masking the second active region, using the masking insulating layer as an etching mask in the first active region, and Etching the conductive layer for the floating gate structure and the stack for the floating gate structure to pattern the floating gate structure and the control gate structure; and (f) at least a floating gate structure.
- FIGS. 1A to 1N are cross-sectional views showing main steps of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.
- FIG. 2 is an enlarged cross-sectional view showing the structure of a gut electrode manufactured according to the first embodiment.
- 3A and 3B are diagrams illustrating the operation of the nonvolatile memory element.
- 4A to 4D are cross-sectional views showing main steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.
- 5A to 5E are cross-sectional views showing main steps of a method for manufacturing a semiconductor device according to the third embodiment of the present invention.
- 6A to 6E are sectional views showing main steps of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.
- 7A to 7G are a plan view and a cross-sectional view schematically illustrating the configuration and operation of a semiconductor nonvolatile memory element having a single-layer gate electrode.
- 8A to 8E are cross-sectional views schematically showing main steps of a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.
- 9A to 9D are sectional views schematically showing main steps of a method for manufacturing a semiconductor device according to a sixth embodiment of the present invention.
- Inactive rewritable semiconductor memories require high voltages for programming and erasing.
- MOS high-voltage field effect
- the logic circuit consists of low-voltage MOS transistors to reduce power consumption.
- the integration of non-volatile memory circuits and logic circuits also requires the integration of low-voltage MOS transistors.
- FIG. 1A to 1N are cross-sectional views illustrating a method of manufacturing a semiconductor device according to a first embodiment of the present invention.
- FIG. 1A to 1N are cross-sectional views illustrating a method of manufacturing a semiconductor device according to a first embodiment of the present invention.
- a shallow trench 2 is formed on one surface of a semiconductor substrate 1 such as a silicon substrate, buried with an insulating film, and the shallow trench isolation (STI) 3 is formed by removing the insulating film on the surface.
- the isolation region can also be formed by local oxidation (LOCOS). Regions A R 1, AR 2, and AR 3 surrounded by STI are defined.
- the area AR 1 is an area for forming a nonvolatile memory element
- the area AR 2 is an area for forming a low-voltage MOS transistor of a logic circuit
- the area AR 3 is for controlling a nonvolatile memory element. This is the area where the high-voltage MOS transistor is formed.
- the semiconductor substrate 1 is heated to 800 to 110 ° C. to form a thermal oxide film 4 having a thickness of 6 to 12 nm in an oxidizing atmosphere.
- This thermal oxide film 4 forms a tunnel oxide film of the nonvolatile memory element.
- FIG. 1 B which functions as a floating gate Ichito electrode of the nonvolatile memory device, phosphorus 1 X 1 0 2 ° as n-type impurity cm- 3 ⁇ 3 X 1 0 21 cm- 3 doped amorphous silicon
- a film 5 is formed on the tunnel oxide film 4 by chemical vapor deposition (CV D) having a thickness of 50 nm to 100 nm. After the non-doped amorphous silicon film is formed, phosphorus may be doped by ion implantation.
- a silicon nitride film 7 of 5 nm to 10 nm is formed.
- a thermal oxide film 8 having a thickness of 3 nm to 10 nm is formed on the surface of the silicon nitride film 7 at 900 ° C. to 100 ° C. in an oxidizing atmosphere.
- the amorphous silicon film is converted into a polycrystalline silicon film by the subsequent heat treatment. In this way, a stack of an oxide film-nitride film-oxide film (ONO film) is formed on the silicon film 5.
- the surface of the region AR1 is covered with a resist mask 9, and the ONO film, the silicon film 5, and the tunnel oxide film 4 in the regions AR2 and AR3 are removed by etching. In regions AR2 and AR3, the silicon surface is exposed. After that, the resist mask 9 is removed.
- heat is applied to the exposed silicon surface with a thickness of 10 nm to 50 nm.
- An oxide film is formed by thermal oxidation at 800 ° C. to 110 ° C. This thermal oxide film forms the gate oxide film of the high-voltage MOS transistor in addition to the thermal oxide film to be formed next.
- the thermal oxide film in the area AR 2 is removed by etching.
- a thermal oxide film 12 having a thickness of 1.5 nm to 8 nm is formed on the surface of the area AR 2 by thermal oxidation at a temperature of 700 ° C. to 110 ° C. This thermal oxide film forms the gate oxide film of the low-voltage MOS transistor.
- a thin gate oxide film suitable for a low-voltage MOS transistor is formed in the region AR2
- a thick oxide film suitable for a high-voltage MOS transistor is formed in the region AR3.
- FIG. 1 as shown in E, phosphorus 5 X 1 0 20 c m- 3 ⁇ 5 X 1 0 21 cm- 3 doped thickness 1 5 0 nm ⁇ 2 5 0 nm of Amorufasushiri con as n-type impurity
- a film 14 is formed on the silicon substrate surface by CVD. After forming a non-doped amorphous silicon film, phosphorus may be doped by ion implantation.
- a tungsten silicide (WSi) film can be grown on the amorphous silicon film with a thickness of 100 nm to 200 nm CVD.
- a plasma nitride film 15 is grown as a hard mask layer to a thickness of 20 nm to 150 ⁇ m.
- a hard mask layer such as a plasma oxynitride film or a plasma oxide film may be used. In this manner, a stack of a conductive layer to be a gate electrode and a hard mask layer thereon is formed.
- a resist pattern 16 having a gate electrode shape is formed on the hard mask layer 15.
- the resist pattern 16 is etched and the underlying hard mask layer 15 is etched.
- the hard mask layer 15 is patterned in the shape of a gate electrode. Thereafter, the resist pattern 16 is removed.
- the regions AR 2 and AR 3 are covered with a resist mask 17, and in the region AR 1, the hard mask 15 is used as an etching mask, and the silicon layers 14 and ⁇ NO films 6 and 7 are formed. 8. Etch silicon layer 5. The gate electrode of the nonvolatile memory element is patterned. Thereafter, the resist mask 17 is removed.
- the substrate was heated to 800 ° C. to 900 ° C. in an oxidizing atmosphere, A thermal oxide film 18 having a thickness of 3 nm to 10 nm is formed on the exposed side wall of the silicon layer.
- the sidewalls of the silicon layers 5 and 14 are thermally oxidized, and oxidized species penetrate into the interface between the silicon substrate 1 and the silicon layers 5 and 14 and the insulating layer, resulting in a parse beak at the edge of the insulating layer. It is formed.
- oxide film 18 is formed on the surface of silicon layer 14.
- the surface of the silicon substrate 1 is covered with the gate oxide films 11 and 12 and the silicon film 14 to prevent oxidation.
- FIG. 2 shows an enlarged view of the gate electrode structure of the nonvolatile memory element and the MOS transistor. Although parse beaks are formed at the ends of oxide films 4, 6, and 8, parse beaks are not generated in oxide film 1 2 (1 1).
- n-type region 21 is formed by ion implantation at LX 10 15 cm— 2 .
- the figure shows the case where the low-concentration n-type region 21 is formed only on one side of the gate electrode, it may be formed on both sides.
- arsenic ions are implanted at an acceleration energy of 30 keV to 60 keV and a dose of 2 ⁇ 10 15 cm— 2 to 7 ⁇ 10 15 cm— 2 to form a high-concentration n-type region 22.
- a high impurity concentration source / drain region 22 and a low concentration n-type region 21 surrounding at least one of them are formed on both sides of the gate electrode.
- the low-concentration n-type region 21 has a function of increasing the efficiency when removing charges from the silicon layer 5.
- the area AR 1 is covered with a resist mask 23, and in the areas AR 2 and AR 3, the silicon layer 14 is etched using the hard mask 15 as an etching mask.
- the gate electrodes are patterned in the regions AR2 and AR3. Thereafter, the resist mask 23 is removed.
- ion implantation is performed to form low-concentration extensions 25 of the source / drain regions.
- a CMOS circuit is formed, a p-channel region and an n-channel region are selectively exposed using a mask, and p-type impurities and n-type impurities are selectively formed.
- an insulating film such as a silicon oxide film is D is deposited and anisotropic etching such as reactive ion etching (RIE) is performed to remove the insulating film on the flat surface and form a sidewall spacer 26 on the side wall of the gate structure. If the hard mask layer 15 on the gate electrode remains, it is removed by etching. '
- the area AR 1 is covered with a resist mask 27, and high-concentration impurities are ion-implanted into the areas AR 2 and AR 3 to form a high-concentration source Z drain region 28.
- the impurity is separately formed in the n-channel region and the p-channel region as described above.
- the resist mask 27 is removed.
- the implanted impurities are activated by annealing. By these heat treatments, the silicon layer 14 also becomes a polycrystalline silicon layer.
- a Co Si film is deposited on the silicon surface by depositing a Co film on the substrate surface and performing a silicidation reaction. Unreacted Co is removed. After that, an interlayer insulating film 30 is formed on the substrate surface, the surface is flattened by chemical mechanical polishing (CMP), and then a contact hole is formed using a resist mask. A barrier metal layer filling the contact hole and a W layer are deposited, and the metal layer on the flat surface is removed by CMP to form a W plug 31.
- CMP chemical mechanical polishing
- a non-volatile memory element is formed in the area AR1
- a low-voltage MOS transistor is formed in the area AR2
- a high-voltage MOS transistor is formed in the area AR3.
- high drive characteristics are maintained because the occurrence of parse beak is prevented. Since the gate electrode of each semiconductor element is positioned in one mask process, the alignment margin is small.
- FIG. 2 shows an enlarged view of the gate electrode of the nonvolatile memory element and the gate electrode of the MOS transistor formed by the above-described steps.
- a thermal oxide film 18 is formed on the side wall of the silicon layer 5 serving as the floating gate electrode, and the leakage of the charge held in the silicon layer 5 is reduced.
- an oxidizing species penetrates into the interface between the silicon substrate 1, the silicon layers 5, 14 and the insulating layers 4, 6, 8 to form a parse beak.
- a silicon gate electrode 14 is formed on a gate oxide film 12 (11) having a uniform thickness.
- Gate oxide film 1 2 Since no parse beak occurs in (11), the voltage applied to the gate electrode is efficiently applied to the channel layer, and the driving capability of the MOS transistor is maintained.
- FIG. 3A shows an operation of writing information to a nonvolatile memory element.
- Ground the source region S apply 5 V to the drain region D, and apply a high voltage of 10 V to the control gate CG.
- the electrons transported from the source region S toward the drain region D become hot electrons due to a high electric field, and are injected from the channel region into the floating gate region FG. In this way, a program (writing) is performed.
- FIG. 3B illustrates the erasure of information.
- a voltage of 110 V is applied to the control gate CG, and a voltage of 5 V is applied to the source region S having the low concentration region 22.
- a high electric field is applied to the tunnel oxide film 4, and electrons of the floating gate FG pass through the tunnel oxide film 4 by FN tunneling and are extracted to the low concentration region 22 of the source region.
- the other drain region D is preferably in an electrically floating state (floating).
- a thermal oxide film was formed on the side wall of the floating gate electrode of the non-volatile memory element to allow the generation of a purge beak. No parse beak is generated in the low-voltage MOS transistor and high-voltage MOS transistor.
- 4A to 4D show a method for manufacturing a semiconductor device according to a second embodiment of the present invention.
- differences from the first embodiment will be mainly described.
- FIG. 4A shows a state similar to FIG. 1F.
- a silicon layer 5 serving as a floating gate, ONO films 6, 7, 8, and a silicon layer 14 serving as a control gate are formed on the tunnel oxide film 4, and a hard layer on the silicon layer 5 is formed thereon.
- the mask layer 15 is buttered using the resist pattern 16.
- a silicon layer 14 is formed on gate oxide films 12 and 11, and a hard mask layer 15 thereon is patterned using resist 1 and pattern 16 c
- the area AR 2 is covered with a resist mask 17, and in the areas AR 1 and AR 3, the hard mask 15 is used as an etching mask, and the silicon layer 14 and the ONO films 6 and 7 thereunder. , 8, Etch the silicon layer 5.
- the gate electrode structure of the nonvolatile memory element and the gate electrode of the high-voltage MOS transistor are patterned. After that, the resist mask 17 is removed.
- a thermal oxide film 18 is formed on the side wall of the gate electrode structure in an oxidizing atmosphere. Thermal oxide film is formed on the sidewalls of the gate electrodes of the non-volatile memory element and the high-voltage MOS transistor, and a purge beak occurs. In a region AR 2 where a low-voltage MOS transistor is formed, a thermal oxide film 18 is formed on the surface of the silicon layer 14. The surface of the silicon substrate 1 is covered with a gate oxide film 12 and a silicon layer 14 to prevent a parse beak below the good electrode.
- FIG. 4D shows the structure formed.
- a silicide layer 29 is formed on the silicon surface and covered with an interlayer insulating film 30.
- a W plug 31 penetrating through the interlayer insulating film is formed.
- the non-volatile memory element and the low-voltage MOS transistor have the same structure as in the first embodiment.
- the gate electrode side wall of the high voltage MOS transistor is covered with a thermal oxide film 18.
- a parse beak generated during the formation of the thermal oxide film is formed under the gate electrode end of the high-voltage MOS transistor, and the withstand voltage of the high-voltage MOS transistor is improved.
- a floating gate structure was formed using a silicon layer.
- a floating gate structure having charge storage capability can also be formed using an ONO film.
- FIG. 5A to 5E show a method for manufacturing a semiconductor device according to a third embodiment of the present invention.
- a thermal oxide film 6 with a thickness of 3 nm to 8 nm is formed on the surface of the silicon substrate 1 on which the STI 3 has been formed by thermal oxidation at 800 to 110 ° C. And then on it 65 0.
- an oxide film may be formed on the nitride film 7 by CVD.
- an ONO film is formed.
- LOCOS can be used instead of STI.
- a resist pattern 9 covering the region AR1 is formed. Using the resist pattern 9 as an etching mask, the ONO films 6, 7, and 8 on the regions AR2 and AR3 are etched. After that, the resist mask 9 is removed.
- a thermal oxide film 11 having a thickness of 5 nm to 500 nm is formed in a region AR3 by thermal oxidation at 800 ° C. to 110 ° C.
- the thermal oxide film in the area AR 2 is removed and a new thermal oxide film 12 having a thickness of 1.5 nm to 8 nm is formed in the area AR 2 by thermal oxidation at 700 ° C. to 110 ° C. I do.
- an amorphous silicon layer 14 functioning as a control gate electrode and a good electrode is formed on the ONO films 6, 7, 8 and the gate oxide films 11 and 12 to a thickness of 150 nm or more. Grow by 250 nm CVD. A plasma nitride film functioning as a hard mask is grown on the amorphous silicon layer 14 by plasma CVD with a thickness of 20 nm to 150 nm.
- a resist pattern 16 having a gate electrode shape is formed on the hard mask layer 15. Using the resist pattern 16 as an etching mask, the hard mask layer 15 is patterned into a gate electrode shape. After that, a step similar to the step shown in FIG. 1G is performed to pattern the gate electrode structure of the nonvolatile memory element. In the regions AR2 and AR3, the silicon layer 14 is left without being patterned.
- a thermal oxide film 18 is formed on the side wall of the gate electrode structure of the nonvolatile memory element. In regions AR 2 and AR 3, oxide film 18 is formed on the surface of silicon layer 14. The parse beak does not grow under the gut electrode.
- Steps similar to those shown in FIGS. 1I to 1N in the first embodiment are performed to form the structure of the nonvolatile memory element and the MOS transistor.
- FIG. 5E shows the configuration of each formed semiconductor element.
- a gate electrode structure is formed on the channel region by ONO films 6, 7, 8 and a floating gate electrode 14 of a silicon layer, and a side wall thereof is covered by an oxide film 18.
- a silicon layer is formed on gate oxide films 11 and 12. The gate electrode 14 is formed, and the thin oxide film 18 on the side wall is not formed.
- a bird's beak was not generated under the gate electrode of the high-voltage MOS transistor.
- a parse beak may be formed on the gate electrode of the high-voltage transistor as in the second embodiment.
- FIG. 6A to 6E show a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.
- points different from the third embodiment will be mainly described.
- FIG. 6A shows a state similar to FIG. 5C.
- a gate electrode-shaped resist pattern 16 is formed on the hard mask layer 15.
- the resist pattern 16 is used as an etching mask, and the hard mask 15 is etched.
- the area AR 2 is covered with a resist mask 17, the hard mask layer 15 is used as an etching mask in the areas AR 1 and AR 3, and the underlying gate electrode layer 14 is patterned. Thereafter, the resist mask 17 is removed.
- a protective oxide film 18 such as a thermal oxide film is formed on the side wall of the gate electrode structure.
- oxide film 18 is formed on silicon layer 14. There is no parse beak below the gate electrode.
- a resist mask exposing only the region AR1 is formed, and ions are implanted into the source-drain region of the nonvolatile memory element.
- the regions AR 1 and AR 3 are covered with a resist mask 23, and the silicon layer 14 is etched in the region AR 2 using the hard mask 15 as an etching mask.
- the gate electrode 14 is patterned in the area AR2. Thereafter, the same steps as those shown in FIGS. 1K to 1N are performed to create the structure of the nonvolatile memory element and the MOS transistor.
- FIG. 6E shows the configuration of the formed semiconductor device.
- a protective oxide film 18 is formed on the gate electrode structure of the nonvolatile memory element and on the side wall of the gate electrode of the high-voltage MOS transistor. With the formation of the protective oxide film, a parse beak is formed below the gate electrode. The parse beak of the high-voltage MOS transistor improves the breakdown voltage of the gate electrode structure.
- 7A to 7C show a configuration of a nonvolatile memory element having a single-layer gate electrode in which a control gate electrode is formed in a substrate.
- 7A is a plan view
- FIGS. 7B and 7C are cross-sectional views taken along the dashed-dotted lines MB-WB and -C in FIG. 7A.
- a nonvolatile memory element is formed using two regions.
- a source region S and a drain region D are formed on both sides of the floating gate electrode FG.
- the lower area AR 1b in the figure is a control gate area CG composed of a low-resistance area heavily doped with impurities.
- the floating gate electrode FG traverses the region AR1a, extends over the region ARib, and extends over a large area of the control gate region.
- FIG. 7B shows a transistor structure formed in the region AR1a.
- a low-concentration region is formed around the high-concentration region to improve the erasing operation.
- FIG. 7C shows a configuration of a floating gate electrode FG extending from the transistor structure onto the control gate region.
- a control gate CG is formed by a high-concentration region in an active region defined by an element isolation region LOCOS formed by a local oxide film.
- the floating gate FG and the control gate CG face each other via an insulating film, and by applying a voltage to the control gate, it is possible to apply a voltage to the channel region of the transistor region via the floating gate FG. it can.
- 7D and 7E are cross-sectional views illustrating a program operation.
- 0 V is applied to the source region S
- 5 V is applied to the drain region D.
- a voltage of 10 V is applied to the control gate region CG.
- electrons from the source region S to the drain region D become a hot electron due to a strong electric field, and are injected into the floating gate FG. Since the floating gate FG extends from the transistor region to above the control gate, the entire floating gate FG is charged as shown in FIG. 7E.
- FIGS. 7F and 7G show the erase operation.
- a high voltage of 15 V is applied to the source region S, and the control gate CG is set to 0 V.
- the drain region D is also set to 0 V.
- Control gate The voltage of CG controls the potential of the floating gate.
- the electrons held in FG are attracted by a high electric field and float. Move from gate FG to low concentration region of source region S by FN tosine ring.
- the charge on the floating gate FG is erased.
- 8A to 8E show a method of manufacturing a semiconductor device using the above-described single-layer gate electrode as a nonvolatile memory element according to the fifth embodiment.
- a tunnel oxide film 4 for a nonvolatile memory element As shown in FIG. 8A, on the surface of the silicon substrate 1 on which the STI 3 is formed, a tunnel oxide film 4 for a nonvolatile memory element, a gate oxide film 12 for a low-voltage MOS transistor, and a high-voltage MOS transistor A gate oxide film 11 is formed, and a silicon layer 41 is formed thereon.
- the silicon layer 41 constitutes a floating gate of the nonvolatile memory element and constitutes a gate electrode of the MOS transistor.
- LOCO S may be used instead of STI.
- a hard mask layer 15 such as silicon nitride is formed on the silicon layer 41, and a gate electrode-shaped resist pattern 16 is formed thereon.
- This state corresponds to a state in which the ONO films 6, 7, and 8 are replaced with the tunnel oxide film 4 in the state of FIG. 5C.
- the regions AR 2 and AR 3 are covered with a resist mask 17, and in the region AR 1, the silicon layer 41 is etched using the hard mask 15 as an etching mask. After that, the resist mask 17 is removed.
- a protective oxide film 18 is formed on the side wall of the patterned silicon layer 41 in the region AR1.
- a protective oxide film 18 is formed on the surface of silicon layer 41.
- ion implantation is performed on the source Z drain region and the control gate region in the nonvolatile memory element region, and the silicon layers 41 in the regions AR 2 and AR 3 are patterned to form the source Z drain. Ion implantation is performed on the extension portion of the region.
- a silicon oxide film is deposited on the substrate surface, the gate electrode region in region AR1 is covered with a mask, and anisotropic etching is performed.
- a side wall spacer 26 of a silicon oxide film is formed.
- a silicon oxide film 26X covering the floating gate electrode remains. After that, the high concentration source / drain regions are formed in the regions AR2 and AR3.
- a silicide layer 29 is formed on the source Z drain region and the exposed gate electrode, the gate electrode structure is covered with an interlayer insulating film 30, and a W plug 31 is formed in the contact hole.
- Embed A semiconductor device including a nonvolatile memory element having a single-layer gate electrode, a low-voltage MOS transistor, and a high-voltage MOS transistor is completed. No parse beak is formed in the MOS transistor, and high drive capability is maintained. The alignment of the gate electrode mask is performed once.
- a parse beak may be formed on the gate electrode of the high-voltage transistor. (Example 6)
- FIG. 9A to 9D show a method for manufacturing a semiconductor device according to a sixth embodiment of the present invention.
- a hard mask pattern 15 is formed on the silicon layer 41, the second area AR2 is covered with a resist mask 17, and the hard mask pattern 15 is formed in the areas AR1 and AR3.
- the metal mask 15 as an etching mask, the silicon layer 41 is etched. After that, the resist mask 17 is removed.
- a protective oxide film 18 is formed on the side wall of the silicon layer 41 patterned in the shape of the gate electrode.
- the silicon layer 41 has not been patterned yet, and the oxide film 18 is formed on the surface of the silicon layer 41.
- ion implantation for the non-volatile element which is performed in the regions AR2 and AR3 using a resist mask, is performed.
- the regions AR 1 and AR 3 are covered with a resist mask 23, and in the region AR 2, the silicon layer 41 is etched using the hard mask 15 as an etching mask. Thereafter, the resist mask 23 is removed.
- the area AR1 is covered with a resist mask, and ions are implanted into the extensions of the soft and drain areas in the areas AR2 and AR3.
- a silicide layer 29 is formed on the exposed source Z drain region and on the exposed gate electrode, and is covered with an interlayer insulating film 30.
- a contact hole is formed in the interlayer insulating film 30, and a W plug 31 is formed.
- a bird's-eye beneath the gate electrode of the high-voltage MOS transistor is used. And a breakdown voltage of the gate electrode is improved. Other points are the same as in the fifth embodiment.
- a semiconductor device including a nonvolatile memory element such as a system LSI and another type of semiconductor element can be manufactured.
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical Kinetics & Catalysis (AREA)
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Abstract
Description
Claims
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
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CNB038230267A CN100429790C (zh) | 2003-03-19 | 2003-03-19 | 半导体器件及其制造方法 |
JP2004569583A JP4721710B2 (ja) | 2003-03-19 | 2003-03-19 | 半導体装置の製造方法 |
PCT/JP2003/003382 WO2004084314A1 (ja) | 2003-03-19 | 2003-03-19 | 半導体装置とその製造方法 |
TW092108946A TWI223898B (en) | 2003-03-19 | 2003-04-17 | Semiconductor device and the manufacturing method of the same |
US11/145,214 US20050224864A1 (en) | 2003-03-19 | 2005-06-06 | Semiconductor device and its manufacture method |
US12/640,067 US20100096684A1 (en) | 2003-03-19 | 2009-12-17 | Semiconductor device and its manufacture method |
US13/026,736 US8304310B2 (en) | 2003-03-19 | 2011-02-14 | Manufacture method of semiconductor device |
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PCT/JP2003/003382 WO2004084314A1 (ja) | 2003-03-19 | 2003-03-19 | 半導体装置とその製造方法 |
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US11/145,214 Continuation US20050224864A1 (en) | 2003-03-19 | 2005-06-06 | Semiconductor device and its manufacture method |
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US (3) | US20050224864A1 (ja) |
JP (1) | JP4721710B2 (ja) |
CN (1) | CN100429790C (ja) |
TW (1) | TWI223898B (ja) |
WO (1) | WO2004084314A1 (ja) |
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Also Published As
Publication number | Publication date |
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US20110136312A1 (en) | 2011-06-09 |
US20050224864A1 (en) | 2005-10-13 |
JP4721710B2 (ja) | 2011-07-13 |
CN100429790C (zh) | 2008-10-29 |
TW200419813A (en) | 2004-10-01 |
US8304310B2 (en) | 2012-11-06 |
TWI223898B (en) | 2004-11-11 |
JPWO2004084314A1 (ja) | 2006-06-29 |
US20100096684A1 (en) | 2010-04-22 |
CN1685524A (zh) | 2005-10-19 |
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