US20050224864A1 - Semiconductor device and its manufacture method - Google Patents

Semiconductor device and its manufacture method Download PDF

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US20050224864A1
US20050224864A1 US11/145,214 US14521405A US2005224864A1 US 20050224864 A1 US20050224864 A1 US 20050224864A1 US 14521405 A US14521405 A US 14521405A US 2005224864 A1 US2005224864 A1 US 2005224864A1
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area
gate
film
gate electrode
semiconductor device
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Hiroshi Hashimoto
Kazuhiko Takada
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Fujitsu Semiconductor Ltd
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Fujitsu Ltd
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Priority to US12/640,067 priority Critical patent/US20100096684A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
    • H01L29/7885—Hot carrier injection from the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/44—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a control gate layer also being used as part of the peripheral transistor

Definitions

  • the present invention relates to a semiconductor device, and its manufacture method, and more particularly to a semiconductor device having a memory circuit of, for example, non-volatile memory cell transistors and a peripheral circuit of logical cell transistors, and to its manufacture method.
  • an electrically erasable non-volatile memory is a structure having a lamination of a floating gate structure having a charge retention function and a control gate structure for applying an electric field to a channel via the floating gate structure, stacked on a semiconductor region formed with the channel.
  • the floating gate structure includes a silicon layer insulated with an insulating layer or layers, or a lamination of an oxide film, a nitride film and an oxide film, forming a nitride film interface having a charge storage function.
  • Programming is performed by selectively injecting electrons into the floating gate.
  • a predetermined voltage is applied to the control gate structure, the conductivity of a channel below the floating gate changes, depending on whether or not there are charges in the floating gate structure. Hence, written information can be read. By draining electrons from the floating gate structure, written information can be erased.
  • a floating electrode is formed by a silicon layer sandwiched between insulating layers, and side walls are thermally oxidized.
  • a floating gate electrode covered with an insulating film of good quality such as a thermally oxidized film improves the charge retention performance.
  • the charge retention performance of a floating gate structure made of a lamination of oxide film-nitride film-oxide film can also be improved by covering the side walls with an oxide film or the like.
  • a semiconductor integrated circuit such as a system LSI of high integration degree is structured having a plurality type of semiconductor elements such as non-volatile memories, high voltage insulated gate field effect (abbreviated to MOS) transistors for driving them and low voltage MOS transistors for logical circuits.
  • MOS high voltage insulated gate field effect
  • a logical circuit low voltage MOS transistor has a short gate length and a thin gate insulating film in order to raise its operation speed.
  • Manufacture processes for a semiconductor integrated circuit are designed to use in common as many same processes as possible for the manufacture of a plurality type of semiconductor elements.
  • the gate electrode of a MOS transistor is made of the same silicon layer as that of the control gate electrode of a non-volatile memory cell.
  • the side walls of the gate electrode of a MOS transistor are also thermally oxidized.
  • oxidizing species enter the interface between a silicon substrate and an upper insulating film and the interface between a silicon layer and an insulating film so that an oxidized region called a bird's beak is formed.
  • a low voltage MOS transistor has a short gate length and a thin gate insulating film. As a birds' beak is formed at the edge portions of a gate insulating film, the gate insulating film becomes thick under the edge portions of the gate electrode so that a drive current of the MOS transistor is lowered.
  • a laminated gate structure of a non-volatile memory cell and a single layer gate structure of a MOS transistor are patterned by using different masks and different processes. Therefore, mask alignment margins are increased. If a first mask alignment margin is 0.2 ⁇ m, a second mask alignment margin is increased to 0.28 ⁇ m. An increase in the mask alignment margin hinders high integration.
  • Japanese Patent Laid-open Publication No. HEI-10-223782 proposes a non-volatile memory cell whose control gate electrode is made of a diffusion region in a substrate.
  • a low resistance region functioning as a control gate electrode is formed in a semiconductor substrate, and a floating gate electrode is formed extending from an area above a channel region of the memory transistor to an area above the low resistance region functioning as the control gate electrode.
  • the control gate electrode can be formed by the same process as that for the source/drain regions of the memory transistor; so that the manufacture processes for a non-volatile memory can be simplified.
  • An object of the present invention is to provide a semiconductor device having memory cells with a high data retention ability and field effect transistors having an insulating film realizing a high drive current.
  • Another object of the present invention is to provide a semiconductor device capable of enhancing a data retention ability of a non-volatile memory cell and preventing lowering of the drive current of a field effect transistor having an insulated gate in a logical circuit.
  • Another object of the present invention is to provide a method of manufacturing the semiconductor device as described above.
  • Another object of the present invention is to provide a method of manufacturing at a high precision the semiconductor device as described above.
  • Still another object of the present invention is to provide a method of manufacturing efficiently the semiconductor device as described above.
  • a semiconductor device comprising: a semiconductor substrate having a first element area and a second element area on a surface thereof; a first transistor of a double gate type having a floating gate and a control gate whose side walls are covered with a thermally oxidized film, and having gate bird's beaks having a first length, formed in the first element area; and a second transistor having a gate electrode having gate bird's beaks having a second length shorter than the first length, formed in the second element area, wherein the first transistor operates as a non-volatile memory cell capable of electrically writing and erasing data and the second transistor operates as a logical circuit element.
  • a manufacture method for a semiconductor device comprising steps of: (a) forming an element separation region in a semiconductor substrate to define first and second areas; (b) forming a floating gate structure lamination layer on the first area; (c) forming a lamination of a gate electrode conductive layer and a masking insulating layer above the floating gate structure lamination layer and above the second area; (d) pattering the masking insulating film in a gate electrode shape; (e) masking the second area, and by using the masking insulating layer as an etching mask, etching the gate electrode conductive layer and the floating gate structure lamination layer in the first area to pattern a floating gate structure and a control gate structure; (f) forming an oxide film on side walls of at least the floating gate structure; and (g) masking the first area, and by using the masking insulating layer as an etching mask, etching the gate electrode conductive layer in the second area to pattern an insulated gate structure.
  • FIGS. 1A to 1 N are cross sectional views illustrating main processes of a semiconductor device manufacture method according to a first embodiment of the present invention.
  • FIG. 2 is an enlarged cross sectional view showing the structure of a gate electrode formed by the first embodiment method.
  • FIGS. 3A and 3B are diagrams illustrating an operation of a non-volatile memory cell.
  • FIGS. 4A to 4 D are cross sectional views illustrating main processes of a semiconductor device manufacture method according to a second embodiment of the present invention.
  • FIGS. 5A to 5 E are cross sectional views illustrating main processes of a semiconductor device manufacture method according to a third embodiment of the present invention.
  • FIGS. 6A to 6 E are cross sectional views illustrating main processes of a semiconductor device manufacture method according to a fourth embodiment of the present invention.
  • FIGS. 7A to 7 G are a plan view and cross sectional views illustratively showing the structure and operation of a non-volatile semiconductor memory cell having a single layer gate electrode.
  • FIGS. 8A to 8 E are cross sectional views illustrating main processes of a semiconductor device manufacture method according to a fifth embodiment of the present invention.
  • FIGS. 9A to 9 D are cross sectional views illustrating main processes of a semiconductor device manufacture method according to a sixth embodiment of the present invention.
  • An electrically erasable non-volatile semiconductor memory uses high voltage for programming and erasure. If a programming circuit and an erase circuit are integrated with a non-volatile memory circuit, high voltage field effect (abbreviated to MOS) transistors are required to be integrated. A logical circuit is made of low voltage MOS transistors for reducing the power dissipation. If a non-volatile memory circuit and a logical circuit are integrated, low voltage MOS transistors are required to be integrated.
  • FIGS. 1A to 1 N are cross sectional views illustrating a semiconductor device manufacture method according to the first embodiment of the present invention.
  • a shallow trench 2 is formed in a principal surface of a semiconductor substrate 1 such as a silicon substrate, an insulating film is buried in the trench and the insulating film on the substrate surface is removed to form a shallow trench isolation (STI) 3 .
  • the isolation region may also be formed by local oxidation of silicon (LOCOS).
  • Areas AR 1 , AR 2 and AR 3 surrounded by STI are defined.
  • a non-volatile memory cell is formed
  • a low voltage MOS transistor of a logical circuit is formed
  • a high voltage MOS transistor is formed which controls non-volatile memory cells.
  • a thermally oxidized film 4 is formed to a thickness of 6 nm to 12 nm in an oxidizing atmosphere by heating the semiconductor substrate to 800° C. to 1100° C.
  • This thermally oxidized film 4 constitutes a tunneling oxide film of a non-volatile memory cell.
  • an amorphous silicon film 5 is deposited on the tunneling oxide film 4 to a thickness of 50 nm to 100 nm by chemical vapor deposition (CVD).
  • the amorphous silicon film 5 is doped with n-type impurities, phosphorus, at 1 ⁇ 10 20 cm ⁇ 3 to 3 ⁇ 10 21 cm ⁇ 3 and functions as a floating gate electrode of the non-volatile memory cell. Phosphorus ions may be implanted after a non-doped amorphous silicon film is formed.
  • a silicon oxide film 6 having a thickness of 4 nm to 8 nm is formed by CVD at a temperature of 700° C. to 800° C. and a silicon nitride film 7 having a thickness of 5 nm to 10 nm is formed by CVD at a temperature of 650° C. to 800° C.
  • a thermally oxidized film 8 having a thickness of 3 nm to 10 nm is formed on the surface of the silicon nitride film 7 in an oxidizing atmosphere at 900° C. to 1000° C.
  • the above-described and subsequent heating processes change the amorphous silicon film to a polysilicon film. In this manner, a lamination of an oxide film—a nitride film—an oxide film (ONO film) is formed on the silicon film 5 .
  • the surface of the area AR 1 is covered with a resist mask 9 , and the ONO film, silicon film 5 and tunneling oxide film 4 in the areas AR 2 and AR 3 are etched and removed.
  • the silicon surface is exposed in the areas AR 2 and AR 3 .
  • the resist mask 9 is thereafter removed.
  • a thermally oxidized film 11 having a thickness of 10 nm to 50 nm is formed at 800° C. to 1100° C.
  • This thermally oxidized film 11 which may be thickened by the following thermal oxidation constitutes a gate oxide film of a high voltage MOS transistor.
  • the thermally oxidized film in the area AR 2 is etched and removed.
  • thermal oxidation at a temperature of 700° C. to 1100° C. is performed to form a thermally oxidized film 12 having a thickness of 1.5 nm to 8 nm on the surface of the area AR 2 .
  • This thermally oxidized film 12 constitutes a gate oxide film of a low voltage MOS transistor.
  • a thin gate oxide film 12 suitable for the low voltage MOS transistor is formed in the area AR 2 and a thick oxide film 11 suitable for the high voltage MOS transistor is formed in the area AR 3 .
  • an amorphous silicon film 14 is formed on the surface of the silicon substrate by CVD.
  • the amorphous silicon film is doped with n-type impurities, phosphorus, at 5 ⁇ 10 20 cm ⁇ 3 to 5 ⁇ 10 21 cm ⁇ 3 and has a thickness of 150 nm to 250 nm.
  • Phosphorus ions may be implanted after a non-doped amorphous silicon film is formed.
  • a tungsten silicide (WSi) film may be grown on the amorphous silicon film by CVD to a thickness of 100 nm to 200 nm.
  • a plasma-enhanced CVD nitride film 15 as a hard mask layer is grown to a thickness of 20 nm to 150 nm.
  • a hard mask layer of a plasma-enhanced CVD oxynitride film, a plasma-enhanced CVD oxide film or the like may be used. Formed in this manner is a lamination of a conductive layer as a gate electrode and an upper hard mask layer.
  • a resist pattern 16 having each gate electrode shape is formed on the hard mask layer 15 .
  • the underlying hard mask layer 15 is etched to pattern the hard mask layer 15 in the gate electrode shape.
  • the resist pattern 16 is thereafter removed.
  • the areas AR 2 and AR 3 are covered with a resist mask 17 , and by using the hard mask 15 as an etching mask, the silicon layer 14 , ONO film 6 , 7 , 8 and silicon layer 5 in the area AR 1 are etched to pattern the gate electrode of the non-volatile memory cell.
  • the resist mask 17 is thereafter removed.
  • the substrate is heated to 800° C. to 900° C. in an oxidizing atmosphere to form a thermally oxidized film 18 having a thickness of 3 nm to 10 nm on the side walls of exposed silicon layers. While the side walls of the silicon layers 5 and 14 are thermally oxidized, oxidizing species enter the interfaces between the silicon substrate 1 , silicon layers 5 and 14 and insulating layers so that bird's beaks are formed at the edge portions of the insulating film.
  • an oxide film 18 is formed on the surface of the silicon layer 14 . Since the surface of the silicon substrate 1 is covered with the gate oxide films 11 and 12 and silicon film 14 , it is not oxidized.
  • FIG. 2 is an enlarged view of the gate electrode structures of the non-volatile memory cell and MOS transistor. Although the bird's beaks are formed at the edge portions of the oxide films 4 , 6 and 8 , no bird's beak is formed at the oxide film 12 ( 11 ).
  • a low impurity concentration n-type region 21 is formed in the area AR 1 by phosphorus ion implantation at an acceleration energy of 30 keV to 70 keV and a dose of 1 ⁇ 10 14 cm ⁇ 3 to 1 ⁇ 10 15 cm ⁇ 2 .
  • the low impurity concentration n-type region 21 is formed only on one side of the gate electrode, it may be formed on both sides.
  • a high impurity concentration n-type region 22 is formed by implanting arsenic ions at an acceleration energy of 30 keV to 60 keV and a dose of 2 ⁇ 10 15 cm ⁇ 2 to 7 ⁇ 10 15 cm ⁇ 2 .
  • the high impurity concentration source/drain regions 22 are formed on both sides of the gate electrode and the low impurity concentration n-type region 21 is formed surrounding at least one of the source/drain regions 22 .
  • the low impurity concentration n-type region 21 exhibits the function of raising an efficiency of draining charges from the silicon layer 5 .
  • the area AR 1 is covered with a resist mask 23 , and by using the hard mask 15 as an etching mask, the silicon layer 14 in the areas AR 2 and AR 3 is etched to pattern the gate electrodes in the areas AR 2 and AR 3 .
  • the resist mask 23 is thereafter removed.
  • ion implantation is performed to form low impurity concentration extensions 25 of source/drain regions.
  • p- and n-channel MOS transistor regions are selectively exposed by using masks to separately implanting p- and n-type impurity ions.
  • an insulating film such as a silicon oxide film is deposited on the surface of the silicon substrate by CVD, and anisotropic etching such as reactive ion etching (RIE) is performed to remove the insulating film on the flat surface and form side wall spacers 26 on the side walls of the gate structures. If the hard mask layer 15 is left on the gate electrode, it is etched and removed.
  • anisotropic etching such as reactive ion etching (RIE) is performed to remove the insulating film on the flat surface and form side wall spacers 26 on the side walls of the gate structures.
  • the area AR 1 is covered with a resist mask 27 , and n-type impurity ions are implanted at a high impurity concentration into the areas AR 2 and AR 3 to form high impurity concentration source/drain regions 28 .
  • p- and n-channel regions are selectively exposed by using masks to separately implanting p- and n-type impurity ions.
  • the resist mask 27 is thereafter removed.
  • Implanted impurity ions are activated by an annealing process. These heating processes change the silicon layer 14 to a polysilicon layer.
  • a Co film is deposited on the substrate surface and a CoSi film 29 is formed on each of the silicon surfaces through silicidation. Unreacted Co is removed. Thereafter, an interlayer insulating film 30 is formed on the substrate surface and its surface is planarized by chemical mechanical polishing (CMP). Thereafter, contact holes are formed by using a resist mask. A barrier metal layer and a W layer are deposited, being filled in the contact holes. The metal layers on the flat surface are removed by CMP to form W plugs 31 .
  • CMP chemical mechanical polishing
  • non-volatile memory cells are formed in the area AR 1 , low voltage MOS transistors are formed in the area AR 2 , and high voltage MOS transistors are formed in the area AR 3 .
  • High drive performance of MOS transistors is retained because bird's beaks are prevented from being formed.
  • a position alignment margin is small since the gate electrode of each semiconductor device is formed by a single mask process.
  • FIG. 2 is an enlarged view of the gate electrode of the non-volatile memory cell and the gate electrode of the MOS transistor formed by the above-described processes.
  • the thermally oxidized film 18 is formed on the side walls of the silicon layer 5 as the floating gate electrode of a non-volatile memory cell, so that leak of charges in the silicon layer 5 can be reduced. While the thermally oxidized film 18 is formed, oxidizing species enter the interfaces between the silicon substrate 1 , silicon layers 5 and 14 and insulating layers 4 , 6 and 8 , and bird's beaks are formed.
  • the silicon gate electrode 14 is formed on the gate oxide film 12 ( 11 ) of uniform thickness. Since no bird's beak is formed at the gate oxide film 12 ( 11 ), a voltage applied to the gate electrode is efficiently applied to the channel so that the drive performance of the MOS transistor can be retained. There may be some possibility of allowing generation of weak bird's beaks under the gate electrode of logical MOS transistor, such bird's beaks are shorter than the bird's beaks of the non-volatile memory cell, and will not appreciably affect the performance of the logical MOS transistor.
  • FIG. 3A illustrates a write operation of writing information in a non-volatile memory cell.
  • a source region S is grounded, 5 V is applied to a drain region D, and a high voltage of 10 V is applied to a control gate CG. Electrons transferred from the source region S toward the drain region D become hot electrons due to a high electric field, and these electrons are injected from the channel into the a floating gate region FG. Programming (write operation) is performed in this manner.
  • FIG. 3B illustrates an erase operation of erasing information in the memory cell.
  • a voltage of ⁇ 10 V is applied to the control gate CG, and a voltage of 5 V is applied to the source region S having the low impurity concentration region 22 .
  • As a high electric field is applied to the tunneling oxide film 4 , electrons in the floating gate FG FN-tunnel through the tunneling oxide film 4 and are drained into the low concentration region 22 of the source region.
  • the other drain region D is preferably in an electrically floating state.
  • the thermally oxidized film is formed on the side walls of the floating gate electrode of a non-volatile memory cell and bird's beaks are allowed to be formed. No bird's beak is formed in the low voltage MOS transistor and high voltage MOS transistor.
  • the operation of a high voltage MOS transistor is not hindered by bird's beaks at the edge portions of a gate electrode, and bird's beaks provide a function of raising a breakdown voltage.
  • FIGS. 4A to 4 D illustrate a semiconductor device manufacture method according to the second embodiment of the present invention. Description will be made mainly on those points different from the first embodiment.
  • FIG. 4A shows the state similar to FIG. 1F .
  • the silicon layer 5 , ONO film 6 , 7 , 8 and silicon layer 14 as the control gate.
  • the hard mask layer 15 on the silicon layer is patterned by using the resist pattern 16 .
  • the silicon layer 14 on which the hard mask layer 15 is patterned by using the resist pattern 16 is the silicon layer 14 on which the hard mask layer 15 is patterned by using the resist pattern 16 .
  • the area AR 2 is covered with a resist mask 17 , and by using the hard mask 15 as an etching mask, the underlying silicon layer 14 , ONO film 6 , 7 , 8 and silicon layer 5 in the areas AR 1 and AR 3 are etched.
  • the gate electrode structure of a non-volatile memory cell and the gate electrode of a high voltage MOS transistor are therefore patterned.
  • the resist mask 17 is thereafter removed.
  • a thermally oxidized film 18 is formed on the side walls of the gate electrode structure in an oxidizing atmosphere.
  • the thermally oxidized film is therefore formed on the side walls of the gate electrodes of a non-volatile memory cell and a high voltage MOS transistor, and bird's beaks appear.
  • the thermally oxidized film 18 is formed on the surface of the silicon layer 14 . Since the surface of the silicon substrate 1 is covered with the gate oxide film 12 and silicon layer 14 , it is possible to prevent bird's beaks from being formed under the gate electrode.
  • FIG. 4D shows the finished structure. Formed on a silicon surface is a silicide layer 29 , and the substrate is covered with an interlayer insulating film 30 . W plugs 31 are formed through the interlayer insulating film.
  • the non-volatile memory cell and low voltage MOS transistor have the structure similar to that of the first embodiment.
  • the side walls of the gate electrode of a high voltage MOS transistor is covered with the thermally oxidized film 18 . Bird's beaks are formed under the edge portions of the gate electrode of a high voltage MOS transistor while the thermally oxidized film is formed, so that a breakdown voltage of the high voltage MOS transistor is raised.
  • the floating gate structure is made of a silicon layer.
  • the floating gate structure with the charge retention function may also be made of an ONO film.
  • FIGS. 5A to 5 E illustrate a semiconductor device manufacture method according to the third embodiment of the present invention.
  • a thermally oxidized film 6 having a thickness of 3 nm to 8 nm is formed through thermal oxidation at 800° C. to 1100° C.
  • a nitride film 7 having a thickness of 5 nm to 15 nm is formed by CVD at 650° C. to 800° C.
  • a thermally oxidized film 8 having a thickness of 3 nm to 10 nm is formed through thermal oxidation at 900° C. to 1000° C.
  • An oxide film may be formed on the nitride film 7 by CVD.
  • An ONO film is therefore formed. Similar to the above-described embodiments, LOCOS may be used in place of STI.
  • the area AR 1 is covered with a resist pattern 9 .
  • the resist pattern 9 as an etching mask, the ONO film 6 , 7 , 8 in the areas AR 2 and AR 3 is etched.
  • the resist mask 9 is thereafter removed.
  • a thermally oxidized film 11 having a thickness of 5 nm to 50 nm is formed in the area AR 3 through thermal oxidation at 800° C. to 1100° C.
  • the thermally oxidized film in the area AR 2 is removed and a thermally oxidized film 12 having a thickness of 1.5 nm to 8 nm is newly formed in the area AR 2 through thermal oxidation at 700° C. to 1100° C.
  • an amorphous silicon layer 14 is grown by CVD on the ONO film 6 , 7 , 8 and gate oxide films 11 and 12 to a thickness of 150 nm to 250 nm, the amorphous silicon layer functioning as a control gate electrode and gate electrodes.
  • a plasma-enhanced CVD nitride film functioning as a hard mask is grown to a thickness of 20 nm to 150 nm by plasma-enhanced CVD.
  • a resist pattern 16 having each gate electrode shape is formed on the hard mask layer 15 .
  • the hard mask layer 15 is patterned in the gate electrode shape.
  • a process similar to the process shown in FIG. 1G is executed to pattern the gate electrode structure of a non-volatile memory cell.
  • the silicon layer 14 in the areas AR 2 and AR 3 is not patterned but left as it is.
  • a thermally oxidized film 18 is formed on the side walls of the gate electrode structure of the non-volatile memory cell. In the areas AR 2 and AR 3 , the oxide layer 18 is formed on the surface of the silicon layer 14 . Bird's beaks are not formed under the gate electrodes.
  • Processes similar to those shown in FIGS. 1I to 1 N of the first embodiment are executed to form the non-volatile memory cell structure and the MOS transistor structures.
  • FIG. 5E shows the finished structure.
  • the non-volatile memory cell has the gate electrode structure above the channel region, constituted of the ONO film 6 , 7 , 8 and floating gate electrode 14 made of a silicon layer, the side walls of the gate electrode structure being covered with the oxide film 18 .
  • the gate electrode 14 made of a silicon layer is formed on the gate oxide films 11 and 12 , and the thin oxide film 18 is not formed on the side walls.
  • no bird's beak is formed under the gate electrode of the high voltage MOS transistor. Similar to the second embodiment, bird's beaks may be formed under the gate electrode of the high voltage MOS transistor.
  • FIGS. 6A to 6 E illustrate a semiconductor device manufacture method according to the fourth embodiment of the present invention. Description will be made mainly on those points different from the first embodiment.
  • FIG. 6A shows the state similar to FIG. 5C .
  • Formed on the hard mask layer 15 is a resist pattern 16 having each gate electrode shape.
  • the resist pattern 16 is etched.
  • the area AR 2 is covered with a resist mask 17 , and by using the hard mask layer 15 as an etching mask, the underlying gate electrode layer 14 in the areas AR 1 and AR 3 is patterned.
  • the resist mask 17 is thereafter removed.
  • a protective oxide film 18 such as a thermally oxidized film is formed on the side walls of gate electrode structures.
  • the oxide film 18 is formed on the silicon layer 14 . No bird's beak is formed under the gate electrode.
  • a resist mask exposing only the area AR 1 is formed, and impurity ions are implanted in source/drain regions of the non-volatile memory cell.
  • the areas AR 1 and AR 3 are covered with a resist mask 23 , and by using the hard mask 15 as an etching mask, the silicon layer 14 in the area AR 2 is etched to pattern the gate electrode 14 .
  • FIG. 6E shows the finished structure.
  • the protective oxide film 18 is formed on the side walls of the gate electrode structure of the non-volatile memory cell and on the side walls of the high voltage MOS transistor. While the protective oxide film is formed, bird's beaks are formed under the gate electrode. The bird's beaks of the high voltage MOS transistor improve the breakdown voltage of the gate electrode structure.
  • FIGS. 7A to 7 C show the structure of a non-volatile memory cell having a single layer gate electrode wherein a control gate electrode is formed in a substrate.
  • FIG. 7A is a plan view and FIGS. 7B and 7C are cross sectional views taken along one-dot chain lines VIIB-VIIB and VIIC-VIIC in FIG. 7A , respectively.
  • a non-volatile memory cell is formed by using two areas.
  • a source region S and a drain region D are formed on both sides of a floating gate electrode FG.
  • An area AR 1 b in a lower portion of FIG. 7A is a control gate region CG made of a low resistance region doped with impurities at a high impurity concentration.
  • the floating gate electrode FG traverses the area AR 1 a and extends above the area AR 1 b in a broad area of the control gate region.
  • FIG. 7B shows the transistor structure formed in the area AR 1 a .
  • the source region S has a low impurity concentration region surrounding a high impurity concentration region to improve the erase operation.
  • FIG. 7C shows the structure of the floating gate electrode FG extending from the transistor structure to the control gate region.
  • the control gate CG is made of a high impurity concentration region in an active region defined by an isolation region LOCOS made of a locally oxidized film.
  • the floating gate FG and control gate CG confront each other via an insulating film. As voltage is applied to the control gate, voltage can be applied to the channel region in the transistor area via the floating gate FG.
  • FIGS. 7D and 7E are cross sectional views illustrating a programming operation.
  • O V is applied to the source region S
  • 5 V is applied to the drain region D.
  • a voltage of 10 V is applied to the control gate region CG. Electrons transferred from the source region S toward the drain region D in the transistor structure become hot electrons due to a high electric field and injected into the floating gate FG. Since the floating gate FG extends from the transistor area to an area above the control gate, the whole floating gate FG is charged as shown in FIG. 7E .
  • FIGS. 7F and 7G illustrate an erase operation.
  • a high voltage of 15 V is applied to the source region S, and 0 V is applied to the control gate CG.
  • the drain region D is also set to 0 V.
  • Voltage at the control gate CG controls the potential of the floating gate. Electrons in the floating gate FG are drained by the high electric field and move through tunneling from the floating gate FG to the low impurity concentration region of the source region S. Charges in the floating gate FG are thereby drained.
  • FIGS. 8A to 8 E illustrate a semiconductor device manufacture method according to the fifth embodiment of the present invention, wherein the single layer gate electrode is used for a non-volatile memory cell.
  • a tunneling oxide film 4 for a non-volatile memory cell As shown in FIG. 8A , on the surface of a silicon substrate 1 with STI 3 , a tunneling oxide film 4 for a non-volatile memory cell, a gate oxide film 12 for a low voltage MOS transistor and a gate oxide film 11 for a high voltage MOS transistor are formed, and a silicon layer 41 is formed on these films.
  • the silicon layer constitutes the floating gates of non-volatile memory cells and the gate electrodes of MOS transistors. LOCOS may be used in place of STI.
  • a hard mask layer 15 such as silicon nitride is formed on the silicon layer 41 , and a resist pattern 16 having each gate electrode shape is formed on the hard mask layer. This state corresponds to the state shown in FIG. 5C with the ONO film 6 , 7 , 8 being replaced with the tunneling oxide film 4 .
  • the resist pattern 16 As an etching mask, the hard mask 15 is etched. The resist pattern 16 is thereafter removed.
  • the areas AR 2 and AR 3 are covered with a resist mask 17 , and by using the hard mask 15 as an etching mask, the silicon layer 41 in the area AR 1 is etched. The resist mask 17 is thereafter removed.
  • a protective oxide film 18 is formed on the side walls of the patterned silicon layer 41 in the area AR 1 .
  • the protective oxide film 18 is formed on the surface of the silicon layer 41 .
  • ion implantation for source/drain regions and a control gate region is performed in the non-volatile memory cell area, the silicon layer 41 in the areas AR 2 and AR 3 is patterned, and ion implantation for extension regions of source/drain regions is performed.
  • a silicon oxide film is deposited on the substrate surface.
  • the gate electrode area in the area AR 1 is covered with a mask and anisotropic etching is performed.
  • side wall spacers 26 are therefore formed.
  • a silicon oxide film 26 x is left covering the floating gate electrode.
  • a silicide layer 29 is formed on the exposed source/drain regions and gate electrodes.
  • the gate electrode structures are covered with an interlayer insulating film 30 , and W plugs 31 are buried in contact holes.
  • a semiconductor device finished in this manner has non-volatile memory cells having the single layer gate electrode, low voltage MOS transistors and high voltage MOS transistors. Bird's beaks are not formed in the MOS transistors so that a high drive ability is maintained. A position alignment of a gate electrode mask is performed only once.
  • Bird's beaks may be formed under the gate electrodes of the high voltage MOS transistor.
  • FIGS. 9A to 9 D illustrate a semiconductor manufacture method according to the sixth embodiment of the present invention.
  • a hard mask pattern 15 is formed on the silicon layer 41 , the area AR 2 is covered with a resist mask 17 , and the silicon layer 41 in the areas AR 1 and AR 3 is etched by using the hard mask 15 as an etching mask.
  • the resist mask 17 is thereafter removed.
  • a protective oxide film 18 is formed on the side walls of the silicon layer 41 patterned in the gate electrode shape. Since the silicon layer 41 in the area AR 2 is still not patterned, the oxide film 18 is formed on the surface of the silicon layer 41 .
  • the areas AR 1 and AR 3 are covered with a resist mask 23 , and the silicon layer 41 in the area AR 2 is etched by using the hard mask 15 as an etching mask.
  • the resist mask 23 is thereafter removed.
  • a silicide layer 29 is formed on exposed source/drain regions and exposed gate electrodes, and an interlayer insulating film 30 is formed covering the semiconductor substrate. Contact holes are formed through the interlayer insulating film 30 and W plugs 31 are buried in the contact holes.
  • bird's beaks are formed under the gate electrode of high voltage MOS transistor to improve the breakdown voltage of the gate electrodes.
  • Other points are similar to the fifth embodiment.

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070040210A1 (en) * 2005-06-24 2007-02-22 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory and fabrication method for the same
US20070293029A1 (en) * 2006-06-14 2007-12-20 Fujitsu Limited Method for fabricating semiconductor device
US20110215395A1 (en) * 2008-10-23 2011-09-08 Nxp B.V. Multi-transistor memory cell
US20140302646A1 (en) * 2013-04-08 2014-10-09 Renesas Electronics Corporation Method of manufacturing semiconductor device
US20150054051A1 (en) * 2013-08-20 2015-02-26 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor device and fabrication method
US20150171101A1 (en) * 2013-12-17 2015-06-18 Synaptics Display Devices Kk Manufacturing method for semiconductor device
JP2016500480A (ja) * 2012-12-14 2016-01-12 スパンション エルエルシー 電荷トラップスプリットゲートデバイス及びその製作方法
US10115625B2 (en) * 2016-12-30 2018-10-30 Globalfoundries Singapore Pte. Ltd. Methods for removal of hard mask

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100575333B1 (ko) * 2003-12-15 2006-05-02 에스티마이크로일렉트로닉스 엔.브이. 플래쉬 메모리소자의 제조방법
KR100673206B1 (ko) * 2004-12-28 2007-01-22 주식회사 하이닉스반도체 플래시 메모리 소자의 제조 방법
KR100632640B1 (ko) * 2005-03-10 2006-10-12 주식회사 하이닉스반도체 플래쉬 메모리 소자의 제조방법
US7910493B2 (en) 2005-04-15 2011-03-22 Tokyo Electron Limited Semiconductor device manufacturing method, semiconductor device, plasma nitriding treatment method, control program and computer storage medium
US7238569B2 (en) * 2005-04-25 2007-07-03 Spansion Llc Formation method of an array source line in NAND flash memory
US7898016B2 (en) 2006-11-30 2011-03-01 Seiko Epson Corporation CMOS semiconductor non-volatile memory device
JP2013211448A (ja) * 2012-03-30 2013-10-10 Asahi Kasei Electronics Co Ltd 半導体装置及びその製造方法
US9111863B2 (en) * 2012-12-03 2015-08-18 Institute of Microelectronics, Chinese Academy of Sciences Method for manufacturing dummy gate in gate-last process and dummy gate in gate-last process
CN103854984B (zh) * 2012-12-03 2017-03-01 中国科学院微电子研究所 一种后栅工艺假栅的制造方法和后栅工艺假栅
JP6029989B2 (ja) * 2013-01-25 2016-11-24 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
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US9966382B2 (en) * 2016-08-16 2018-05-08 United Microelectronics Corp. Semiconductor structure and method for fabricating the same
DE102017125541B4 (de) * 2017-06-30 2020-02-27 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung mit Speicherzellenbereich und Schaltungsbereichen sowie Verfahren zu deren Herstellung
CN107978606B (zh) * 2017-11-20 2020-08-25 上海华力微电子有限公司 一种嵌入式闪存工艺集成方法
CN110634735A (zh) * 2019-09-26 2019-12-31 上海华力集成电路制造有限公司 双重栅极氧化层生长方法及半导体器件的制造方法

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4635347A (en) * 1985-03-29 1987-01-13 Advanced Micro Devices, Inc. Method of fabricating titanium silicide gate electrodes and interconnections
US4651406A (en) * 1980-02-27 1987-03-24 Hitachi, Ltd. Forming memory transistors with varying gate oxide thicknesses
US4775642A (en) * 1987-02-02 1988-10-04 Motorola, Inc. Modified source/drain implants in a double-poly non-volatile memory process
US5976934A (en) * 1996-11-22 1999-11-02 Kabushiki Kaisha Toshiba Method of manufacturing a nonvolatile semiconductor memory device with select gate bird's beaks
US6235574B1 (en) * 1999-03-22 2001-05-22 Infineon North America Corp. High performance DRAM and method of manufacture
US6281558B1 (en) * 1998-03-26 2001-08-28 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof
US6294430B1 (en) * 2000-01-31 2001-09-25 Advanced Micro Devices, Inc. Nitridization of the pre-ddi screen oxide
US20010025981A1 (en) * 1997-03-05 2001-10-04 Yoo Jong-Weon Methods of fabricating nonvolatile memory devices including bird's beak oxide
US20020033501A1 (en) * 2000-09-21 2002-03-21 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory and method of fabricating the same
US6417051B1 (en) * 1999-03-12 2002-07-09 Kabushiki Kaisha Toshiba Method of manufacturing memory device including insulated gate field effect transistors
US6448136B1 (en) * 2000-12-08 2002-09-10 Macronix International Co., Ltd. Method of manufacturing flash memory
US6794708B2 (en) * 2000-06-09 2004-09-21 Kabushiki Kaisha Toshiba Nonvolatile semiconductor device with floating gate structure

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03214777A (ja) * 1990-01-19 1991-09-19 Hitachi Ltd 半導体集積回路装置及びその製造方法
JP3397804B2 (ja) * 1992-06-09 2003-04-21 シチズン時計株式会社 不揮発性メモリの製造方法
KR0161402B1 (ko) * 1995-03-22 1998-12-01 김광호 불휘발성 메모리 제조방법
US5789776A (en) 1995-09-22 1998-08-04 Nvx Corporation Single poly memory cell and array
JPH10223782A (ja) 1997-02-06 1998-08-21 Toshiba Corp 不揮発性半導体記憶装置およびその製造方法
JPH1154637A (ja) * 1997-08-06 1999-02-26 Hitachi Ltd 半導体集積回路装置の製造方法および半導体集積回路装置
JP2002520807A (ja) * 1998-05-04 2002-07-09 サイプレス セミコンダクター コーポレイション 単一ポリメモリーセルとアレー
JP3895069B2 (ja) * 1999-02-22 2007-03-22 株式会社東芝 半導体装置とその製造方法
JP2000340773A (ja) * 1999-05-26 2000-12-08 Denso Corp 不揮発性半導体記憶装置及びその製造方法
JP4181284B2 (ja) * 1999-10-14 2008-11-12 松下電器産業株式会社 半導体装置の製造方法
TW461093B (en) * 2000-07-07 2001-10-21 United Microelectronics Corp Fabrication method for a high voltage electrical erasable programmable read only memory device
JP3916419B2 (ja) * 2001-07-02 2007-05-16 松下電器産業株式会社 半導体記憶装置の製造方法
JP2003023114A (ja) * 2001-07-05 2003-01-24 Fujitsu Ltd 半導体集積回路装置およびその製造方法
JP2003031705A (ja) * 2001-07-19 2003-01-31 Toshiba Corp 半導体装置、半導体装置の製造方法
JP2003068889A (ja) * 2001-08-23 2003-03-07 Matsushita Electric Ind Co Ltd 不揮発性半導体記憶装置の製造方法

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4651406A (en) * 1980-02-27 1987-03-24 Hitachi, Ltd. Forming memory transistors with varying gate oxide thicknesses
US4635347A (en) * 1985-03-29 1987-01-13 Advanced Micro Devices, Inc. Method of fabricating titanium silicide gate electrodes and interconnections
US4775642A (en) * 1987-02-02 1988-10-04 Motorola, Inc. Modified source/drain implants in a double-poly non-volatile memory process
US5976934A (en) * 1996-11-22 1999-11-02 Kabushiki Kaisha Toshiba Method of manufacturing a nonvolatile semiconductor memory device with select gate bird's beaks
US20010025981A1 (en) * 1997-03-05 2001-10-04 Yoo Jong-Weon Methods of fabricating nonvolatile memory devices including bird's beak oxide
US6281558B1 (en) * 1998-03-26 2001-08-28 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof
US6417051B1 (en) * 1999-03-12 2002-07-09 Kabushiki Kaisha Toshiba Method of manufacturing memory device including insulated gate field effect transistors
US6235574B1 (en) * 1999-03-22 2001-05-22 Infineon North America Corp. High performance DRAM and method of manufacture
US6294430B1 (en) * 2000-01-31 2001-09-25 Advanced Micro Devices, Inc. Nitridization of the pre-ddi screen oxide
US6794708B2 (en) * 2000-06-09 2004-09-21 Kabushiki Kaisha Toshiba Nonvolatile semiconductor device with floating gate structure
US20020033501A1 (en) * 2000-09-21 2002-03-21 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory and method of fabricating the same
US6448136B1 (en) * 2000-12-08 2002-09-10 Macronix International Co., Ltd. Method of manufacturing flash memory

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070040210A1 (en) * 2005-06-24 2007-02-22 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory and fabrication method for the same
US7566926B2 (en) 2005-06-24 2009-07-28 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory
US20090239365A1 (en) * 2005-06-24 2009-09-24 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory and fabrication method for the same
US7772102B2 (en) 2005-06-24 2010-08-10 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory and fabrication method for the same
US20070293029A1 (en) * 2006-06-14 2007-12-20 Fujitsu Limited Method for fabricating semiconductor device
US7557004B2 (en) * 2006-06-14 2009-07-07 Fujitsu Microelectronics Limited Method for fabricating semiconductor device
US20110215395A1 (en) * 2008-10-23 2011-09-08 Nxp B.V. Multi-transistor memory cell
US8994096B2 (en) * 2008-10-23 2015-03-31 Nxp B.V. Multi-transistor memory cell with an enhancement junction field effect transistor (JFET) as the access gate transistor
JP2016500480A (ja) * 2012-12-14 2016-01-12 スパンション エルエルシー 電荷トラップスプリットゲートデバイス及びその製作方法
US20140302646A1 (en) * 2013-04-08 2014-10-09 Renesas Electronics Corporation Method of manufacturing semiconductor device
US20150054051A1 (en) * 2013-08-20 2015-02-26 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor device and fabrication method
US9093317B2 (en) * 2013-08-20 2015-07-28 Semiconductor Manufacturing International (Beijing) Corporation Semiconductor device and fabrication method
US20150171101A1 (en) * 2013-12-17 2015-06-18 Synaptics Display Devices Kk Manufacturing method for semiconductor device
US9412755B2 (en) * 2013-12-17 2016-08-09 Synaptics Display Devices Gk Manufacturing method for semiconductor device
US10115625B2 (en) * 2016-12-30 2018-10-30 Globalfoundries Singapore Pte. Ltd. Methods for removal of hard mask

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US8304310B2 (en) 2012-11-06
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US20100096684A1 (en) 2010-04-22
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