JP2005183914A - フラッシュメモリ素子の製造方法 - Google Patents
フラッシュメモリ素子の製造方法 Download PDFInfo
- Publication number
- JP2005183914A JP2005183914A JP2004189321A JP2004189321A JP2005183914A JP 2005183914 A JP2005183914 A JP 2005183914A JP 2004189321 A JP2004189321 A JP 2004189321A JP 2004189321 A JP2004189321 A JP 2004189321A JP 2005183914 A JP2005183914 A JP 2005183914A
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- Prior art keywords
- voltage region
- region
- high voltage
- low voltage
- forming
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Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 30
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 125000006850 spacer group Chemical group 0.000 claims abstract description 8
- 239000011229 interlayer Substances 0.000 claims abstract description 5
- 238000005468 ion implantation Methods 0.000 claims description 29
- 229910052785 arsenic Inorganic materials 0.000 claims description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 6
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims 1
- 239000007943 implant Substances 0.000 abstract 2
- 239000003989 dielectric material Substances 0.000 abstract 1
- 238000002407 reforming Methods 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 150000002500 ions Chemical class 0.000 description 6
- 238000002955 isolation Methods 0.000 description 4
- 238000005304 joining Methods 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
【解決手段】 高電圧領域及び低電圧領域が画定される半導体基板上にゲート電極パターンを形成する段階と、前記高電圧領域及び低電圧領域が同時に露出されるようにマスクパターンを形成した後第1イオン注入工程を行なうことにより、高電圧領域の接合領域及び低電圧領域の接合領域を同時に形成する段階と、前記高電圧領域及び低電圧領域を同時に露出させるマスクパターンを除去し、前記形成されたゲート電極パターンにスペーサを各々形成する段階と、前記高電圧領域及び低電圧領域が同時に露出されるようにマスクパターンを再形成した後第2イオン注入工程を行なうことにより、前記高電圧領域の接合領域及び低電圧領域の接合領域の各々にLDD領域を同時に形成する段階と、前記結果物の全面に層間絶縁膜を形成した後、前記高電圧領域及び低電圧領域のLDD領域と接触するコンタクトプラグを形成する段階とを備える。
【選択図】図7
Description
32 素子分離膜
34 ゲート電極パターン
36a、36b 接合領域
38 スペーサ
40a、40b LDD領域
42 層間絶縁膜
44 コンタクトプラグ
Claims (3)
- 高電圧領域及び低電圧領域が画定される半導体基板上にゲート電極パターンを形成する段階と、
前記高電圧領域及び低電圧領域が同時に露出されるようにマスクパターンを形成した後、第1イオン注入工程を行なうことにより、高電圧領域の接合領域及び低電圧領域の接合領域を同時に形成する段階と、
前記高電圧領域及び低電圧領域を同時に露出させるマスクパターンを除去し、前記形成されたゲート電極パターンにスペーサを各々形成する段階と、
前記高電圧領域及び低電圧領域が同時に露出されるようにマスクパターンを再形成した後、第2イオン注入工程を行なうことにより、前記高電圧領域の接合領域及び低電圧領域の接合領域の各々にLDD領域を同時に形成する段階と、
前記結果物の全面に層間絶縁膜を形成した後、前記高電圧領域及び低電圧領域のLDD領域と接触するコンタクトプラグを形成する段階と
を備えることを特徴とするフラッシュメモリ素子の製造方法。 - 前記第1イオン注入工程は、
燐(P)イオン注入工程と砒素(As)イオン注入工程を各々行うことを特徴とする請求項1に記載のフラッシュメモリ素子の製造方法。 - 前記第2イオン注入工程は、
砒素(As)イオン注入工程を行うことを特徴とする請求項1に記載のフラッシュメモリ素子の製造方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020030091653A KR100575333B1 (ko) | 2003-12-15 | 2003-12-15 | 플래쉬 메모리소자의 제조방법 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2005183914A true JP2005183914A (ja) | 2005-07-07 |
Family
ID=34651477
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004189321A Pending JP2005183914A (ja) | 2003-12-15 | 2004-06-28 | フラッシュメモリ素子の製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US20050130372A1 (ja) |
JP (1) | JP2005183914A (ja) |
KR (1) | KR100575333B1 (ja) |
DE (1) | DE102004031517A1 (ja) |
TW (1) | TWI255015B (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7432199B2 (en) | 2006-10-20 | 2008-10-07 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor device having reduced contact resistance |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007180482A (ja) | 2005-12-28 | 2007-07-12 | Hynix Semiconductor Inc | フラッシュメモリ素子の製造方法 |
US8598005B2 (en) * | 2011-07-18 | 2013-12-03 | Spansion Llc | Method and manufacture for embedded flash to achieve high quality spacers for core and high voltage devices and low temperature spacers for high performance logic devices |
US9673208B2 (en) * | 2015-10-12 | 2017-06-06 | Silicon Storage Technology, Inc. | Method of forming memory array and logic devices |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09237846A (ja) * | 1995-12-28 | 1997-09-09 | Nippon Steel Corp | 半導体装置、不揮発性半導体記憶装置及びその製造方法 |
WO1998025305A1 (fr) * | 1996-12-04 | 1998-06-11 | Hitachi, Ltd. | Procede de fabrication d'un dispositif a semi-conducteur |
WO2004084314A1 (ja) * | 2003-03-19 | 2004-09-30 | Fujitsu Limited | 半導体装置とその製造方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3581797D1 (de) * | 1984-12-27 | 1991-03-28 | Toshiba Kawasaki Kk | Misfet mit niedrigdotiertem drain und verfahren zu seiner herstellung. |
JPS61216364A (ja) * | 1985-03-20 | 1986-09-26 | Fujitsu Ltd | 半導体装置 |
US4795716A (en) * | 1987-06-19 | 1989-01-03 | General Electric Company | Method of making a power IC structure with enhancement and/or CMOS logic |
JP3227983B2 (ja) * | 1993-09-10 | 2001-11-12 | ソニー株式会社 | 半導体装置及びその製造方法 |
US6159795A (en) * | 1998-07-02 | 2000-12-12 | Advanced Micro Devices, Inc. | Low voltage junction and high voltage junction optimization for flash memory |
JP2002118177A (ja) * | 2000-10-11 | 2002-04-19 | Toshiba Corp | 半導体装置及びその製造方法 |
JPWO2004112139A1 (ja) * | 2003-06-10 | 2006-09-28 | 富士通株式会社 | 半導体装置とその製造方法 |
-
2003
- 2003-12-15 KR KR1020030091653A patent/KR100575333B1/ko not_active IP Right Cessation
-
2004
- 2004-06-28 US US10/878,916 patent/US20050130372A1/en not_active Abandoned
- 2004-06-28 JP JP2004189321A patent/JP2005183914A/ja active Pending
- 2004-06-29 DE DE102004031517A patent/DE102004031517A1/de not_active Withdrawn
- 2004-06-30 TW TW093119276A patent/TWI255015B/zh not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09237846A (ja) * | 1995-12-28 | 1997-09-09 | Nippon Steel Corp | 半導体装置、不揮発性半導体記憶装置及びその製造方法 |
WO1998025305A1 (fr) * | 1996-12-04 | 1998-06-11 | Hitachi, Ltd. | Procede de fabrication d'un dispositif a semi-conducteur |
WO2004084314A1 (ja) * | 2003-03-19 | 2004-09-30 | Fujitsu Limited | 半導体装置とその製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7432199B2 (en) | 2006-10-20 | 2008-10-07 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor device having reduced contact resistance |
Also Published As
Publication number | Publication date |
---|---|
TWI255015B (en) | 2006-05-11 |
KR20050059928A (ko) | 2005-06-21 |
TW200520165A (en) | 2005-06-16 |
US20050130372A1 (en) | 2005-06-16 |
DE102004031517A1 (de) | 2005-07-07 |
KR100575333B1 (ko) | 2006-05-02 |
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