Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/30181—Instruction operation extension or modification
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F15/00—Digital computers in general; Data processing equipment in general
  • G06F15/76—Architectures of general purpose stored program computers
  • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
  • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
  • G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
  • G06F9/3455—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results using stride
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
  • G06F9/3802—Instruction prefetching
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
  • G06F9/3824—Operand accessing
  • G06F9/383—Operand prefetching
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
  • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
  • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
  • G06F9/3877—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
  • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
  • G06F9/3893—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
  • G06F9/3895—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
  • G06F9/3897—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path

Definitions

• the invention relates to what is claimed in the preamble and is therefore concerned with improvements in multidi ensional fields from data processing cells for data processing.
• Multidimensional fields from data processing cells are already known.
• the category of these modules includes, in particular, systolic arrays, neural networks, multiprocessor systems> processors with several computing units and / or logical cells and / or communicative / peripheral cells (10), networking and network components, such as e.g. Crossbar switches, as well as known modules of the FPGA, DPGA, Chameleon, XPUTER, etc. modules are known in particular, in which the first cells can be reconfigured during runtime without disturbing the operation of other cells, i cf.
• BESTATIGUNGSKOPIE Quantity is particularly relevant, it is currently common to provide dedicated logic circuits in the form of ASICS and the like. However, these have the problem of entailing particularly high development costs, since both the design of the circuit and the production of the large number of masks are expensive.
• the object of the present invention is to provide something new for commercial use.
• the configuration retention means are designed, at least some of the configurations available, non-volatile ..
• the function can be configured in a coarse-grained manner, i.e. if that.
• Configuration reserve means only has to hold a few bits in order to determine a respective function of the cell. This makes it easier to maintain a large number of configurations to be worked through successively, but these are in each case or at least partially predefined. At least one of ALUs, EAlUs, RAM cells, I / O cells and logic blocks can be provided as cell elements.
• the networking can also be configured in a coarse-grained manner, ie only a few bits will have to be set in order to provide the networking. In an alternative way, it is possible to at least largely predefine the networking and only vary the respective function.
• the finished module for example in its function as in the case of wave reconfiguration, is to carry out a specific one of a predetermined number of functions, but the networking itself is fixed.
• a closest neighbor Connection are provided (to the applicant's parallel application regarding the increase of the nearest neighbor dimensionality or connectivity is pointed out for the purpose of disclosure), some of the nearest neighbor connections are activated and some are deactivated.
• a circuitry arrangement and / or bus structure that can be changed, if necessary, can be reconfigured for the running time. It should be pointed out that, depending on the user requirements, a multitude of different tasks can be provided with one building block unchanged except for the configuration specification, so that mask costs are distributed over a large number of building blocks and are therefore no longer so important.
• each cell element is assigned its own configuration provision means. These can replace the configuration registers provided in XPP architectures and accessible from a central configuration memory. It is possible to enter a in the configuration reserve. Maintain a variety of configurations; this allows reconfiguration during operation, for example, without having to integrate a configuration unit which is also expensive and requires silicon area.
• the configurations to be activated can be selected within the field via status triggers, data operations, sequencer arrangements, etc. It is also preferred if a plurality of fixed, non-volatile configurations are specified in the configuration reserve. Alternatively, volatile and non-volatile configurations can be used. It is pointed out that a complete or partial configuration specification can take place before or each actual commissioning.
• Cells is reconfigured via a configuration manager or in some other way.
• the changing of the large number of held and / or predetermined configurations that is to be used in each case can be determined or changed in particular by means of wave reconfiguration or local sequencing.
• configuration storage means as ROM, EPROM, EEPROM, flash memory, fuse, antifuse-programmable storage means and / or storage means, in particular in upper layers of a silicon structure. Arrangements that provide for the configuration easily and simply with a large number of pieces are particularly preferred. This is through appropriate
• CMOS complementary metal-oxide-semiconductor
• CMOS complementary metal-oxide-semiconductor
• a function block of a defined function can be obtained by specifying a multidimensional field with cell elements that can be configured in function and / or networking and associated configuration retention means for local configuration retention, determining which configurations are to be held in these, and then non-volatile configuration retention means are provided so that they hold at least some of the configurations held non-volatile.
• AI shows a data processing arrangement according to the invention
• the multidimensional field 1 comprises three rows and columns of PAEs, as are known per se from the applicant's input mentioned and other publications. These units have coarse-granularly configurable ALUs 2b, to which data from a bus system " 2d are received via multiplexer 2c and which are flanked on both sides with forward / reverse registers 2e, 2f, as is known per se.
• the operation of the multiplexers 2g, 2c and that of the ALU 2b and the registers 2e, 2f is known per se and is not explained in detail here.
• the configuration which these units have, ie the Connections that the multiplexer activates or the respective function of the ALU are stored in the configuration memory 2 hours, and a variety of different configurations can be stored for sequencing or wave reconfiguration, which are based on signals from the cells or on external signals can be activated, and a fixed, unchangeable memory does not have to be provided for all configurations nn a memory (possibly comparatively small) may also be provided in certain cases. This therefore allows a line or memory mix.
• configuration memory 2h is non-volatile and its content is fixed during the manufacture of the IC containing the elements.
• a chip is designed which corresponds in its rough structure to a large number of other, similar chips and differs from those only in terms of the non-volatile configuration memory contents.
• non-volatile configuration memory contents are determined with dedicated metal layers and / or by burning / melting certain fuses / antifuses intended for configuration or in some other way.
• the memory contents are then determined whether the non-volatile configuration memory contents are determined with dedicated metal layers and / or by burning / melting certain fuses / antifuses intended for configuration or in some other way. The memory contents are then
• this deals with the integrated electronic processing of information which is in the form of analog signals. It should be particularly emphasized that, as will be seen, the analog processing, for example, is based on permanently stored configurations.
• FPAAs Field Programmable Analog Arrays
• FPMAs Field Programmable Mixed-Signal Arrays
• FPADs Field Programmable Analog Devices
• FPAs, FPMAs and FPADs consist of individual, programmable cells.
• the core of such a cell is an analog operational amplifier, to which a specific function from a set of possible functions can be assigned. Possible functions are, for example, adders, inverters, rectifiers and filters of the first order, with which an analog signal can be processed.
• the cells are connected to each other by a bus system and are controlled by logic elements;
• ASICs Application Specific Integrated Circuits
• DSPs Digital Signal Processors
• CPUs Central Processing
• a circuit with discrete components can be optimally designed for a specific task due to its primary flexibility.
• FPAAs FPAAs
• FPMAs FPADs
• the possibilities for processing analog signals given by FPAAs, FPMAs and FPADs are based on the model
• a single FPAA, FPMA or FPAD cell can be configured as memory in the manner of a sample-and-hold stage. However, it can then no longer perform an additional function.
• FPAAs, FPMAs and FP ⁇ Ds are subject to functional restrictions due to their exclusively analog signal processing.
• the capabilities of the digital logic implemented in FPAAs, FPMAs and FPADs are limited to the functions that are necessary for the reconfiguration of the cells.
• the function of the cells which they perform during operation is not supported, let alone expanded, by the logic in the prior art, for example by digital counting functions or basic logic functions such as NAND and NOR.
• digital counting functions or basic logic functions such as NAND and NOR.
• FPAAs, FPMAs and FPADs therefore make it possible, if at all, to perform logic functions, such as decisions dependent on input signals, only to a small extent or only with great effort.
• ASICs have a high primary flexibility because they are developed for a special application. However, they are only suitable for the application for which they are developed; ASICs can only be reconfigured within the framework specified by the application. If the application changes by a detail that was not taken into account when developing the ASIC, in extreme cases a new ASIC must be developed.
• DSPs and CPUs Of all the signal processing options, DSPs and CPUs can be configured and reconfigured most flexibly, but neither partially nor during runtime.
• analog signals in 'convert a material suitable for DSPs or CPUs format
• the analog signals must be digitally encoded. This requires an analog-to-digital conversion, which can be quite complex and expensive with higher precision requirements and can furthermore restrict the bandwidth.
• the internal bus systems in DSPs and CPUs must transmit the individual bits of a digitally coded analog signal in parallel. The required width of the data bus system increases with the required precision of the digital coding of the signal. In contrast, one line per analog signal transmitted is sufficient for analog transmission.
• DSPs and CPUs do not have a cell-like structure, but are built in the classic von Neumann architecture. Their modularity is therefore only minimal.
• analog circuits are increasingly being replaced by digital arithmetic units, for example in the case of the DSPs, whereby the disadvantages mentioned in the DSPs have to be accepted.
• the invention thus also includes a programmable, at least partially analog arithmetic unit (Reconfigurable Analog Processor, RAP) with functions expanded by logic elements, in such a way that the functional scope of a digital arithmetic unit is combined with the possibility of fast, analog calculation of complex functions (about the
• a RAP consists of cells that are freely configurable in their function and networking and can be reconfigured during runtime. When a single cell is reconfigured at runtime, other cells are not affected in their work.
• a cell is divided into an analog section and a logic section.
• the analog section is used to process analog data based on operational amplifier circuits, as are known from FPAAs, FPMAs and FPADs.
• the logic section controls the functions of the analog section during runtime, during initial configuration and during reconfiguration during runtime.
• the analog section can also be controlled and configured analog.
• each RAP cell has the possibility, independently of an analog or digital signal, that is to say with its own internal structures, to decide on a reconfiguration of itself, to initiate this reconfiguration and the necessary ones Obtain data from a suitable structure.
• the invention describes, among other things, an analog, reconfigurable arithmetic unit (Reconfigurable Analog Processor, RAP) made up of individual functional cells that are connected to each other and to the outside world by a suitable bus system.
• the function of the cells is configurable and can be reconfigured during operation so that the function of other cells that are not to be reconfigured is not impaired.
• a functional cell contains an analog section and a logic section.
• the analog section is used to process analog data based on operational amplifier circuits.
• the logic section controls the functions of the analog section during runtime, during initial configuration and during reconfiguration during runtime.
• the analog, reconfigurable arithmetic unit made up of individual functional cells that are connected to each other and to the outside world by a suitable bus system.
• the function of the cells is configurable and can be reconfigured during operation so that the function of other cells that are not to be reconfigured is not impaired.
• a functional cell contains an analog section and a logic section.
• the analog section is used to process analog data based
• Logic section the purely analog functions of the analog section by providing, for example, logic functions and / or digital counting functions and / or arithmetic and / or storage elements.
• Each cell can be assigned one or more analog memories, which store analog variables such as input or output signals and can make them available for further processing.
• each cell has one or more digital registers for storing digital data for the. Configuration and operation of the cell are necessary. For each cell there is the possibility, depending on an analog or digital signal, to decide independently, i.e. with its own internal structures, about a reconfiguration of its cells or other cells, which may have been grouped together, to initiate this reconfiguration and the necessary data from a suitable structure, which can be located on the block. There is also the possibility of tracing the analog result of the operation of a cell without access to a bus system to the cell's analog data input.
• a signal is to be defined here as a quantity, for example a voltage U_0 (t), which prevails at a specific point in time at a specific point in a circuit. Such a point can be, for example, an output, an input or a bus line.
• the voltage U_0 (t) can either be related to ground (GND) or to a second voltage U_l (t).
• the signal can be temporal, constant or variable over time.
• a signal is to be referred to here as a digital signal or digital signal if it only has two states, for example wise 0 or 1, can assume only two information in the sense of the definition of information used here.
• a signal is to be referred to here as an analog signal or an analog signal if it can assume at least three and at most countably infinitely many states, that is to say contains more than two pieces of information in the sense of the definition of the information used here. This means in particular that more and more information can be transmitted simultaneously over one line using analog signals than with digital signals.
• a cell is the smallest complete, independent functional unit of a RAP.
• Two different types of cells are possible - the simple cell and "the extended cell. Both cell types can be used on a RAP. They differ in their range of functions. Both Common to cell types is the division of their structure into an analog section and a logic section.
• Some or all of the cells can have one. Include clock multipliers for generating a local, higher clock limited to the cell, which supports, for example, the counting functions of the logic section of the cell. It is also conceivable that some or all of the cells have structures for generating a can contain cell-internal or locally limited cell clock, the frequency of which can be configured independently of the frequency of any bus clock. The cell clock can be activated and deactivated.
• the simple cell (SCELL)
• the elements of the simple cell are divided into two groups, called the analog section and the logic section.
• Analog section is used for analog data processing of the analog input signals of a cell, but can also generate analog signals, such as (but not only) a square-wave signal or a triangular signal.
• the logic section provides additional non-analog functions, in particular, for example, input data-dependent logic operations, comparisons and counting operations, memories and / or arithmetic operations and also controls the activity of the entire SCELL.
• An element of the logic section is the control logic (CL). It controls the functions of the analog section and manages signals for the reconfiguration of the cell, which are received or sent via the bus systems.
• the SCELL analog input stage is a state-of-the-art multiplexer (MUX0) for analog signals.
• the analog signal to be processed is routed from an analog data bus system (ABUS) to the inputs of MUX0.
• MUX0 controlled by the CL, selects the analog signal to be processed by the SCELL and connects it to the analog processing unit (APU, Analog Processing Unit).
• the APU is a configurable unit according to the state of the art. It contains one or more operational amplifier device (s) whose function can be selected from a set of possible functions. The function is selected using a digital signal from the CL.
• Functions of the APU can be, for example (but not only):
• the analog signal to be processed is changed in accordance with the function programmed by the CL in the APU or is not changed (in the function of a voltage follower) or the APU is used the generation of a new analog signal.
• the analog output of the APU is connected to a memory stage (BIPS).
• the BIPS can be in one of several states programmable by the CL, for example in one of the following.
• the output signal of the BIPS has the value that was at its input when the BIPS received a BUFFER signal from the CL.
• the output value is kept constant as long as the BUFFER signal is present.
• the output signal of the BIPS has the inverted value that was at its input when the BIPS received a BUFFER signal from the CL.
• the output value is kept constant as long as the BUFFER signal is present.
• INVERT The input signal of the BIPS is inverted.
• 3STATE The output of the BIPS assumes a high impedance state.
• the output of the BIPS is connected to the input of an analog de-multiplexer (DeMUX), the outputs of which are connected to the
• ABUS bus lines are connected.
• the CL controls which DeMUX output the processed analog signal is routed to.
• - digital counters that can be set, triggered, queried, reset and stopped by the CL and / or the APU; these can be formed as coarse-grained logic elements; other coarse-grained logic and / or functional elements such as arithmetic, in particular ALU-like and / or storage elements can also be implemented.
• the Extended Cell (ECELL)
• the extended cell contains a complete, fully functional SCELL which has been expanded by additional elements and functions in order (in particular (but not only)) to be able to perform loop operations without access to the bus system.
• the analog input stage has been expanded by a second, equivalent, analog multiplexer (MUX1) that accesses the ABUS.
• MUX0 and MUX1 it is possible instead of (as with a SCELL) only. one input signal two input Release signals for subsequent processing in the cell.
• MUXO and MUX1 each have an additional ' input which is connected to ground and an input to which the result signal from the output of the BIPS of ECELL is fed back.
• the output of MUXO carries the analog signal selected by MUXO for processing, which can also be the constant ground level or the result signal from the output of the ECELL's BIPS.
• the output of MUX1 carries the analog signal selected by MUX1 for processing, which can also be the constant ground level or the result signal from the output of the BIPS of ECELL.
• the output signals from MUXO and MUX1 are routed to the following programmable memory stages (BUFFO, BUFFl).
• BUFFO receives the output signal from MUXO
• BUFFl receives the output signal from MUX1.
• BUFFO and BUFFl are configurable units thanks to the CL, whose function can be selected from a set of possible functions. Possible functions of BUFFO and BUFFl are, for example
• BUFNONINV The value of the output signal from BUFFO or BUFFl is equal to the analog input signal that was present when BUFFO or BUFFl received a BUFFER signal from the CL. The output value is kept constant as long as the BUFFER signal is present.
• BUFINV The value of the output signal from BUFFO or BUFFl is equal to the analog input signal that was present when BUFFO or BUFFl received a BUFFER signal from the CL. The output value is kept constant as long as the BUFFER signal is present.
• INVERT The current analog input signal from BUFFO or BUFFl is inverted.
• the output signal from BUFFO and the output signal from BUFF1 are each fed to an analog input of the expanded analog processing unit XAPU of ECELL. All functions of the APU of a SCELL are contained in the XAPU of an ECELL.
• the XAPU has two analog inputs, so that operations with two analog, temporally constant or temporally variable signals are possible in the XAPU, in particular the addition, subtraction, multiplication and division of two such signals. It is thus conceivable to program the XAPU using an analog, time-constant or time-variable control signal by assigning certain functions to certain values of the control signal. In addition, it is conceivable to use j an analog control signal from the APU to transmit a parameter necessary for performing a function.
• f (t) is an analog time-varying (voltage) signal that is to be multiplied by a time-varying (voltage) signal g (t)
• VGA Voltage Controll. ed amplifier
• f (t) being at one analog input of the XAPU
• g (t) is at the other analog input of the XAPU and representing the said control signal.
• the output signal of the XAPU is fed to the input of the BIPS.
• the BIPS of ECELL and ' the BIPS of SCELL can be the same.
• the BIPS output signal is routed to the DeMUX input.
• the DeMUX of the ECELL and the DeMUX of the SCELL can be the same.
• the output signal of the BIPS is routed via a separate line to an input of MUXO and an input of MUX1.
• the logic section may include a clock multiplication element which multiplies the DBUS clock and which may be programmable. This means that the ECELL can operate internally with a multiple of the DBUS cycle.
• the analog section and the logic section of the cell are preferably structured and connected in such a way that when certain criteria occur, the cell can generate a signal, the RECONREQ signal, with which it can initiate its own reconfiguration or the reconfiguration of another or more other cells can.
• the RECONREQ signal can be digital and forwarded via a separate digital bus system. However, it can also be analog and can be forwarded via a separate analog bus system.
• an analog RECONREQ signal it is possible, in addition to the RECONREQ information, to transmit additional information, for example the address of the cell or cells to be reconfigured, simultaneously on only one bus line. Criteria that trigger a RECONREQ signal can, for example (but not only):
• the signals mentioned in the list above can also originate from other cells or other elements of the RAP.
• further criteria can be formed by logically linking (AND, OR, NAND, NOR, XOR etc.) the named criteria.
• the logic section of ECELL contains structures suitable for the logical linking of criteria, e.g. for comparison of results, flags of an ALU such as the transfer of an arithmetic unit (carry etc)
• the criteria for forming a RECONREQ signal are evaluated in the CL of the cell.
• the CL of the cell generates a digital word (RECONREQ word) with the necessary RECONREQ information from these criteria.
• This RECONREQ word can be passed on by the cell in digital or analog form.
• Separate bus systems (RECONREQ bus), a digital bus and an analog bus are available for this.
• the digital RECONREQ word is converted into analog form in a digital-to-analog converter (DAC).
• DAC digital-to-analog converter
• This structure can be, for example, a loading logic and a switching table as described in patent application DE196 54 846.2.
• the loading logic is a structure which, after a RECONREQ signal, carries out the reconfiguration of the cell or cells in question.
• Several cells are connected to a single LL via the RECONREQ bus. These cells form one with the associated LL. Cluster.
• Each cell in a cluster can send a RECONREQ signal to its LL and thus request every cell in the same cluster to be reconfigured.
• a building block can contain several clusters. The LLs of these clusters are connected to each other via a bus system and can therefore exchange information. Such information can in particular
• Be addresses of umzukon 'figuring cells This makes it possible for any cell of the RAP to request any cell of the RAP for reconfiguration.
• the LL can be structured according to PACT_SWT (cf. patent application cited) and can therefore process digital RECONREQ words directly.
• the LL requires analog pre-stages, namely an analog selection stage (ASELSTAGE) and an analog-digital converter stage (ADC).
• ASELSTAGE analog selection stage
• ADC analog-digital converter stage
• the job of ASELSTAGE is to check whether and on which analog RECONREQ bus a RECONREQ signal is present. If a RECONREQ signal is available on an analog RECONREQ bus, this bus is selected by the ASELSTAGE and switched to the ADC for further processing, which is the analog
• the ASELSTAGE can be realized in different ways. One way is to use a multiplexer, another is to use an arbiter.
• ASELSTAGE as a multiplexer.
• the analog RECONREQ buses of the cells monitored by the LL are connected to the inputs of a clocked analog multiplexer according to the prior art. With each cycle, the multiplexer is switched on by one input, so that with each cycle a different bus on Output of the multiplexer is.
• a comparator monitors the output of the multiplexer. If there is no analog RECONREQ signal at the output of the multiplexer, the output of the multiplexer has a certain level, for example 0 volts. If a RECONREQ signal is present, there is a different level at the output of the multiplexer, which causes the comparator to switch the RECONREQ signal to the subsequent ADC.
• several comparators can be provided which compare the signal with different signal levels and thus directly effect an evaluation. This is particularly useful. if ... only a few signal levels can be distinguished.
• ASELSTAGE as an arbiter.
• the analog RECONREQ buses of the cells in a cluster are first routed to the inputs of an analog multiplexer (AMUX). If a RECONREQ signal is present on one of the analog RECONREQ buses, this bus is selected by the AMUX and the connected RECONREQ word is switched to the output of the AMUX.
• AMUX analog multiplexer
• a RAP preferably contains at least two independent, flexible bus systems for networking the individual cells and for connecting the RAP to the outside world.
• the preferred bus systems can be configured and reconfigured during runtime without the RAP having to be interrupted.
• the bus systems can be equipped with properties as described in patent application DE 197 04 742.4. A distinction is made here between the analog bus system and the digital bus system.
• the analog bus system (ABUS)
• the ABUS analog bus system is used to transmit the analog data and analog signals to be processed, already processed or newly generated from the outside to the cells and / or between the cells.
• the ABUS it is possible with the ABUS to cascade cells in order to process an analog signal in several successive operations, with one cell being operated on. With each of its lines, the ABUS can transmit several, in particular more than two pieces of information simultaneously, for example 256 pieces of information.
• the ABUS can be clocked at a fixed or variable frequency or can be asynchronous, i.e. not clocked.
• the ABUS can be implemented in a manner as described in patent application DE 197 04 742.4.
• the digital bus system (DBUS)
• DBUS second bus system on the RAP
• the DBUS is clocked and is used to distribute digital data, such as configuration data and status data, between the cells.
• the logic section of each cell is connected to the DBUS.
• the DBUS can be implemented in a manner as described in patent application DE 197 04 742.4.
• FIG. Structure of a simple cell Figure B2 shows the structure of an expanded cell Figure B3 shows a possible way of realizing BUFFO or BUFFl
• Figure B4 shows how, for example, the expression f (t) A g (t) can be calculated.
• Figure 1 shows the structure of a simple cell (SCELL). It consists of the digital section (0101) and the analog section (0102).
• the central element of the logic section is the control logic CL (0110), which uses the DBUS (0130) with other cells and additional structures .
• CL control logic
• CL DBUS
• FIG. 1 shows the structure of a simple cell (SCELL). It consists of the digital section (0101) and the analog section (0102).
• the central element of the logic section is the control logic CL (0110), which uses the DBUS (0130) with other cells and additional structures .
• a charging logic and / or a switching table as described in patent application DE 196 54 846.2, and / or can communicate with the outside world.
• the MUXO (0121) multiplexer is connected to the ABUS (0131). If an analog signal is to be processed by the SCELL, MUXO (0121), via the lines (0141) controlled by the control logic CL (0101) or another suitable structure, selects that line of the ABUS
• the output of MUXO (0121) is connected to the analog processing unit APU (0120) via line 0146.
• the signal selected by MUXO is processed if a signal has been selected, or the APU generates a signal, which can be a RECONREQ signal, or the APU remains in a predefined idle state.
• the behavior of the APU is controlled by the CL (0101) via lines 0143. These lines (0143) can be bidirectional, so that the APU is able to send signals to the CL (0101) depending on certain events and criteria.
• the criteria can be those that for example also lead to the generation of a RECONREQ signal.
• a generated signal can in particular be a RECONREQ signal, as described in section cellreconfig ' .
• the signal processed or generated by the APU is sent via line 0149 to a memory stage BIPS (0124), the function of which is controlled by the CL (0101).
• the functions BUFNONINV, BUFINV, INVERT, PASS, 3STATE described in section scell are available.
• the analog signal is taken over by a demultiplexer DeMUX (0125), which, controlled by the CL via line 0145 or another suitable structure, switches it to the ABUS 0131.
• the logic section (0101) of the SCELL consists of the CL (0110) and the LOGUNIT (Olli), which are connected to each other via line 0140.
• Figure 2 shows the structure of an expanded cell (ECELL). It is functionally divided into an analog section (0202) and a logic section (0201).
• MUXO selects the first analog signal
• MUXl selects the second analog signal. There are three options for the origin of the two analog signals to be processed.
• the analog output signal from BUFFO (0223) is sent via line 0248 to the first analog input of the XAPU (0220).
• the analog output signal from BUFFl (0224) is sent via line 0249 to the second analog input of the XAPU (0220).
• the XAPU (0220) processes the two analog input signals into one analog output signal in accordance with the function programmed by the CL (0210) via line 0243, as described in section Ecell.
• the output signal of the XAPU (0220) is transmitted via line 0250 to a further memory stage (BIPS, 0225).
• BIPS further memory stage
• the BIPS of the ECELL and the BIPS of the SCELL can be the same.
• the function of the BIPS (0225) is controlled by the CL (0210) via line 0244.
• the analog output signal of the BIPS is transmitted via line 0251 to the demultiplexer (DeMUX, 0226), which applies the signal to the ABUS (0231).
• the DeMUX is controlled by the CL (0210).
• the logic section (0201) of the ECELL consists of a complete logic section as can be found in a SCELL, i.e. the CL (0210) and the LOGUNIT (0211), which are connected to each other via the line (0240).
• the logic section of the ECELL is also able to control and manage the XAPU (0120) with its extended range of functions compared to the APU of a SCELL. For example, enable logical operations such as NAND ' NOR, AND, OR, XOR. Input variables of such operations can be criteria that also lead to the formation of a RECONREQ signal, but also digital signals that are generated specifically for this purpose.
• Figure 3 shows a possible way of realizing BUFFO or ⁇ BUFFl.
• OP0 is an operational amplifier that is wired in such a way that it either inverts or loops through the analog signal at input IN.
• the operating mode is selected by DeMUXO. If- on. S. control input NONINV INV is a logical 0, the input signal is looped through, if there is a logical 1 at the control input NONINV INV, the input signal is inverted.
• DeMUX1 is used to decide whether the signal is buffered in capacitor C (BUFFER) or whether it is available without buffering at output OUT of OP1 (PASS). Buffering takes place when the control input BUFF PASS receives a logical 0. There is no intermediate storage if the control input BUFF PASS receives a logical 1.
• FIG. 4 shows how, for example, the expression f (t) ⁇ g (t) can be calculated.
• f (t) is logarithmized in the first cell, which means that the logarithm of f (t) to any, but fixed, base a is formed.
• a SCELL that is configured as a logarithmizer can be used for this.
• the result of this operation is multiplied by g (t) in the second cell.
• An ECELL can be used for this purpose, which multiplies both signals in the manner of a voltage-controlled amplifier.
• base a is raised to the power of the multiplication operation.
• a SCELL can be used for this, which is configured as a delogarithmizer.
• the result of the delogarithmic operation corresponds to the expression ([f (t)] A ⁇ g (t) ⁇ .
• one or more converter stages can be provided.
• Transducer units are easily adaptable to a particular purpose, for example to meet high-frequency applications or, in the case of low-frequency applications, to provide extreme low-noise or a very good signal-to-noise ratio.
• the digital and analog elements are preferably mixed, in particular on one and the same IC.
• a transition means can be provided in a mixed field by means of one or more ADCs and / or DACs and / or comparators. This is advantageous because, for example in software defined radio, the purely digital processing of the incoming high-frequency weak antenna signals is still problematic, although great freedom of choice is also desired with regard to analog signal processing and / or processing.
• the invention further relates to devices and methods for improving the transfer of data within multidimensional arrangements of transmitters and receivers or cells. It should be mentioned that this is particularly relevant in critical applications such as software defined radio.
• the cells of about multidimensional processor arrays can now perform different functions, such as e Bool specific linkages cause of input operands,
• Connections run between them, which can also be set, typically buses, for example, which can create a network in various ways and thus set up a multidimensional field that can be set in its network.
• the cells exchange information as required, such as status signals, Trigger or the data to be processed.
• the cells are arranged in rows and columns in a two-dimensional processor array, with the outputs from cells of a first row leading to buses to which the inputs of the cells of the next row are to be coupled.
• forward and backward registers are also provided in order to route data bypassing cells to bus systems of other rows, to balance branches to be executed in parallel, etc. It has also already been proposed to implement such and / or reverse registers with functionality that goes beyond pure data transfer.
• a specific function In order to carry out a specific type of data processing, a specific function must be assigned to each cell and suitable networking must be provided. Before the multidimensional processor field processes data as desired, it has to be determined which cell is to perform which function, a function has to be defined for each cell involved in a data processing task and the networking has to be determined. It is desirable to choose the function and networking so that data processing can be carried out as quickly as possible. However, it is often not possible to find a configuration that optimally guarantees the desired data transfer. Suboptimal configurations must then be used.
• the data processing cells have an aspect ratio that at least 1.5: 1, preferably 2: 1. This enables the preferred pipelining in the PAEs and / or the buses. It is preferred, but not mandatory, to provide separate pipelining in each PAE in particular, which enables cycle increases
• the cells will in particular be PAE cells with EALU, as they are per se from the previously cited state of the Technology are known. Such cells, as preferred, will be cells that can be configured in a coarse-grained manner.
• the data processing cells are arranged in rows and columns. This allows a particularly favorable design of the cells, which are typically approximately trapezoidal or rectangular. It can then be provided that at least some of the data processing cells have data inputs to receive data from an upper row and data outputs to output data to a lower row. .In . such a case, 'results in the improved connectivity in both rows.
• the data processing units are EALUs, ALU and / or register-flanked cells, i.e. It is typically used to connect different rows in addition to the data processing and data without delay, i.e. For example, registers that forward as quickly as possible still have registers that are used to delay data during forwarding, be it to prevent or interrupt uncontrolled feedback loops (principle of the so-called annihilated feedback loop termination, so-called AFTER cells) ) or to force simultaneous synchronization in the event of data splitting through branches and subsequent reunification (balancing).
• the specified minimum aspect ratio which is at least 1.5: 1, preferably assumes 15 larger values and, with careful design of the units, may well range between 5: 1 and 10: 1.
• Figure C1 shows a processor array of the present invention
• a processor field 1 generally designated 1, comprises a plurality of data processing cells 2 arranged adjacent to it and having inputs 3, the data from
• Networking routes 4 an operand linking unit 5, which link them according to the respective function of their operand linking unit 5 and outputs 6 in order to give the data linked on networking routes 4, the data processing cells or their data through which operand combination unit 5 has an aspect ratio of length to width which is greater than 2: 1.
• Processor field 1 in the present case is an arrangement which is per se known as an XPP; Alternatively, it can be arranged as an array of elements that can be partially reconfigured at runtime, for example as a processor, coprocessor, DSP, etc. In the case shown, the process field is made up of 3 rows and 4 columns, but only for reasons of
• Clarity chosen comparatively small. It will typically be made larger.
• the data processing cells 2 can be configured in a coarse granular manner and have finely granular state machines. They can be reconfigured in a manner known per se without disrupting operation. Attention is drawn to the possibility of central configuration specification realized here, but not to be explained in more detail, for example by a configuration manager, the wave configuration, etc.
• the cells contain an ALU unit as an operand i linking unit 5, in the arithmetic unit
• Operations such as addition, multiplication, subtraction and division can be carried out on up to three incoming operands, as well as links such as IS larger? Is smaller? Null? as well as XOR, OR, AND NAND etc.
• the ALU unit is arranged in the center and flanked by a forward and a reverse register, which can also be connected to the network paths 4 in a manner known per se via the connections of the data processing cell 2.
• the data inputs and outputs 3 and 6 are connected to the connection paths 4 via multiplexers. It is in the present case a bus system with a plurality of lines is provided in order to network the cells in the rows and columns in a configurable manner.
• the aspect ratio of the ALU unit is now 6: 1 in the example shown, i.e. the cell is much longer than it is wide.
• a program is first selected for execution on array 1.
• a configuration is then determined by means known per se that permits an optimal data throughput. It is now taken into account here that data also on cells that are not immediately in the row below or to the side of a given cell, but e.g. three columns are laterally offset, can receive data within one processing cycle without major delays.
• the configuration obtained taking this extended nearest neighbor definition into account is configured on the array and executed.
• the present invention is concerned not only with the advantageous structure of a multidimeriisional field of reconfigurable elements as with reconfigurable processors, but also with methods for their operation, for example in such a way that a translation of a classical high-level language (PROGRAM) such as Pascal, C, C ++ , Java etc. on a reconfigurable architecture.
• PROGRAM classical high-level language
• a method for operating a multidimensional field of reconfigurable elements in which groups of data-handling elements are configured in a predetermined manner during the runtime for processing predetermined tasks in the field, and it is provided that for at least one task to be processed, a plurality of such element group arrangements are determined in the multidimensional field, which are suitable for processing the specified tasks, for processing the specified ones
• a particularly suitable element group arrangement is selected from the plurality and the selected arrangement is configured into the field.
• the invention thus proposes to predetermine a large number of arrangements or configurations during the preparation of the actual data processing and then to select those from the predetermined element group arrangements which are particularly well suited to the processing of the specified task with the field resources then given.
• a significant improvement in the operation of a multidimensional field of reconfigurable elements is essentially given by a simple extension of the compiler with which the previously programmed codes are translated, namely by the fact that it not only determines a single configuration for a given task, but several such configurations and thus takes advantage of the fact that there is no clear solution to the problem of translating a piece of given high-language code onto a multidimensional field of reconfigurable elements.
• compiler is used here for a means that determines confections, regardless of whether it is is a router part, a translator part or another part of a means for configuration determination based on program codes. This' agent may by fixed wiring, ie, be implemented in hardware or as a software program.
• Reconfiguration data transmission takes time, it is provided that elements that are likely to be available soon are also taken into account when selecting the optimal geometry in each case. It can be exploited that it is often possible to predict that certain elements will soon be used for the reconfiguration becomes available, for example when it has received data for the further processing of cells that have already indicated its reconfigurability and the number of processing cycles still required, the downstream cells for this purpose are finite and can be estimated or known. According to the invention, such information can be managed as a reconfigurability prediction. It should be mentioned that the available and / or required elements also include bus connections, lines, etc.
• Tasks are coordinated in time, prioritization, etc. This can in particular be part of an operating system, provided the multidimensional field of reconfigurable elements is designed as a processor or coprocessor.
• CT computed to parallel processing
• a scheduler for hyperthreading, multitasking, multithreading etc. should be mentioned. In this regard, reference is made to corresponding further parts of the present application. It should be mentioned that such units can be implemented in hardware and / or software.
• configuration data is read from a memory that has non-negligible access times, or if, should real-time determination of a configuration be desired, it is generated with non-negligible generation times, it is desirable to first provide a characteristic data record that is compared to the actual configuration data record is reduced in size and then a selection can only be made on the basis of this characteristic data record.
• a characteristic data record that is compared to the actual configuration data record is reduced in size and then a selection can only be made on the basis of this characteristic data record.
• a characteristic data record that is compared to the actual configuration data record is reduced in size and then a selection can only be made on the basis of this characteristic data record.
• a characteristic data record that is compared to the actual configuration data record is reduced in size and then a selection can only be made on the basis of this characteristic data record.
• a characteristic data record that is compared to the actual configuration data record is reduced in size and then a selection can only be made on the basis of this characteristic data record.
• Configurations to be loaded in advance into a main memory which allows very quick access, to make a quick selection based on the different configuration data sets and then to download the complete configuration data for the selected configuration from the slow memory. It should be pointed out that in such cases it is also possible to read in part of the configurations beforehand, for example if it is foreseeable that certain configurations are typically preferred, be it because statistical evaluations of the typical ones
• the selection of a predefined element group arrangement that is to be configured into a field can, apart from the available geometry, also depend on other parameters. be made gig. These include the achievable processing speed, the priority of a task and / or the energy consumption that is required to process a given task in a given time. It should be noted that several parameters can be viewed at the same time, either by discarding configurations regarded as equivalent on the basis of a first parameter, such as the required field volume, by viewing a second parameter, for example by using unsharp logic methods , several parameters can be optimized at the same time as far as possible.
• Fig. Dl a multidimensional field of data-handling elements in a partially reconfigurable state
• Fig. D2 examples of different configuration geometries
• Fig. D3 a processor partially reconfigured at runtime.
• a data processing device 1 generally designated 1, comprises a multidimensional field of reconfigurable elements 2 and a preprocessor 3, which feeds configurations into the multidimensional field 1 via suitable data buses 4 and receives information about reconfigurable elements from the multidimensional field 2 and several elements a memory 5 with slow access, in which configurations for in tasks to be processed in the multidimensional field 2 are stored in advance.
• the multidimensional processor 1 is an XPU architecture, the PAE as configurable
• a keyboard, cameras that call up images, A / D converters, etc. can be provided for this purpose.
• the multidimensional field 2 consists here only of a series of exclusively identical data-handling elements, between which suitable networks via buses and the like can be configured.
• suitable networks via buses and the like can be configured.
• bus resources are assumed in the present case, although the typical application of such resources and their resources is purely practical
• the data-handling elements are suitable for processing the commands in sequence, as is known per se, that is to say that it is possible to build up sequencers over individual cells or groups of them. It should be mentioned that time division multiplexing is possible. This permits a corresponding folding of several operations, which can then also be carried out in the case of large arrays or more space.
• the multidimensional field 2 can be reconfigured for the duration, that is to say it is possible to individually handle the data Assigned to elements or groups of those new objects during run-time, without the operation of which to interrupt overall arrangement or other elements or groups' as a whole.
• configuration memories are assigned locally to the data-handling elements, just like registers, namely forward and backward registers, bus lines, fine-grained state machines for exchanging trigger signals with one another and with the preprocessor unit 3, etc.
• the preprocessor 3 is designed to load configurations into the multidimensional field, specifically via lines 4, when it receives the message from the multidimensional field that individual elements or groups of these can be reconfigured.
• the preprocessor 3 contains a local memory (cache) and is connected to a further memory 5 (hard disk, RAM), which can be accessed more slowly and on which configuration data are stored.
• a CT is suitable, for example.
• Configuration data and configuration requests are transmitted via lines 4. Attention is drawn to the implementation of Rdy / Ack protocols, 'pre-configuration of elements in element-related memories etc., which is possible but not mandatory.
• This characteristic data record comprises a first digit which indicates how many columns are spaced between the outermost cells to the left and right of one another; then they follow after a comma Number of elements in a column that are needed. If rows are free in a column, ie not occupied, there is also a b in the identifier. If a column is left blank, that is, from the respective configuration except for buses, there is a b. in the configuration. This can be seen in configurations I and II. The data for one column is separated from that of the next column by a comma. Similar configuration data are also stored for a second configuration b).
• the preprocessor 3 first loads from the memory 5 the labels which are not extensive and thus can be loaded quickly configurations. It then determines which task is to be processed quickly and which configurations can be loaded particularly well into the field. This is done by comparing the maximum column width of a possible configuration with the actually available column width. For task a), configuration III and IV can be discarded that require too many columns. Configurations I and II must also be discarded from the remaining ones due to their geometric shape. It is then examined which configuration of b) should be loaded. All three configurations can be loaded here per se.
• the data processing can then be continued with a configuration arrangement as shown in FIG. 3. It should be mentioned that in cases where different data handling elements are provided, the corresponding information can also be stored in the characteristic data record.
• the present invention thus proposes, in a first basic concept, a method for selecting one of a number of ways of achieving one
• the selection of a path can include, for example, the selection of a given algorithm from a large number of different algorithms, be it for tasks such as sorting data, certain mathematical transformations or the like. If there are several sorting algorithms, algorithms for determining a Fourier transform or the like in a program module library, z. B. can be determined for each a characteristic quantity and then a selection is made taking into account the same. This makes it possible to choose algorithms that have particularly low energy consumption, for example. This can be for mobile applications like laptops,
• a place & route algorithm can also use the optimization, for example to achieve low-energy arrangements. This is particularly preferred and is considered inventive in itself. It is also possible to provide a large number of different configurations for one and the same algorithm, for example taking into account different subtasks to be configured simultaneously and / or sequentially on the multidimensional field, and then to make a selection from these by evaluating the respectively assigned size.
• a given data processing task or a subtask should be assigned to the multidimensional field of configurable data handling elements under consideration and / or another element for data processing outside the multidimensional field; For example, a decision can be made as to whether, if the multidimensional field serves as a coprocessor, a specific subtask should be better processed on a purely sequential CPU or the reconfigurable multidimensional field, which typically works as a data flow processor or the like. It is also possible to determine the need or the usefulness of dedicated circuits such as ASICs for certain tasks.
• the field of configurable data handling elements will be a two-dimensional field. It should be mentioned that the invention can be used for fields such as FPGAs, XPP processors, etc. It is particularly preferred for partially reconfigurable processor fields for elements that can be configured at runtime, in particular partially not to be reconfigured at runtime without interference.
• data handling elements to be taken into account are in particular at least some, preferably all, of the elements buses, registers, ALUs, RAMs, I / O ports and configurating units (CTs). It should be noted that some of these parts require only an estimated or partial consumption account; For example, only certain driver stages and the like need to be taken into account in buses.
• the characteristic value is only roughly estimated, for example to determine whether a particular element is currently being used and / or configured, or whether it is not being used instead, and possibly even from a power supply to a wake -up circuit and / or at least largely disconnected from a clock supply. It is therefore not necessary to carry out an absolutely exact consumption identification, for example by specifying the consumption of the specific algebraic operation, which is currently and / or permanently assigned to a respective arithmetic-logic unit. Rather, it may be sufficient to determine the quantity that characterizes consumption only as to whether and to what extent the respective element is actually being used at the moment. Exceptions to this are possible.
• the selection will typically not be made solely taking into account the consumption-characterizing quantities, but can also include other parameters, such as a required execution time, required resources in a multidimensional field, a current or expected processor load due to other tasks and / or a currently desired or expected or permissible power consumption ,
• the key figures are available through measured values and / or hardware or synthesis analyzes and can be stored in particular in look-up tables.
• the respective path can be selected before the actual data processing, for example when defining configurations to be loaded later among several configurations that can be implemented theoretically. In such a case, it is particularly preferred if the characteristic quantity is also determined during the simulation of the data processing functions. Alternatively, it can be provided that the selection from various possible paths during the run time is done. In such a case, several possible algorithms, e.g. For example, in order to sort data, it is then queried how much individual data is to be sorted and how the degree of order of this data is, and only then is a selection from different, 'predetermined algorithms parameterized on the basis of the parameters assigned to them Consumption indicator sizes such as the total power consumption etc. made. Similarly, a configuration at runtime depending on z. B. a current possible or desired current consumption.
• a desired type of data processing is determined, which is to be carried out on the processor field. For example, a Viterbi algorithm is programmed. and a suitable one for the processor field under consideration
• FREG and BREG Forward and reverse registers (FREG and BREG) and switches in buses (LSW and RSW).
• the total energy consumption per element type is then determined and then the total energy consumption of all different units.
• the energy consumption values for a single element per cycle are in turn estimated from simulations of the hardware Circuits in the architecture under consideration and are stored in a table for the method of the invention.
• WO 00/49496 discloses a method for executing a computer program with a processor, which comprises a configurable functional unit which is capable of executing reconfigurable instructions, the effect of which can be redefined at runtime by loading a configuration program, the A method comprising the steps of selecting combinations of reconfigurable instructions, generating a respective configuration program for each combination, and executing the computer program. Each time an instruction from one of the combinations is used during execution and the configurable functional unit is not to be configured tion program is configured for this combination, the configuration program for all of the instructions of the combination can be loaded into the configurable functional unit.
• a data processing device with a configurable functional unit serving to execute an instruction according to a configurable function.
• the configurable functional unit has a plurality of independent configurable logic blocks for performing programmable logic operations to implement the configurable function.
• Configurable connection circuits are provided between the configurable logic blocks and both the inputs and the outputs of the configurable functional unit. This allows the distribution of logic functions to be optimized via the configurable logic blocks.
• the conventional arrangements are used, among other things, to process functions in the configurable data processing logic cell field, DFP, FPGA or the like, which cannot be processed efficiently on the CPU's own ALU.
• the configurable data processing logic cell array is thus practically used to enable user-defined opcodes that enable algorithms to be processed more efficiently than would be possible on the ALU arithmetic unit of the CPU without configurable data processing logic cell array support.
• the coupling is therefore usually word-based, but not block-based, as would be necessary for the data flow processing.
• logic cell fields consisting of coarse and / or fine-grained logic cells and logic cell elements consists in a very loose coupling of such a field to a conventional CPU and / or a CPU core in embedded systems.
• a conventional, sequential program can run on a CPU or the like, for example a program written in C, C ++ or the like, from which calls of data stream processing on the fine and / or grossly granular data processing logic cell field instantiate become.
• the problem then is that when programming for this logic cell field, a program that is not written in C or another sequential high-level language must be provided for the data stream processing.
• PACT04 (DE 196 54 846.2-53, WO 98/29952), PACT08, (DE) within a data processing logic cell array arrangement such as is found in particular in PACT02 (DE 196 51 075.9-53, WO 98/26356), PACT04 (DE 196 54 846.2-53, WO 98/29952) 197 04 728.9, WO 98/35299)
• PACT13 (DE 199 26 538.0, WO 00/77652)
• PACT31 (DE 102 12 621.6-53, PCT / EP 02/10572) is known to also provide sequential data processing within the data processing logic cell field , In this case, however, partial execution is achieved within a single configuration, for example in order to save resources, achieve time optimization and so on, without this already leading to a programmer being able to easily and automatically convert a piece of high-level language code to a data processing logic cell field , as is the case with conventional machine models for sequential processors.
• Time usage planning control means and methods are therefore known per se from the state of the art, which, at least under corresponding
• time-use planning control means which were used in the prior art for configuration and / or configuration management, for the purposes of scheduling tasks, threads, multithreads and hyperthreads is regarded as inventive per se. It is also desirable, at least in accordance with a partial aspect, in preferred variants to be able to support modern data processing and program processing technologies such as multitasking, multithreading, hyperthreading, at least in preferred variants of a semiconductor architecture.
• a further essential aspect of the present invention can thus be seen in the fact that data are supplied to the data processing logic cell field in response to the execution of a loading configuration by the data processing logic cell field and / or data from this data processing logic cell field are written away (STORE) by a STORE- Configuration is processed accordingly.
• These loading and / or storage configurations are preferably designed in such a way that addresses are generated directly or indirectly within the data processing logic cell field and / or another unit such as a RISC architecture, which addresses are accessed directly and indirectly for loading and / or storage should.
• This configuration of address generators within a configuration makes it possible to load a large amount of data into the data processing logic cell field, where they can be stored in internal memories (iRAM) and / or where they can be stored in internal cells such as EALUs with registers and / or the like can be filed.
• the loading or storage configuration thus enables a block-wise and almost data stream-like, - in particular comparatively fast, loading of data, and a loading configuration of this type can actually be carried out before one or more
• Loading can take place in particular from and into a cache.
• This has the advantages that the external communication with larger memory banks is handled via the cache controller, without separate switching arrangements having to be provided within the data processing logic cell field so that the access in a read or write manner with cache memory means is typically very fast and at most low latency and that a CPU unit, typically there via a separate LOAD / STORE unit, is also connected to this cache, so that data can be accessed and exchanged between the CPU core and the data processing logic unit.
• lenfeld can be done block by block quickly and in such a way that a separate command, for example from the OpCode fetcher of the CPU, does not have to be fetched and processed for each transfer of data.
• This cache coupling also proves to be considerably cheaper than coupling a data processing logic cell field to the ALU via registers if these registers only communicate with a cache via a LOAD / STORE unit, as was quoted from the non-PACT-specific ones Writings are known per se.
• a further data connection can be provided to the load / store unit of the or a sequential CPU unit assigned to the data processing logic cell field and / or to its register.
• Data processing logic cell arrangement can take place and / or by one or more multiplexers downstream of a single port.
• the logic cells of the field ALUs or EALUs can include and become typical of those on the input and / or output side, in particular both at the input - As well as short, finely granularly configurable, FPGA-like circuits on the output side, in order to cut out four-bit blocks from a continuous data stream, as required for MPEG-4 decoding.
• this is advantageous if a data stream is to get into the line and is to be subjected to a kind of preprocessing there without blocking larger PAE units.
• the ALU as SIMD
• Arithmetic unit is designed, in which case a very wide data input word of, for example, 32-bit data width is split up into several parallel data words by the upstream, for example, FPGA-like strips. For example, 4-bit width, which can then be processed in parallel in the SIMD arithmetic units, which can significantly increase the overall performance of the system if the corresponding application is required. It should be pointed out that there was talk of FPGA-like upstream or downstream structures above. With FPGA-like, however, what is explicitly mentioned does not necessarily refer to 1-bit granular arrangements. It is particularly possible instead of this to provide hyper-fine-granular structures only of finer granular structures, for example 4 bits wide.
• the FPGA-type input and / or output structures before and / or after a Removing particular as SIMD arithmetic unit designed ALU unit are configurable to always 4 bits wide wört 'he supplied and / or processed. It is possible to provide cascading here so that, for example, the incoming 32-bit wide data words flow into 4 separated or separating 8-bit FPGA-like structures arranged side by side, these 4 pieces of 8-bit wide FPGA-like structures a second one Stripe with 8 pieces of 4-bit wide FPGA-like structures is added, and if necessary after another such strip, if this is considered necessary for the respective purpose, for example 16 pieces of 2-bit wide FPGA-like structures arranged next to one another in parallel be provided.
• the coupling advantages described above for data block streams can in principle be achieved via the cache; However, it is particularly preferred if the cache is built up in strips (slice-like) and then access to several of the slices can take place simultaneously, in particular to all slices simultaneously. This is advantageous when, as will be discussed, on the data processing logic cell array (XPP) and / or the sequence target CPU and / or the sequential CPUs, a large number of threads are to be processed, be it by means of hyperthreading, multitasking and / or multithreading.
• Cache memory means with disk access or disk access enabling control means are therefore preferably provided. It can e.g. B. ' each thread can be assigned its own slice. This enables you to later ensure, when the threads are processed, that the relevant cache areas are accessed when the command group to be processed with the thread is resumed.
• the cache does not necessarily have to be divided into slices and that if this is the case, each slice does not necessarily have to be assigned to a separate thread. However, it should be noted that this is by far the preferred method. It should also be pointed out that there may be cases in which not all cache areas are used simultaneously or temporarily at a given time. Rather, it is to be expected that in typical data processing applications, such as will occur in hand-held mobile telephones (cell phones), laptops, cameras and so on, there will often be times when the entire cache is not required. It is therefore particularly preferred if individual cache areas can be separated from the power supply in such a way that their energy consumption drops significantly, in particular to or near zero.
• a slice-wise design of the cache this can be done by slice-wise deactivation of the cache using suitable power disconnection means.
• the separation can take place either via a clocking down, clock separation or a power separation.
• a single cache disk or the like can be Assignment, which is designed to recognize whether a respective cache area or a respective cache disk currently has a thread, hyperthread or task assigned to it, by which it is used. If it is then determined by the access recognition means that this is not the case, it will typically be possible to separate the clock and / or even the power. It should be noted that when you turn the power of the cache area is possible after a severing an immediate recovery response, so no significant delay is expected by the switching on and off the power supply to ⁇ if Major appropriate semiconductor technologies implementation in hardware is.
• Another particular advantage that results from the present invention is that although there is a particularly efficient coupling with regard to the transfer of data or operands in a block-by-block form, balancing is nevertheless not necessary in this way that the exact same processing time in sequential CPU and XPP 'is kauslo- or gikzellenfeld required. Rather, the processing takes place in a practically often independent manner, in particular in such a way that the sequential CPU and the data processing logic cell array arrangement can be considered as separate resources for a scheduler or the like. This allows an immediate implementation of known data processing program splitting technologies such as multitasking, multithreading and hyperthreading. The.
• the resulting advantage that path balancing is not required means that, for example, any number of pipeline stages can be run through in the sequential CPU.
• Another advantage of the present invention is that by configuring a load configuration or a store configuration in the XPP or other data processing logic cell fields, the data can be loaded into or written to the field at a speed that is no longer determined by the clock speed of the CPU, the speed at which the OpCode fetcher works, or the like.
• the sequence control of the sequential CPU is no longer a bottleneck-like limitation for the data throughput of the data cell logic field without there being only a loose coupling.
• CT or CM; configuration manager or configuration table
• CM configuration manager or configuration table
• Data processing logic cell array such as an XPP receives configurations from the opcode fetcher of a sequential CPU via the coprocessor interface. This means that the sequential CPU and / or another XPP can initiate a call that leads to data processing on the XPP.
• the XPP is then z. B. about the described Cache coupling and / or by means of LOAD and / or STORE configurations, which provide address generators for loading and / or writing away data in the XPP or data processing logic cell field, are kept in the data exchange.
• LOAD and / or STORE configurations which provide address generators for loading and / or writing away data in the XPP or data processing logic cell field
• the coprocessor coupling that is to say the coupling of the data processing logic cell array
• the scheduling for this logic cell array will also take place on the sequential CPU or on a higher-level scheduler unit or a corresponding scheduler means.
• the threading control and management practically takes place on the scheduler or the sequential CPU.
• the data processing logic cell array can be used by calling it up in a conventional manner, such as with a standard coprocessor, for example with 8086/8087 combinations.
• CT configuration manager
• Data processing logic cell array memory especially internal memory, especially in the XPP architecture, such as it is known from the various prior applications and from the applicant's publications to address RAM-PAEs or other appropriately managed or internal memories like a vector register, ie to store the data quantities loaded via the LOAD configuration in vector-like manner in the internal memories as in vector registers, after reconfiguration of the XPP or the data processing logic cell field, that is to say overwriting or reloading and / or activation of a new configuration which carries out the actual processing of the data (in this connection it should be pointed out that reference can also be made to such a processing configuration) to access a plurality of configurations, which are to be processed, for example, in wave mode and / or sequentially one after the other) as in the case of a vector register and then in turn manage the results and / or intermediate results obtained in this way into the internal memory or via the XPP like internal memory external storage, to store these results there.
• Reconfiguring the processing configuration by loading the STORE configuration in a suitable manner, which in turn happens in data stream fashion, be it via the I / O port directly into external memory areas and / or, as particularly preferred, into cache memory areas, to which then at a later point in time, the sequential CPU and / or other configurations can access the XPP that previously generated the data or another corresponding data processing unit.
• a particularly preferred variant consists, at least for certain data processing results and / or intermediate Results as memory or vector register means, in which or the data obtained are to be stored, not to use an internal memory, in which data via a STORE configuration in the cache or another area on which the sequential CPU or another data processing unit can access, are to be written away, but instead write the results directly into appropriate, in particular access-reserved cache areas, which can be organized in particular slice-like.
• This may have the disadvantage of greater latency, particularly if the paths between the XPP or data processing logic cell array unit and the cache are so long that the signal propagation times are significant, but may result in no further STORE configuration being required.
• Data processing logic cell field are determined to be kept low, while the latency when accessing the serving then only as a "quasi-cache ⁇ storage area by other units not or does not fall significantly significant.
• a configuration is also possible in such a way that the cache controller of a conventional sequential CPU addresses a memory area as a cache, which, without serving for data exchange with the data processing logic cell array, physically on and / or in the latter lies. This has the advantage that if applications are running on the data processing logic cell field which have a small local memory requirement at most and / or if only a few further configurations are required in relation to the available memory quantities, these are used as one or more sequential CPUs Cache can be available.
• the cache controller can and will be designed for the management of a cache area with a dynamic scope, ie with a varying size. Dynamic cache scope management or cache
• Scope management means for dynamic cache management will typically consider the workload on the sequential CPU and / or data processing logic cell array. In other words, it can be analyzed, for example, how many NOPs are present on the sequential CPU in a given time unit and / or how many configurations in the XPP
• the dynamic cache size disclosed hereby is particularly preferably runtime dynamic, i. H .
• the chace controller manages a current cache size, which can change from cycle to cycle or cycle group.
• the access management of an XPP or data processing logic cell array with access as internal memory as with a vector register and as a cache-like memory for external access which increases the memory access. handles have already been described in DE 196 54 595 and PCT / DE 97/03013 (PACT03).
• the cited documents are hereby incorporated in their entirety by reference for disclosure purposes.
• CT or CM configuration management unit
• CM configuration management unit
• the administration of configurations is known per se from the various property rights of the applicant, which are referred to for disclosure purposes, and from his other publications. It should now be explicitly pointed out that such units and their mode of operation, with which configurations which are currently not yet required can be preloaded, in particular independently of connections to sequential CPUs etc., can also be used very well in order to operate in multitasking mode and / or in hyperthreading and / or multithreading to effect a thread and / or hyperthread change.
• hyperthreading management hardware When used with a purely sequential CPU and / or several purely sequential CPUs, hyperthreading management hardware is thus implemented by the connection of a configuration manager.
• PACT10 DE 198 07 872.2, WO 99/44147, WO 99/44120.
• PUs can be implemented using the known techniques, as are known in particular from PACT31 (DE 102 12 621.6-53, PCT / EP 02/10572), in which one or more are located within an array Sequential CPUs are constructed using one or more memory areas in particular in the data processing logic cell field for the construction of the sequential CPU, in particular as a command and / or data register.
• Thread and / or hyperthread changes can be carried out using the known CT technology in such a way and preferably will also take place that performance slices and / or time slices are assigned by a CT known per se, software-implemented operating system scheduler or the like, during which time slices are determined which tasks or threads subsequently assume which parts per se assumes that resources are free to be processed.
• an address sequence is to be generated for a first task, according to which , during the execution of a LOAD configuration, data are loaded from a cache memory to which a data processing logic cell array is coupled in the manner described
• the processing of a second the actual data processing configuration, can be started, which can also be preloaded, since it is certain that this configuration, unless interrupts or the like force a complete task change, must be carried out
• processors are now aware of the problem of the so-called cache miss, in which the data is requested but is not available in the cache for load access, which occurs in a coupling
• a change can preferably be made to another thread, hyperthread and / or task, which in particular has been previously carried out by the operating system scheduler, in particular software-implemented, and / or by another hardware and / or software-implemented, correspondingly acting unit for a next possible one Execution was determined and accordingly preferably in advance in one of the
• latencies are when they occur because e.g. B. Configurations have not yet been configured, data has not yet been loaded and / or data has not yet been written off, bridged and / or hidden by
• Threads, hyperthreads and / or tasks are carried out which are already preconfigured and which work with data which are already available or which can be written off to resources which are already available for the write-off. That way
• Latency is largely covered and, assuming a sufficient number of threads, hyperthreads and / or tasks to be executed per se, a practically 100% utilization of the data processing logic cell field is achieved.
• a task change in such real-time capable systems will typically be possible in three ways, namely either when a task has run for a certain time (watchdog principle), when a resource is not available, be it because it is blocked by others Access or due to latencies when accessing it, in particular in a writing and / or reading manner, that is to say in the event of latencies in data access and / or when interrupts occur.
• a first variant is that within a resource that can be addressed by the scheduler or the CT. There is a change to the processing of an interrupt, for example. If the response times to interrupts or other requirements are so long that a configuration can still be processed without interruption during this time, this is not critical, especially during the processing of the currently running configuration on the resource that has to be changed to process the interrupt , a configuration for interrupt processing can be preloaded.
• the selection of the interrupt processing configuration to be preloaded is e.g. B. by CT. It is possible to run the configuration runtime on the one to be released or changed for interrupt processing Limit resource. Please refer to PACT29 / PCT (PCT / DE03 / 000942).
• a single resource ie • examples game as to reserve a separate XPP unit and / or parts of an XPP field for such processing. If an interrupt to be processed quickly occurs, • either a configuration that has been preloaded for particularly critical interrupts can be processed or loading of an interrupt handling configuration into the reserved resource is started immediately. A selection of the configuration required for the corresponding interrupt is possible by means of appropriate triggering, wave processing, etc.
• a further, particularly preferred variant of the response to interrupts if at least one of the accessible resources is a sequential CPU, consists in executing an interrupt routine on it, in which code for the data processing logic cell field is again prohibited.
• an interrupt routine is only processed on a sequential CPU without XPP data processing steps being called. This guarantees that the processing operation on the data processing logic cell field cannot be interrupted and further processing can then take place on this data processing logic cell field after a task switch.
• the actual interrupt routine does not have an XPP code, it can nevertheless be ensured that an interrupt at a later, no longer real-time point in time with the XPP leads to a state detected by an interrupt and / or a real-time request and / or Data can be responded using the data processing logic cell array.
• bus systems for reconfigurable processors in which a dynamic bus structure can take place. It should be mentioned that it is possible in particular to mix bus systems, namely the known, so-called “global” buses which can be dynamically set up and buses which cannot be set up dynamically. This also applies to the bus systems and methods disclosed below, ie the bus systems and connection set-up methods described must be are not the only bus systems or methods to be provided in a field of elements to be connected.
• the present invention thus proposes in a further basic concept a method for dynamically establishing a connection between a transmitter and a receiver via one.
• Numerous possible routes that progress from station to station in which it is provided that, starting from a unit that causes the bus structure (transmitter and / or receiver), a request is sent to the nearest stations that are ready for the bus structure, these stations a code number, here meaning, parameter, is assigned, starting from at least a plurality, preferably each free station, to which a code number has been assigned, a request to the nearest stations for the availability of the stations for a bus structure is sent, the available stations a further code number is assigned, and this continues until the desired end of the bus is reached.
• a code number here meaning, parameter
• Another essential aspect of the present invention thus exploits the knowledge that buses can be built without problems by the fact that they are closest
• Transmission stations on the way of a possible bus inquiries are sent as to whether these stations are for the bus setup are available and then, starting from the available stations, these nearest stations are addressed in a further step, the response number being recorded by the code number assignment in order to enable the bus structure to be traced back on the basis thereof. It is possible that not every station addressed and recognized as a free station proceeds when the bus is set up, because, for example, an evaluation in the station of a desired destination shows that the bus set-up has moved in the wrong direction, but everyone prefers it The free station to which a code number has been assigned tries to continue to set up the bus by also addressing the neighboring stations of the station addressed first.
• a code number is regularly assigned to each station that has been addressed. This is advantageous in order to determine that the station has already been addressed and is therefore no longer supposed to be available when it is addressed from another direction. This prevents a signal from spreading after the neighboring stations have already been released as not required.
• the parameter is changed from station to station in such a way that the route chosen when the bus is set up can be traced, in particular by way of backtracing. This backtracing can be achieved by incrementing or decrementing one at the target
• cyclic counting can also take place, i. H. Counting in a cyclic number range, in which a lower value is repeatedly started after the highest possible value has been exceeded (e.g. 1, 2, 3, 4; 1, 2, 3, 4; 1, 2-, 3 , 4; or 1, 2, 3, 4, 5; '1, 2, 3, 4, 5; 1, 2, 3, 4, 5;).
• a cyclical counting of at least three different count values is then preferred in order to characterize the station in order to ensure a correct tracing of the path.
• the method described will identify this bus to be set up, if a bus structure between transmitter and receiver is possible at all.
• the bus structure but a plurality of unnecessary stations are addressed and if possible it is preferable to release it again, after construction of the bus or to the signaling between transmitter and receiver, that 'a bus path constructed wur- de.
• the characteristic values can be reversed .
• the station in front of it is addressed and it is ensured that the stations addressed by this station that are different and therefore not located on the bus (back) are released for external use.
• everyone is speaking stations that have been released for further use in other bus routes have in turn progressed to all other stations that are not required and that were previously addressed. This ensures that all stations that were previously addressed for the bus setup are now available again.
• a signal can be sent along all stations that are required for the bus route, which tells the bus stations that they are involved in the bus route.
• Such information can in turn be sent backwards by means of back-tracing, for example by evaluating the code numbers that were assigned to the stations during the setup phase.
• a global release can then be carried out, for example by starting from the starting station or a central control instance by resetting all stations that are not currently used on existing buses or by releasing them for the establishment of a bus route.
• a bus can also be released under certain conditions, such as after a fixed time period. This type of release, however, can prevent buses that could be built per se from being set up; In the case of very large processor fields, it is conceivable that the distances become extremely long because various cell group arrangements that are dynamically configured into the field during operation have to be meandered or through such configurations, which is what large fields can take a long time. Concern is therefore preferable for it to be taken that a sufficient time to build a bus remains'.
• the other stations are released, for example by back-tracing after reaching the target station.
• This bus participation signal which is sent backwards, can take place on the basis of the numerical values which are assigned to the neighboring stations. It should also be noted that it is also possible that the station only remembers from which direction it was addressed. In such a case, traceability can take place very quickly at the neighboring stations without comparing which key figure values they have. Furthermore, if the station records which neighboring stations were still addressed when the bus was set up, it can be ensured that tracing the stations not involved in the established bus are released.
• the code number to be assigned to a station when it is addressed can therefore also be a code number which indicates the direction from which the station was addressed.
• a second bus between e.g. B. enable a second transmitter and a second receiver; one of the transmitters and / or one of the receivers can also be identical. Addressing two receivers from one and the same transmitter can be useful if, for example, a calculation result is required as an input for two different branches of a program that are configured in different areas.
• Addressing a single receiver from several transmitters may be desirable if two operands, which are to be obtained from different configuration areas, are to be linked there, and addressing one receiver via one and the same transmitter may be required if operands, the too different lent times were obtained or determined, should be linked to one and the same recipient, for example in the form a n xa n - ⁇ . It can then be ensured via registers in the bus that such a link would be possible after two bus systems have been set up, even if this would typically be less preferred than local buffering of operands and the like for reasons of energy consumption in the bus system.
• the further or next to be built bus can be set up, for example, by sending a signal with the station release signal after a station has been provisionally reserved, indicating which bus the station belonged to, which bus can in turn be identified by a prioritization signal. If a releasing station is then adjacent to a station that would like to set up a bus itself that has a slightly lower prioritization, this can be determined there and the next bus set-up can then be initiated from this station. Alternatively, if all stations that are not currently required on a bus structure are released globally and / or thereafter, a global signal can be sent, for example from a central control entity, which tells the field which bus connection is to be established next or which priority the next bus connection to be established.
• bus configuration management information of this type can also in particular centrally and / or locally in several places, for example in hierarchically arranged processor fields in which a bus structure is desired within a certain area Bus requesting station such as a transmitter that must reach its receiver.
• Bus requesting station such as a transmitter that must reach its receiver.
• Which type of station release and / or the notification that a further bus can be set up is actually implemented will depend in particular on how quickly the relevant information can be propagated via the array and / or which bus set-up frequency is expected over time.
• bus connections in the horizontal and vertical directions for example, if the bus connections in the vertical direction additionally include registers through which the data are to be routed, while along the vertical direction there are bus connections that transmit data with lower energy losses (a An example of such an architecture is the applicant's XPP 128), which is provided when the bus is set up The number of steps taken horizontally and vertically is noted.
• This information can be stored in a station or on a header that is also transmitted with the bus structure request signal; Such information is then evaluated for bus selection. Alternatively, it can be queried at each station, for example, how many buses already exist in the vicinity of the station, for example in order to enable an approximately uniform bus connection density to be obtained across the array. On the one hand, this procedure is advantageous because the data transport along the buses results in increased energy consumption due to the necessary reloading of the bus line capacities, the drivers to be integrated in the buses, which is why the bus distribution density is evened out over the processor field in order to equalize the thermal
• the clock rate can possibly be increased overall with the same cooling, which is advantageous in the field of mobile processors for laptops, cell phones and the like.
• equalizing the bus connection density is also advantageous for increasing capacity utilization and conserving resources.
• Multidimensional field of reconfigurable elements can refer to coarse-granular reconfigurable elements with elements such as ALUs, extended ALUs, RAMPAEs, etc., as mentioned above, and that in the sense of the invention a multidimensionality not only through the spatial stacking and juxtaposition of reconfigurable elements can be obtained, but also by a certain way of connection.
• the elements in FIG. 5 are assigned two closest neighbors in the middle, in two-dimensional fields such as typically four nearest neighbors in tiling, and in a three-dimensional arrangement typically six nearest neighbors, as is the case with the stacking of cubes and the like can be recognized.
• FIG. El shows a multidimensional field of communicating reconfigurable elements, which are designed for the bus structure, before the start of the bus structure;
• FIG. E2 shows the field from FIG. 1 after the first bus setup step;
• FIG. E3 shows the field from FIG. 1 after the second bus setup step;
• FIG. E4 shows the field from FIG. 1 after the receiver field has been reached with different, possible bus connections;
• Fig. E5 the arrangement with the selected bus.
• panel 1 comprises a plurality of reconfigurable cells that can communicate via self-assembling buses together.
• Each cell la, lb, lc etc. to be involved in the bus structure has internal logic elements that make it possible to store information about whether the cell is currently being used by a bus (cells marked with an X in field 1) whether the cell has already been addressed as a possible bus cell with a current bus structure, and, if so, in how many vertical and horizontal steps the bus structure was carried out to the cell, how many steps were covered during the bus structure or whether the cell is still completely free and has not yet been addressed.
• two memory areas are provided in each cell, which are denoted by H and V in the figures.
• a memory area for the total number of steps performed can be stored, as represented by the large numbers 1-12 in FIGS. 1-5.
• the selected maximum number 12 is only an example, since in the selected example of low complexity this is the number of steps required to reach the receiver, starting from the selected transmitter.
• the cells are further designed to do so when they receive a bus setup request signal and are free. are at one participate in the bus to be set up, and at the same time send a request to neighboring stations in a subsequent step as to whether these neighboring stations are also free to set up the bus. For this purpose, they have signal transmission and reception connection circuits for the nearest neighbors.
• the individual cell is further designed such that, together with the bus structure request signal, information relating to the total step size already covered and the number of horizontal and vertical substeps (H and V) can be transmitted to the 10 stations addressed.
• the bus is set up as follows: First, the dynamically configurable array is operated in such a way that all the buses are set up. Then like it
• neighbors i.e. those cells that border on the cell edges, in the example shown four cells. These cells find that they are free, that they are the are first stations that receive bus setup request signals, and that they are each one step horizontally or vertically, respectively, from the transmitting cell. It will be 0 or 1 stored in the neighbor cells corresponding to the H and V a memory area, and it is stored a 1 'eiten employer in the Stepwise of the requested cell.
• each previously addressed free cell in turn addresses its own neighboring cells and asks if they are available for the bus setup.
• Corresponding notes on the horizontal or vertical step size are also stored in corresponding memory areas.
• the cells already marked with X on the other hand, ignore the bus setup request signal, as is the case in the 4th cell from the left, 2nd row from below.

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