GB9828381D0 - Hardware/software codesign system - Google Patents

Hardware/software codesign system

Info

Publication number
GB9828381D0
GB9828381D0 GBGB9828381.5A GB9828381A GB9828381D0 GB 9828381 D0 GB9828381 D0 GB 9828381D0 GB 9828381 A GB9828381 A GB 9828381A GB 9828381 D0 GB9828381 D0 GB 9828381D0
Authority
GB
United Kingdom
Prior art keywords
hardware
codesign system
software codesign
software
system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
GBGB9828381.5A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oxford University Innovation Ltd
Original Assignee
Oxford University Innovation Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oxford University Innovation Ltd filed Critical Oxford University Innovation Ltd
Priority to GBGB9828381.5A priority Critical patent/GB9828381D0/en
Publication of GB9828381D0 publication Critical patent/GB9828381D0/en
Application status is Ceased legal-status Critical

Links

GBGB9828381.5A 1998-12-22 1998-12-22 Hardware/software codesign system Ceased GB9828381D0 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GBGB9828381.5A GB9828381D0 (en) 1998-12-22 1998-12-22 Hardware/software codesign system

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GBGB9828381.5A GB9828381D0 (en) 1998-12-22 1998-12-22 Hardware/software codesign system
AU18752/00A AU1875200A (en) 1998-12-22 1999-12-21 Hardware/software codesign system
GB0115062A GB2362005B (en) 1998-12-22 1999-12-21 Hardware/software codesign system
PCT/GB1999/004338 WO2000038087A1 (en) 1998-12-22 1999-12-21 Hardware/software codesign system

Publications (1)

Publication Number Publication Date
GB9828381D0 true GB9828381D0 (en) 1999-02-17

Family

ID=10844844

Family Applications (2)

Application Number Title Priority Date Filing Date
GBGB9828381.5A Ceased GB9828381D0 (en) 1998-12-22 1998-12-22 Hardware/software codesign system
GB0115062A Expired - Fee Related GB2362005B (en) 1998-12-22 1999-12-21 Hardware/software codesign system

Family Applications After (1)

Application Number Title Priority Date Filing Date
GB0115062A Expired - Fee Related GB2362005B (en) 1998-12-22 1999-12-21 Hardware/software codesign system

Country Status (3)

Country Link
AU (1) AU1875200A (en)
GB (2) GB9828381D0 (en)
WO (1) WO2000038087A1 (en)

Families Citing this family (36)

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US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
EP1138001B1 (en) 1998-11-20 2003-08-27 Altera Corporation Reconfigurable programmable logic device computer system
US6539532B1 (en) 1999-02-26 2003-03-25 Xilinx, Inc. Method and apparatus for relocating elements in an evolvable configuration bitstream
US6363517B1 (en) 1999-02-26 2002-03-26 Xilinx, Inc. Method and apparatus for remotely evolving configuration bitstreams
US6378122B1 (en) 1999-02-26 2002-04-23 Xilinx, Inc. Method and apparatus for evolving a plurality of versions of a configuration bitstream in parallel
US6430736B1 (en) * 1999-02-26 2002-08-06 Xilinx, Inc. Method and apparatus for evolving configuration bitstreams
US6363519B1 (en) 1999-02-26 2002-03-26 Xilinx, Inc. Method and apparatus for testing evolvable configuration bitstreams
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7343594B1 (en) 2000-08-07 2008-03-11 Altera Corporation Software-to-hardware compiler with symbol set inference analysis
US7257780B2 (en) 2000-08-07 2007-08-14 Altera Corporation Software-to-hardware compiler
US7069204B1 (en) * 2000-09-28 2006-06-27 Cadence Design System, Inc. Method and system for performance level modeling and simulation of electronic systems having both hardware and software elements
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
GB0028079D0 (en) * 2000-11-17 2001-01-03 Imperial College System and method
US20020112219A1 (en) * 2001-01-19 2002-08-15 El-Ghoroury Hussein S. Matched instruction set processor systems and efficient design and implementation methods thereof
US20020116166A1 (en) * 2001-02-13 2002-08-22 El-Ghoroury Hussein S. Matched instruction set processor systems and method, system, and apparatus to efficiently design and implement matched instruction set process systems using interconnected design components
US7055019B2 (en) 2001-02-13 2006-05-30 Ellipsis Digital Systems, Inc. Matched instruction set processor systems and method, system, and apparatus to efficiently design and implement matched instruction set processor systems by mapping system designs to re-configurable hardware platforms
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
AU2003286131A1 (en) * 2002-08-07 2004-03-19 Pact Xpp Technologies Ag Method and device for processing data
EP1286279A1 (en) * 2001-08-21 2003-02-26 Alcatel Alsthom Compagnie Generale D'electricite Configuration tool
US20030140337A1 (en) * 2001-12-21 2003-07-24 Celoxica Ltd. System, method, and article of manufacture for data transfer reporting for an application
US20030121010A1 (en) * 2001-12-21 2003-06-26 Celoxica Ltd. System, method, and article of manufacture for estimating a potential performance of a codesign from an executable specification
US6668312B2 (en) * 2001-12-21 2003-12-23 Celoxica Ltd. System, method, and article of manufacture for dynamically profiling memory transfers in a program
GB0215034D0 (en) * 2002-06-28 2002-08-07 Critical Blue Ltd Architecture generation method
CN1672132A (en) * 2002-07-25 2005-09-21 皇家飞利浦电子股份有限公司 Source-to-source partitioning compilation
US6964029B2 (en) * 2002-10-31 2005-11-08 Src Computers, Inc. System and method for partitioning control-dataflow graph representations
US6983456B2 (en) 2002-10-31 2006-01-03 Src Computers, Inc. Process for converting programs in high-level programming languages to a unified executable for hybrid computing platforms
DE10316292A1 (en) * 2003-04-09 2004-11-11 Siemens Ag Method and arrangement for performance prediction of an information technology system
US7424698B2 (en) 2004-02-27 2008-09-09 Intel Corporation Allocation of combined or separate data and control planes
US7073159B2 (en) 2004-03-31 2006-07-04 Intel Corporation Constraints-directed compilation for heterogeneous reconfigurable architectures
US7945894B2 (en) 2005-12-05 2011-05-17 National Instruments Corporation Implementing a design flow for a programmable hardware element coupled to a processor
US8121813B2 (en) 2009-01-28 2012-02-21 General Electric Company System and method for clearance estimation between two objects
US20120096445A1 (en) * 2010-10-18 2012-04-19 Nokia Corporation Method and apparatus for providing portability of partially accelerated signal processing applications
US8959469B2 (en) 2012-02-09 2015-02-17 Altera Corporation Configuring a programmable device using high-level language
CN104572234A (en) * 2014-12-29 2015-04-29 杭州华为数字技术有限公司 Method for generating source codes used for parallel computing architecture and source-to-source compiler

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5535342A (en) * 1992-11-05 1996-07-09 Giga Operations Corporation Pld connector for module having configuration of either first PLD or second PLD and reconfigurable bus for communication of two different bus protocols
SE505783C2 (en) * 1995-10-03 1997-10-06 Ericsson Telefon Ab L M Method for making a digital signal processor
EP1065611A3 (en) * 1995-10-23 2006-05-10 Interuniversitair Microelektronica Centrum Vzw A design environment for hardware/software co-design
DE69631278T2 (en) * 1995-10-23 2004-11-18 Interuniversitair Micro-Electronica Centrum Vzw Design system and method for combined design of hardware and software

Also Published As

Publication number Publication date
GB2362005A (en) 2001-11-07
WO2000038087A1 (en) 2000-06-29
AU1875200A (en) 2000-07-12
GB0115062D0 (en) 2001-08-15
GB2362005B (en) 2003-07-16

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Legal Events

Date Code Title Description
COOA Change in applicant's name or ownership of the application
AT Applications terminated before publication under section 16(1)