US20020152060A1 - Inter-chip communication system - Google Patents

Inter-chip communication system Download PDF

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Publication number
US20020152060A1
US20020152060A1 US09/900,124 US90012401A US2002152060A1 US 20020152060 A1 US20020152060 A1 US 20020152060A1 US 90012401 A US90012401 A US 90012401A US 2002152060 A1 US2002152060 A1 US 2002152060A1
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US
United States
Prior art keywords
logic
data
simulation
fpga
system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US09/900,124
Inventor
Ping-sheng Tseng
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
VERISITY DESIGN Inc A CALIFORNIA Corp
Original Assignee
Axis Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US09/144,222 priority Critical patent/US6321366B1/en
Priority to US37301499A priority
Application filed by Axis Systems Inc filed Critical Axis Systems Inc
Priority to US09/900,124 priority patent/US20020152060A1/en
Assigned to AXIS SYSTEMS, INC. reassignment AXIS SYSTEMS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TSENG, PING-SHENG
Priority claimed from US09/918,600 external-priority patent/US20060117274A1/en
Publication of US20020152060A1 publication Critical patent/US20020152060A1/en
Assigned to VERISITY DESIGN, INC. A CALIFORNIA CORPORATION reassignment VERISITY DESIGN, INC. A CALIFORNIA CORPORATION MERGER (SEE DOCUMENT FOR DETAILS). Assignors: AXIS SYSTEMS, INC.
Priority claimed from US13/078,786 external-priority patent/US9195784B2/en
Application status is Abandoned legal-status Critical

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