GB2304438A - Re-configurable application specific device - Google Patents

Re-configurable application specific device Download PDF

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Publication number
GB2304438A
GB2304438A GB9516877A GB9516877A GB2304438A GB 2304438 A GB2304438 A GB 2304438A GB 9516877 A GB9516877 A GB 9516877A GB 9516877 A GB9516877 A GB 9516877A GB 2304438 A GB2304438 A GB 2304438A
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device
data
micro
controller
input
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GB9516877D0 (en )
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Kenneth Austin
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Kenneth Austin
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture

Abstract

In a re-configurable semi-conductor integrated circuit device which, as made, comprises a plurality of cells (2) which have two or more possible configurations, means (3) for storing configuration data for at least two cell configurations (per cell), data memory (5) for the array of cells, and input/output channels for the device, improvements in flexibility and efficiency are made possible by the provision of a programmable micro-controller (9) and a direct memory access engine (11) controlled by the programmable micro-controller to control the transfer of data to and/or from:- the array memory; the input/output channels and the means storing configuration data. Re-configuration may be initiated by interrupt signals generated by an off-chip signal, an on-chip signal or an on-chip event. A plurality of programmable sequencers are used to generate a sequence of configuration data storage addresses.

Description

TITLE: Re-configurable application specific device DESCRIPTION The present invention relates to a reconfigurable integrated circuit, with particular emphasis on a re-configurable application specific device, but without limitation to same.

U.K. Patent Application No. 9503003 describes a configurable semi-conductor integrated circuit, eg. a digital signal processor, in which an area thereof is formed with a plurality of cells each having at least one function and interconnections with at least some other said cells. At least some of the plurality of cells have interconnections which ar electrically selectable as to their conduction state, and at least some of the plurality of cells have interconnections which are pre-wired. Each cell has two or more possible configurations, each configuration being defined by the cell function and/or its interconnection with other cells according to cell configuration data.Means is provided for storing configuration data for at least two cell configurations (per cell) and means is provided to enable one of the possible cell configurations according to the cell configuration data selected. A control circuit is utilised to pass configuration data, program data and coefficients to an array memory and memory caches.

The previous architecture had fixed programming circuitry and the present invention aims to provide improvements in flexibility and efficiency.

Accordingly, the present invention provides a reconfigurable semi-conductor integrated circuit device of the type which, as made, comprises a plurality of cells which have two or more possible configurations, means for storing configuration data for at least two cell configurations (per cell), data memory for the array and input/output channels for the device, the device further comprising a programmable micro-controller and a direct memory access engine controlled by the programmable micro-controller to control the transfer of data to and/or from:- the array memory; the input/output channels and the means storing configuration data.

More particularly, the direct memory engine (hereinafter referred to as a DMA engine) directly generates internal and external addresses transferring a preselected number of data words. Thus, the microcontroller directs data transfer, while the DMA engine is responsible for transferring data at high speed. It receives its instructions from the micro-controller and transfers data in the background.

A further advantageous feature is the provision of interrupt logic that can be used to interrupt the main flow of data and cause a new set of transfers to occur. Interrupts may be generated either by an offchip signal, and on-chip signal or an on-chip event caused by an interrupt timer. It is preferred that the micro-controller has a dedicated interrupt circuit for each of the logic blocks. For this purpose each logic block feeds a control node of the micro-processor which can be used to signify the end of a task or request for more data etc. More preferably still, the microcontroller has a timer for each logic block and the timer can be used to time a process that the block is performing thereby freeing the block from dedicating some of its cells to this task.A further alternative is for external signals to be routed into the microcontroller from the input to replace or be used in conjunction with internally generated interrupts.

More particularly the device further comprises a plurality of programmable sequencers which can be programmed individually or in combination to generate a sequence of configuration data storage addresses.

A further feature of the invention comprises a programmable input/output by which the band width allocated for user input/output of configuration data and program data can be altered according to the application of the device.

The present invention will now be described further, by way of example only, with reference to the accompanying drawings; in which: Figure 1 is a schematic block diagram showing the principal elements of an integrated circuit device according to the present invention, Figure 2 illustrates the device of Figure 1 in further detail, Figure 3 is a schematic diagram showing in further detail one cell of the logic block for the device of Figures 1 and 2, Figure 4 is a schematic illustrating the logic blocks and the associated circuitry with address line and active cache selection, Figure 5 is a schematic of the logic blocks showing the details of the circuitry utilised for selecting and updating the memory caches, Figure 6 is a block diagram illustrating a single bit sequencer for use in the device of Figures 1 and 2, Figure 7 is a schematic circuit diagram for a programmable modulo counter as used in the single bit sequencer, Figure 8 is a flow chart illustrating part of a normal program flow, and Figure 9 is a flow chart showing the interrupt service routine.

The present invention is described in the context of an integrated circuit intended for an application specific device, one embodiment of which is a reconfigurable signal processor (DSP). A device according to Figure 1 comprises a plurality of logic function units or cells 2, programmable inputs and outputs 4 for the logic function units, and a configuration cache 3 storing configuration data for the logic function units. In practice, the configuration cache 3 may be on-chip in immediate proximity to the logic function units as part of an array of logic blocks, as illustrated in Figures 3, 4 and 5. The processor also comprises a data memory 5, a micro-sequencer 7, a micro-controller 9, a direct memory access engine 11 and programmable input/output 13 for the DMA engine and micro-controller.

According to a preferred embodiment the logic block array comprises 32 logic blocks 21 as shown diagrammatically in Figure 2. Each logic block 21 comprises a matrix array of cells, for example an array of 8 x 8 cell. Figure 3 illustrates schematically in further detail one of the logic cells of one of the logic blocks 21. It comprises a cell function unit 22 incorporating the desired logic circuitry, an 8 bit decoder 23, four-8 bit configuration caches 25(a-d), comprising programmable memory (RAM), two-8 bit ROM configuration memories 27a, b representing two alternative boot-up configurations for the cell function unit. Usually the cells will be disposed in groups, eg. columns which show the same boot up configuration - representing primary functions, eg.

shifter, compare, adder etc. Also there are decode cells, eg. the row of cells at the bottom in Figures 4 and 5. Also illustrated are two 4-1 input multiplexers 28, 29 receiving signal inputs from other cells at 38 and 40, and a 1-4 output multiplexer 31 giving outputs to other cells at 42. The decoder 23 controls the input and output multiplexers and the cell function unit, either in terms of logic function or interconnect function by way of connection lines 30, 32, 34 and 36, according to which of the configuration caches 25a-d, 27a, b is selected. In addition an instruction bus 35 connects into the logical unit from the decode cells and also serves to control the function of the logic function unit. In the illustrated embodiment caches 25 and 27 have four and two address lines respectively.

Addressing of the logic block and transferring of data is described further with reference to Figure 2, 4 and 5.

The micro-controller 9 instructs the DMA engine 11 having taken its program instructions from the programmable input 13 via multiplexer 41. The program data is read in along program data bus 43.

Figure 6 illustrates one of eight single bit sequencers for the device which make up the microsequencer 7 of Figure 1. Each comprises, in the illustrated embodiment a four-input multiplexer 601 receiving global clock inputs - CLK1, CLK2, CLK3 and CLK4. There are two modulo counters, one, 100, operating on frequency and the other, 101, operating on sequence length. These are set from the microcontroller. A sequence can be stored in each of RAM blocks A and B. Means is provided for selecting which of the sequences is to be output on a global cache line.

Figure 6 illustrates the output for global cache-line G1. Thus, there are eight possible outputs G1-G8 for the whole device. The global lines G1-G8 are illustrated in Figure 4. Signals from the 8 global lines can be fed to each logic block 21. The global lines connect with 3, 8 input multiplexer 105, 107 and 109. The micro-controller controls the multiplexers 105, 107, 109 according to the selection of either RAM A or RAM B which has associated read enable, write enable, and data transmission lines 210, 212 and 214 respectively. Outputs from the three multiplexers 105, 107, 109 feed to decoder 115. Furthermore, there are node connections in each logic block and global connections with each logic block, x busses, these can provide a signal source for selection by the multiplexer as an alternative to or in addition to signals on lines G1-G8.Decoder 15 has six output lines which connect with the respective RAM and ROM memory caches by horizontal connection lines.

Figure 5 illustrates for one logic block the circuitry utilised for selecting and/or updating the caches of the array of cells. Co-ordinate selection of any of the caches 25a-d, 27a, b of a cell is possible utilising the two decoders 502, 504 by way of the DMA engine 11 under the instructions from the microcontroller. Transferring of data to the selected caches (in the case of the RAM caches 25a-d) is by data bus 506 with data being passed by the DMA engine under instruction from the micro-controller. Where the data is to be written to the number of the caches is to be same, this can be written simultaneously to these caches.

The micro-controller has associated interrupt logic which can be used to interrupt the main flow of data and cause a new set of transfers to occur.

Interrupts may be generated by either an off-chip signal, for example through the programmable input 13, an on-chip signal or an on-chip event caused by an interrupt timer. The micro-controller 9 has a dedicated interrupt circuitry for each of the 32 array blocks.

Furthermore each block can generate in interrupt by taking a control node on the micro-controller high, signalling the end of a task or request for more data.

Alternatively, the micro-controller can use one of its 32 timers (not illustrated), ie. one for each logic block, to time a process that the block is performing thereby freeing the block from dedicating some of its cells to this task. External signals can be routed into the micro-controller which can replace or be used in conjunction with other generated interrupts.

A further feature of the invention is the use of programmable input/output which allows the designer to allocate pins, ie. band width, to apportion user input/output for configuration data and program data.

Accordingly, a program address generator 150 is provided - see Figure 2. A multiplexer 41 sets the band width for the configuration data and the program data under control of the micro-controller 9, in conjunction with the DMA engine and the respective address busses 154, 156 and 158. Thus, the band width/number of pins allocated to configuration and program data respectively can be allocated according to the requirements for the task to be performed.

The operation of the circuit will now be described with reference to the flow chart of Figure 8.

On powering up the device to configure a specific application, the program input determines whether one of the prewired ROM configuration 27a, 27b is to be selected. If it is then the required control information is sent to the array as indicated by box 100. If not, then the required configuration data is written to say the first memory cache 25a and the first logic block. The timer will be set for that logic block as will the interrupts for that logic block. The process is repeated for all the logic blocks with the configuration data to be written to the blocks being determined by the architecture specification data, whilst the timers and interrupts are set according to control flow information. This all serves to initialise the array with the required start-up configuration if it is not to be one of the prewired boot configurations.

In the normal program flow the micro-controller is programmed to monitor a node in each logic block so that when an event occurs which turns it high or low a corresponding instruction will be carried out. In the example given for a false signal, instructions are sent to a decode cell to set a desired function for one column of cells. That selection will remain, for example until the allocated time has been completed or until an interrupt signal is received from one or more of the various sources. Where the signal is true then an alternative configuration cache is adopted. The program continues to run with that configuration cache until it is instructed to change caches as part of the program run or according to interrupts.

Figure 9 illustrates a interrupt service routine in more detail from which it will be seen that interrupts may be array interrupts 61 or timer interrupts 63. There is one for each logic block.

Claims (12)

1. A re-configurable semi-conductor integrated circuit device of the type which, as made, comprises a plurality of cells which have two or more possible configurations, means for storing configuration data for at least two cell configurations (per cell), data memory for the array and input/output channels for the device, the device further comprising a programmable microcontroller and a direct memory access engine controlled by the programmable micro-controller to control the transfer of data to and/or from:- the array memory; the input/output channels and the means storing configuration data.
2. A device as claimed in claim 1 in which the direct memory engine directly generates internal and external addresses transferring a preselected number of data words.
3. A device as claimed in claim 1 or 2 in which the micro-controller directs data transfer, while the DMA engine is responsible for transferring data at high speed.
4. A device as claimed in any one of claims 1, 2 or 3 in which interrupt logic is provided to interrupt the main flow of data and cause a new set of transfers to occur.
5. A device as claimed in claim 4 in which interrupts are generated either by an off-chip signal, an on-chip signal or an on-chip event caused by an interrupt timer.
6. A device as claimed in claim 4 or 5 in which the micro-controller has a dedicated interrupt circuit for each of the logic blocks.
7. A device as claimed in claim 6 in which each logic block feeds a control node of the micro-processor which can be used to signify the end of a task or request for more data etc.
8. A device as claimed in any one of claims 4, 5, 6 or 7 in which the micro-controller has a timer for each logic block and the timer can be used to time a process that the block is performing.
9. A device as claimed in any one of claims 4 to 8 in which external interrupt signals are routed into the micro-controller from the input to replace or be used in conjunction with internally generated interrupts.
10. A device as claimed in any one of the preceding claims further comprising a plurality of programmable sequencers which can be programmed individually or in combination to generate a sequence of configuration data storage addresses.
11. A device as claimed in any one of the preceding claims further comprising a programmable input/output by which the band width allocated for user input/output of configuration data and program data can be altered according to the application of the device.
12. A device constructed and arranged substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.
GB9516877A 1995-08-17 1995-08-17 Re-configurable application specific device Withdrawn GB9516877D0 (en)

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GB9516877A GB9516877D0 (en) 1995-08-17 1995-08-17 Re-configurable application specific device
PCT/GB1996/002013 WO1997007466A1 (en) 1995-08-17 1996-08-19 Re-configurable application specific device

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GB2391671A (en) * 1999-07-02 2004-02-11 Altera Corp Embedded memory blocks for programmable logic
EP1472616A2 (en) * 2001-09-19 2004-11-03 PACT XPP Technologies AG Reconfigurable elements
EP1610227A1 (en) * 2004-06-24 2005-12-28 Fujitsu Limited Reconfigurable processor with configuration cache and semiconductor device
US7650448B2 (en) 1996-12-20 2010-01-19 Pact Xpp Technologies Ag I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
US7657877B2 (en) 2001-06-20 2010-02-02 Pact Xpp Technologies Ag Method for processing data
US7782087B2 (en) 2002-09-06 2010-08-24 Martin Vorbach Reconfigurable sequencer structure
US7822881B2 (en) 1996-12-27 2010-10-26 Martin Vorbach Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like)
US7822968B2 (en) 1996-12-09 2010-10-26 Martin Vorbach Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs
US7840842B2 (en) 2001-09-03 2010-11-23 Martin Vorbach Method for debugging reconfigurable architectures
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US8099618B2 (en) 2001-03-05 2012-01-17 Martin Vorbach Methods and devices for treating and processing data
US8127061B2 (en) 2002-02-18 2012-02-28 Martin Vorbach Bus systems and reconfiguration methods
US8156284B2 (en) 2002-08-07 2012-04-10 Martin Vorbach Data processing method and device
US8209653B2 (en) 2001-09-03 2012-06-26 Martin Vorbach Router
US8230411B1 (en) 1999-06-10 2012-07-24 Martin Vorbach Method for interleaving a program over a plurality of cells
US8250503B2 (en) 2006-01-18 2012-08-21 Martin Vorbach Hardware definition method including determining whether to implement a function as hardware or software
US8281108B2 (en) 2002-01-19 2012-10-02 Martin Vorbach Reconfigurable general purpose processor having time restricted configurations
US8301872B2 (en) 2000-06-13 2012-10-30 Martin Vorbach Pipeline configuration protocol and configuration unit communication
USRE44365E1 (en) 1997-02-08 2013-07-09 Martin Vorbach Method of self-synchronization of configurable elements of a programmable module
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
US8812820B2 (en) 2003-08-28 2014-08-19 Pact Xpp Technologies Ag Data processing device and method
US8819505B2 (en) 1997-12-22 2014-08-26 Pact Xpp Technologies Ag Data processor having disabled cores
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements

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US8156312B2 (en) 1996-12-09 2012-04-10 Martin Vorbach Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units
US7822968B2 (en) 1996-12-09 2010-10-26 Martin Vorbach Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs
US8195856B2 (en) 1996-12-20 2012-06-05 Martin Vorbach I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures
US7899962B2 (en) 1996-12-20 2011-03-01 Martin Vorbach I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures
US7650448B2 (en) 1996-12-20 2010-01-19 Pact Xpp Technologies Ag I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures
US7822881B2 (en) 1996-12-27 2010-10-26 Martin Vorbach Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like)
USRE44383E1 (en) 1997-02-08 2013-07-16 Martin Vorbach Method of self-synchronization of configurable elements of a programmable module
USRE45109E1 (en) 1997-02-08 2014-09-02 Pact Xpp Technologies Ag Method of self-synchronization of configurable elements of a programmable module
USRE45223E1 (en) 1997-02-08 2014-10-28 Pact Xpp Technologies Ag Method of self-synchronization of configurable elements of a programmable module
USRE44365E1 (en) 1997-02-08 2013-07-09 Martin Vorbach Method of self-synchronization of configurable elements of a programmable module
US8819505B2 (en) 1997-12-22 2014-08-26 Pact Xpp Technologies Ag Data processor having disabled cores
US6034538A (en) * 1998-01-21 2000-03-07 Lucent Technologies Inc. Virtual logic system for reconfigurable hardware
GB2333625A (en) * 1998-01-21 1999-07-28 Lucent Technologies Inc Virtual logic system for reconfigurable hardware
GB2333625B (en) * 1998-01-21 2001-01-10 Lucent Technologies Inc Virtual logic system for reconfigurable hardware
US6292916B1 (en) 1998-12-10 2001-09-18 Lucent Technologies Inc. Parallel backtracing for satisfiability on reconfigurable hardware
GB2346240B (en) * 1999-01-28 2003-09-03 Nec Corp Programmable device
GB2346240A (en) * 1999-01-28 2000-08-02 Nec Corp Programmable device
US6281703B1 (en) 1999-01-28 2001-08-28 Nec Corporation Programmable device with an array of programmable cells and interconnection network
US8468329B2 (en) 1999-02-25 2013-06-18 Martin Vorbach Pipeline configuration protocol and configuration unit communication
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GB2350456A (en) * 1999-05-13 2000-11-29 Jpc Technology Ltd Data processing
US8726250B2 (en) 1999-06-10 2014-05-13 Pact Xpp Technologies Ag Configurable logic integrated circuit having a multidimensional structure of configurable elements
US8230411B1 (en) 1999-06-10 2012-07-24 Martin Vorbach Method for interleaving a program over a plurality of cells
US8312200B2 (en) 1999-06-10 2012-11-13 Martin Vorbach Processor chip including a plurality of cache elements connected to a plurality of processor cores
GB2391671B (en) * 1999-07-02 2004-04-28 Altera Corp Embedded memory blocks for programmable logic
GB2391671A (en) * 1999-07-02 2004-02-11 Altera Corp Embedded memory blocks for programmable logic
GB2352548A (en) * 1999-07-26 2001-01-31 Sun Microsystems Inc Executing standard functions in a computer system
US6704816B1 (en) 1999-07-26 2004-03-09 Sun Microsystems, Inc. Method and apparatus for executing standard functions in a computer system using a field programmable gate array
GB2352548B (en) * 1999-07-26 2001-06-06 Sun Microsystems Inc Method and apparatus for executing standard functions in a computer system
US8301872B2 (en) 2000-06-13 2012-10-30 Martin Vorbach Pipeline configuration protocol and configuration unit communication
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US9047440B2 (en) 2000-10-06 2015-06-02 Pact Xpp Technologies Ag Logical cell array and bus system
US8471593B2 (en) 2000-10-06 2013-06-25 Martin Vorbach Logic cell array and bus system
US8312301B2 (en) 2001-03-05 2012-11-13 Martin Vorbach Methods and devices for treating and processing data
US8145881B2 (en) 2001-03-05 2012-03-27 Martin Vorbach Data processing device and method
US8099618B2 (en) 2001-03-05 2012-01-17 Martin Vorbach Methods and devices for treating and processing data
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US7657877B2 (en) 2001-06-20 2010-02-02 Pact Xpp Technologies Ag Method for processing data
US8869121B2 (en) 2001-08-16 2014-10-21 Pact Xpp Technologies Ag Method for the translation of programs for reconfigurable architectures
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
US8069373B2 (en) 2001-09-03 2011-11-29 Martin Vorbach Method for debugging reconfigurable architectures
US8209653B2 (en) 2001-09-03 2012-06-26 Martin Vorbach Router
US8407525B2 (en) 2001-09-03 2013-03-26 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
US8429385B2 (en) 2001-09-03 2013-04-23 Martin Vorbach Device including a field having function cells and information providing cells controlled by the function cells
US7840842B2 (en) 2001-09-03 2010-11-23 Martin Vorbach Method for debugging reconfigurable architectures
EP1472616A2 (en) * 2001-09-19 2004-11-03 PACT XPP Technologies AG Reconfigurable elements
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US8281108B2 (en) 2002-01-19 2012-10-02 Martin Vorbach Reconfigurable general purpose processor having time restricted configurations
US8127061B2 (en) 2002-02-18 2012-02-28 Martin Vorbach Bus systems and reconfiguration methods
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US8281265B2 (en) 2002-08-07 2012-10-02 Martin Vorbach Method and device for processing data
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
US8156284B2 (en) 2002-08-07 2012-04-10 Martin Vorbach Data processing method and device
US8803552B2 (en) 2002-09-06 2014-08-12 Pact Xpp Technologies Ag Reconfigurable sequencer structure
US7782087B2 (en) 2002-09-06 2010-08-24 Martin Vorbach Reconfigurable sequencer structure
US7928763B2 (en) 2002-09-06 2011-04-19 Martin Vorbach Multi-core processing system
US8310274B2 (en) 2002-09-06 2012-11-13 Martin Vorbach Reconfigurable sequencer structure
US8812820B2 (en) 2003-08-28 2014-08-19 Pact Xpp Technologies Ag Data processing device and method
EP1610227A1 (en) * 2004-06-24 2005-12-28 Fujitsu Limited Reconfigurable processor with configuration cache and semiconductor device
US8250503B2 (en) 2006-01-18 2012-08-21 Martin Vorbach Hardware definition method including determining whether to implement a function as hardware or software

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GB9516877D0 (en) 1995-10-18 grant

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