ATE109910T1 - Organisation eines integrierten cachespeichers zur flexiblen anwendung zur unterstützung von multiprozessor-operationen. - Google Patents

Organisation eines integrierten cachespeichers zur flexiblen anwendung zur unterstützung von multiprozessor-operationen.

Info

Publication number
ATE109910T1
ATE109910T1 AT89300434T AT89300434T ATE109910T1 AT E109910 T1 ATE109910 T1 AT E109910T1 AT 89300434 T AT89300434 T AT 89300434T AT 89300434 T AT89300434 T AT 89300434T AT E109910 T1 ATE109910 T1 AT E109910T1
Authority
AT
Austria
Prior art keywords
cache
bits
support
organization
integrated cache
Prior art date
Application number
AT89300434T
Other languages
English (en)
Inventor
Gigy Baror
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE109910T1 publication Critical patent/ATE109910T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0837—Cache consistency protocols with software control, e.g. non-cacheable data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
AT89300434T 1988-01-20 1989-01-18 Organisation eines integrierten cachespeichers zur flexiblen anwendung zur unterstützung von multiprozessor-operationen. ATE109910T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14607688A 1988-01-20 1988-01-20

Publications (1)

Publication Number Publication Date
ATE109910T1 true ATE109910T1 (de) 1994-08-15

Family

ID=22515762

Family Applications (1)

Application Number Title Priority Date Filing Date
AT89300434T ATE109910T1 (de) 1988-01-20 1989-01-18 Organisation eines integrierten cachespeichers zur flexiblen anwendung zur unterstützung von multiprozessor-operationen.

Country Status (5)

Country Link
US (2) US5627992A (de)
EP (1) EP0325421B1 (de)
JP (1) JP2881309B2 (de)
AT (1) ATE109910T1 (de)
DE (1) DE68917326T2 (de)

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Also Published As

Publication number Publication date
DE68917326D1 (de) 1994-09-15
JPH01239663A (ja) 1989-09-25
EP0325421A2 (de) 1989-07-26
US5627992A (en) 1997-05-06
DE68917326T2 (de) 1995-03-02
US6014728A (en) 2000-01-11
EP0325421A3 (de) 1991-01-16
EP0325421B1 (de) 1994-08-10
JP2881309B2 (ja) 1999-04-12

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