AU7305491A - Architecture for minimal instruction set computing system - Google Patents
Architecture for minimal instruction set computing systemInfo
- Publication number
- AU7305491A AU7305491A AU73054/91A AU7305491A AU7305491A AU 7305491 A AU7305491 A AU 7305491A AU 73054/91 A AU73054/91 A AU 73054/91A AU 7305491 A AU7305491 A AU 7305491A AU 7305491 A AU7305491 A AU 7305491A
- Authority
- AU
- Australia
- Prior art keywords
- architecture
- computing system
- instruction set
- set computing
- minimal instruction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/3016—Decoding the operand specifier, e.g. specifier format
- G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/3017—Runtime instruction translation, e.g. macros
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
- G06F9/327—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for interrupts
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3858—Result writeback, i.e. updating the architectural state or memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
- G06F9/3871—Asynchronous instruction pipeline, e.g. using handshake signals between stages
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US471962 | 1983-03-03 | ||
US47196290A | 1990-01-29 | 1990-01-29 |
Publications (1)
Publication Number | Publication Date |
---|---|
AU7305491A true AU7305491A (en) | 1991-08-21 |
Family
ID=23873672
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU73054/91A Abandoned AU7305491A (en) | 1990-01-29 | 1991-01-29 | Architecture for minimal instruction set computing system |
Country Status (3)
Country | Link |
---|---|
US (1) | US5675777A (en) |
AU (1) | AU7305491A (en) |
WO (1) | WO1991011765A1 (en) |
Families Citing this family (52)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100329338B1 (en) | 1994-12-02 | 2002-07-18 | 피터 엔. 데트킨 | Microprocessor with packing operation of composite operands |
US7266725B2 (en) | 2001-09-03 | 2007-09-04 | Pact Xpp Technologies Ag | Method for debugging reconfigurable architectures |
US5838960A (en) * | 1996-09-26 | 1998-11-17 | Bay Networks, Inc. | Apparatus for performing an atomic add instructions |
DE19654595A1 (en) | 1996-12-20 | 1998-07-02 | Pact Inf Tech Gmbh | I0 and memory bus system for DFPs as well as building blocks with two- or multi-dimensional programmable cell structures |
US6542998B1 (en) | 1997-02-08 | 2003-04-01 | Pact Gmbh | Method of self-synchronization of configurable elements of a programmable module |
US6505290B1 (en) * | 1997-09-05 | 2003-01-07 | Motorola, Inc. | Method and apparatus for interfacing a processor to a coprocessor |
US5923893A (en) * | 1997-09-05 | 1999-07-13 | Motorola, Inc. | Method and apparatus for interfacing a processor to a coprocessor |
US8686549B2 (en) * | 2001-09-03 | 2014-04-01 | Martin Vorbach | Reconfigurable elements |
DE19861088A1 (en) | 1997-12-22 | 2000-02-10 | Pact Inf Tech Gmbh | Repairing integrated circuits by replacing subassemblies with substitutes |
EP0926589A1 (en) | 1997-12-24 | 1999-06-30 | STMicroelectronics S.r.l. | Processor having internal control instructions |
US6321327B1 (en) * | 1998-12-30 | 2001-11-20 | Intel Corporation | Method for setting a bit associated with each component of packed floating-pint operand that is normalized in SIMD operations |
US7003660B2 (en) | 2000-06-13 | 2006-02-21 | Pact Xpp Technologies Ag | Pipeline configuration unit protocols and communication |
TW463528B (en) * | 1999-04-05 | 2001-11-11 | Idemitsu Kosan Co | Organic electroluminescence element and their preparation |
TW482980B (en) * | 1999-05-31 | 2002-04-11 | Ibm | Hardware device for executing base programmable instructions based upon micro-instructions |
DE10081643D2 (en) * | 1999-06-10 | 2002-05-29 | Pact Inf Tech Gmbh | Sequence partitioning on cell structures |
EP1242874A1 (en) * | 1999-12-31 | 2002-09-25 | Intel Corporation | External microcode |
JP2001216152A (en) * | 2000-01-28 | 2001-08-10 | Rooran:Kk | Logical integrated circuit and computer readable recording medium in which source of its cpu core is recorded |
US8058899B2 (en) | 2000-10-06 | 2011-11-15 | Martin Vorbach | Logic cell array and bus system |
US6708239B1 (en) * | 2000-12-08 | 2004-03-16 | The Boeing Company | Network device interface for digitally interfacing data channels to a controller via a network |
US7444531B2 (en) | 2001-03-05 | 2008-10-28 | Pact Xpp Technologies Ag | Methods and devices for treating and processing data |
US7844796B2 (en) | 2001-03-05 | 2010-11-30 | Martin Vorbach | Data processing device and method |
US9037807B2 (en) | 2001-03-05 | 2015-05-19 | Pact Xpp Technologies Ag | Processor arrangement on a chip including data processing, memory, and interface elements |
US9250908B2 (en) | 2001-03-05 | 2016-02-02 | Pact Xpp Technologies Ag | Multi-processor bus and cache interconnection system |
US9552047B2 (en) | 2001-03-05 | 2017-01-24 | Pact Xpp Technologies Ag | Multiprocessor having runtime adjustable clock and clock dependent power supply |
US9436631B2 (en) | 2001-03-05 | 2016-09-06 | Pact Xpp Technologies Ag | Chip including memory element storing higher level memory data on a page by page basis |
US9141390B2 (en) | 2001-03-05 | 2015-09-22 | Pact Xpp Technologies Ag | Method of processing data with an array of data processors according to application ID |
US9411532B2 (en) | 2001-09-07 | 2016-08-09 | Pact Xpp Technologies Ag | Methods and systems for transferring data between a processing device and external devices |
US10031733B2 (en) | 2001-06-20 | 2018-07-24 | Scientia Sol Mentis Ag | Method for processing data |
US7996827B2 (en) | 2001-08-16 | 2011-08-09 | Martin Vorbach | Method for the translation of programs for reconfigurable architectures |
US7434191B2 (en) | 2001-09-03 | 2008-10-07 | Pact Xpp Technologies Ag | Router |
US8686475B2 (en) * | 2001-09-19 | 2014-04-01 | Pact Xpp Technologies Ag | Reconfigurable elements |
EP1483682A2 (en) | 2002-01-19 | 2004-12-08 | PACT XPP Technologies AG | Reconfigurable processor |
ATE402446T1 (en) | 2002-02-18 | 2008-08-15 | Pact Xpp Technologies Ag | BUS SYSTEMS AND RECONFIGURATION PROCEDURES |
US9170812B2 (en) | 2002-03-21 | 2015-10-27 | Pact Xpp Technologies Ag | Data processing system having integrated pipelined array data processor |
US20110161977A1 (en) * | 2002-03-21 | 2011-06-30 | Martin Vorbach | Method and device for data processing |
US8914590B2 (en) | 2002-08-07 | 2014-12-16 | Pact Xpp Technologies Ag | Data processing method and device |
US7657861B2 (en) | 2002-08-07 | 2010-02-02 | Pact Xpp Technologies Ag | Method and device for processing data |
AU2003286131A1 (en) | 2002-08-07 | 2004-03-19 | Pact Xpp Technologies Ag | Method and device for processing data |
AU2003289844A1 (en) | 2002-09-06 | 2004-05-13 | Pact Xpp Technologies Ag | Reconfigurable sequencer structure |
JP4700611B2 (en) | 2003-08-28 | 2011-06-15 | ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト | Data processing apparatus and data processing method |
JP2009524134A (en) | 2006-01-18 | 2009-06-25 | ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト | Hardware definition method |
AU2007212342B2 (en) * | 2006-02-03 | 2011-05-12 | Russell H. Fish Iii | Thread optimized multiprocessor architecture |
WO2009062496A1 (en) * | 2007-11-17 | 2009-05-22 | Pact Xpp Technologies Ag | Reconfigurable floating-point and bit level data processing unit |
US20110173596A1 (en) * | 2007-11-28 | 2011-07-14 | Martin Vorbach | Method for facilitating compilation of high-level code for varying architectures |
US20110119657A1 (en) * | 2007-12-07 | 2011-05-19 | Martin Vorbach | Using function calls as compiler directives |
US7877582B2 (en) * | 2008-01-31 | 2011-01-25 | International Business Machines Corporation | Multi-addressable register file |
US7849294B2 (en) | 2008-01-31 | 2010-12-07 | International Business Machines Corporation | Sharing data in internal and memory representations with dynamic data-driven conversion |
US9727336B2 (en) | 2011-09-16 | 2017-08-08 | International Business Machines Corporation | Fine-grained instruction enablement at sub-function granularity based on an indicated subrange of registers |
US9411585B2 (en) | 2011-09-16 | 2016-08-09 | International Business Machines Corporation | Multi-addressable register files and format conversions associated therewith |
US8838888B2 (en) | 2012-03-19 | 2014-09-16 | International Business Machines Corporation | Conditional write processing for a cache structure of a coupling facility |
US11841822B2 (en) | 2019-04-27 | 2023-12-12 | Cambricon Technologies Corporation Limited | Fractal calculating device and method, integrated circuit and board card |
WO2020220935A1 (en) * | 2019-04-27 | 2020-11-05 | 中科寒武纪科技股份有限公司 | Operation apparatus |
Family Cites Families (24)
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US3700873A (en) * | 1970-04-06 | 1972-10-24 | Ibm | Structured computer notation and system architecture utilizing same |
US4040031A (en) * | 1973-04-13 | 1977-08-02 | Compagnie Honeywell Bull (Societe Anonyme) | Computer instruction control apparatus and method |
DE2747304C3 (en) * | 1977-10-21 | 1981-03-26 | IBM Deutschland GmbH, 70569 Stuttgart | Micro-command control device |
US4442488A (en) * | 1980-05-05 | 1984-04-10 | Floating Point Systems, Inc. | Instruction cache memory system |
US4376976A (en) * | 1980-07-31 | 1983-03-15 | Sperry Corporation | Overlapped macro instruction control system |
US4454580A (en) * | 1981-09-16 | 1984-06-12 | International Business Machines Corporation | Program call method and call instruction execution apparatus |
US4594659A (en) * | 1982-10-13 | 1986-06-10 | Honeywell Information Systems Inc. | Method and apparatus for prefetching instructions for a central execution pipeline unit |
US4626988A (en) * | 1983-03-07 | 1986-12-02 | International Business Machines Corporation | Instruction fetch look-aside buffer with loop mode control |
US4635194A (en) * | 1983-05-02 | 1987-01-06 | International Business Machines Corporation | Instruction buffer bypass apparatus |
US4569016A (en) * | 1983-06-30 | 1986-02-04 | International Business Machines Corporation | Mechanism for implementing one machine cycle executable mask and rotate instructions in a primitive instruction set computing system |
US4589087A (en) * | 1983-06-30 | 1986-05-13 | International Business Machines Corporation | Condition register architecture for a primitive instruction set machine |
US4589065A (en) * | 1983-06-30 | 1986-05-13 | International Business Machines Corporation | Mechanism for implementing one machine cycle executable trap instructions in a primitive instruction set computing system |
US4566063A (en) * | 1983-10-17 | 1986-01-21 | Motorola, Inc. | Data processor which can repeat the execution of instruction loops with minimal instruction fetches |
US4729093A (en) * | 1984-09-26 | 1988-03-01 | Motorola, Inc. | Microcomputer which prioritizes instruction prefetch requests and data operand requests |
US4714994A (en) * | 1985-04-30 | 1987-12-22 | International Business Machines Corp. | Instruction prefetch buffer control |
US4739471A (en) * | 1985-06-28 | 1988-04-19 | Hewlett-Packard Company | Method and means for moving bytes in a reduced instruction set computer |
US4761731A (en) * | 1985-08-14 | 1988-08-02 | Control Data Corporation | Look-ahead instruction fetch control for a cache memory |
US4734852A (en) * | 1985-08-30 | 1988-03-29 | Advanced Micro Devices, Inc. | Mechanism for performing data references to storage in parallel with instruction execution on a reduced instruction-set processor |
JP2610821B2 (en) * | 1986-01-08 | 1997-05-14 | 株式会社日立製作所 | Multi-processor system |
US4766566A (en) * | 1986-08-18 | 1988-08-23 | International Business Machines Corp. | Performance enhancement scheme for a RISC type VLSI processor using dual execution units for parallel instruction processing |
US4851990A (en) * | 1987-02-09 | 1989-07-25 | Advanced Micro Devices, Inc. | High performance processor interface between a single chip processor and off chip memory means having a dedicated and shared bus structure |
US4926323A (en) * | 1988-03-03 | 1990-05-15 | Advanced Micro Devices, Inc. | Streamlined instruction processor |
US5050068A (en) * | 1988-10-03 | 1991-09-17 | Duke University | Method and apparatus for using extracted program flow information to prepare for execution multiple instruction streams |
US5201056A (en) * | 1990-05-02 | 1993-04-06 | Motorola, Inc. | RISC microprocessor architecture with multi-bit tag extended instructions for selectively attaching tag from either instruction or input data to arithmetic operation output |
-
1991
- 1991-01-29 WO PCT/US1991/000587 patent/WO1991011765A1/en unknown
- 1991-01-29 AU AU73054/91A patent/AU7305491A/en not_active Abandoned
-
1995
- 1995-05-22 US US08/445,973 patent/US5675777A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US5675777A (en) | 1997-10-07 |
WO1991011765A1 (en) | 1991-08-08 |
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